Cypress Semiconductor CYS25G0101DX-ATC User manual

Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
March 19, 2002
CYS25G0101DX-ATC Evaluation Board
User’s Guide
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CYS25G0101DX-ATC Evaluation Board User’s Guide
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Table of Contents
1. Introduction ....................................................................................................................................... 4
2. Features ............................................................................................................................................. 4
3. Kit Contents ...................................................................................................................................... 4
4. Functional Description ..................................................................................................................... 4
5. Diagnostic Modes ........................................................................................................................... 12
5.1 Diagnostic Loopback Mode ..................................................................................................... 12
5.2 Line Loopback ........................................................................................................................... 13
5.3 Analog Line Loopback .............................................................................................................. 14
5.4 “Parallel Line Loopback” (TEST0) Mode ................................................................................ 15
5.4.1 Test the Internal RX CDR PLL Only ................................................................................ 15
5.4.2 Test the Internal RX CDR PLL and TX PLL .................................................................... 15
6. Testing Hookup ............................................................................................................................... 16
6.1 Set-up for BERT Test ................................................................................................................ 16
6.2 Set-up for Eye Diagram Test .................................................................................................... 17
6.3 SONET Jitter Transfer and Jitter Tolerance Test ................................................................... 18
6.4 Set-up for Testing the TX PLL in Parallel Line Loopback Mode ........................................... 19
7. Eye Diagram Testing Result .......................................................................................................... 20
8. Jitter Transfer Testing Result ........................................................................................................ 21
9. Jitter Tolerance Testing Result ..................................................................................................... 22
10. Schematic Diagram, PCB Layout and BOM (Bill of Material) ................................................... 23
Appendix A: Schematic Diagrams of the CYS25G0101DX Evaluation Board ............................... 24
Appendix B: PCB Layout Diagrams of the CYS25G0101DX Evaluation Board ............................ 32
Appendix C: CYS25G0101DX Evaluation Board LVPECL BOM (Bill of Material) ......................... 42
Appendix D: CYS25G0101DX Evaluation Board HSTL BOM (Bill of Material) .............................. 47
List of Figures
Figure 1. The Block Diagram of the CYS25G0101DX ......................................................................... 5
Figure 2. The CYS25G0101DX Evaluation Board ................................................................................ 6
Figure 3. The Jumper Orientations of the CYS25G0101DX ............................................................. 11
Figure 4. Diagnostic Loopback Mode Data Path .............................................................................. 12
Figure 5. Line Loopback Mode Data Path .........................................................................................13
Figure 6. Analog Line Loopback Mode Data Path ............................................................................ 14
Figure 7. Parallel Loopback (TEST0) Mode Data Path ..................................................................... 15
Figure 8. Equipment Set-up for BERT Test .......................................................................................16
Figure 9. Equipment Set-up For Eye Diagram Test .......................................................................... 17
Figure 10. Equipment Set-up For Jitter Test ..................................................................................... 18
Figure 11. Equipment Set-up For Testing the TX PLL in Parallel Line Loopback Mode ............... 19
Figure 12. CYS25G0101DX Evaluation Board Eye Diagram ............................................................ 20
Figure 13. CYS25G0101DX Evaluation Board GR-253 Jitter Transfer Testing Result .................. 21
Figure 14. CYS25G0101DX Evaluation Board G958 Jitter Transfer Testing Result ...................... 21
Figure 15. CYS25G0101DX Evaluation Board GR-253 JitterTolerance Testing Result ................. 22
Figure 16. CYS25G0101DX Evaluation Board G825 Jitter Tolerance Testing Result .................... 22
Figure 17. Top Level of CYS25G0101DX Evaluation Board Schematic Diagram ......................... 25
Figure 18. Parallel Output Block Schematic Diagram ...................................................................... 26
Figure 19. Parallel Input Block Schematic Diagram ......................................................................... 27
Figure 20. Signals Block Schematic Diagram ................................................................................... 28
Figure 21. Power Supply Block Schematic Diagram ........................................................................ 29
Figure 22. Control Block Schematic Diagram ................................................................................... 30
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List of Figures(continued)
Figure 23. Reference Clock Block Schematic Diagram ................................................................... 31
Figure 24. CYS25G0101DX Evaluation Board PCB Mechanical Drawing ....................................... 33
Figure 25. CYS25G0101DX Evaluation Board PCB Top Layer Silk Screen .................................... 34
Figure 26. CYS25G0101DX Evaluation Board PCB Top Layer Layout ........................................... 35
Figure 27. CYS25G0101DX Evaluation Board PCB Top Layer Solder Mask .................................. 36
Figure 28. CYS25G0101DX Evaluation Board PCB Power Plane Layout ....................................... 37
Figure 29. CYS25G0101DX Evaluation Board PCB Ground Plane Layout ..................................... 38
Figure 30. CYS25G0101DX Evaluation Board PCB Bottom Silk Screen ........................................ 39
Figure 31. CYS25G0101DX Evaluation Board PCB Bottom Layer Layout ..................................... 40
Figure 32. CYS25G0101DX Evaluation Board PCB Bottom Solder Mask ....................................... 41
List of Tables
Table 1. Functional Description of the Connectors ............................................................................ 6
Table 2. Pin Assignment of J1 Header and Description of J10 Header ............................................ 7
Table 3. Pin Assignment of J2 Header and Description of J9 Header .............................................. 8
Table 4. Functional Description of DIP Switch 1 (SW1) ..................................................................... 9
Table 5. Functional Description of J4 Connector ............................................................................. 10
Table 6. Description of LED Indicators .............................................................................................. 10
Table 7. Operation Specification of CYS25G0101DX Evaluation Board ......................................... 23
Table 8. CYS25G0101DX Evaluation Board LVPECL BOM - Page 1 of 4 ........................................ 43
Table 9. CYS25G0101DX Evaluation Board LVPECL BOM - Page 2 of 4 ........................................ 44
Table 10. CYS25G0101DX Evaluation Board LVPECL BOM - Page 3 of 4 ..................................... 45
Table 11. CYS25G0101DX Evaluation Board LVPECL BOM - Page 4 of 4 ..................................... 46
Table 12. CYS25G0101DX Evaluation Board HSTL BOM - Page 1 of 4 .......................................... 48
Table 13. CYS25G0101DX Evaluation Board HSTL BOM - Page 2 of 4 .......................................... 49
Table 14. CYS25G0101DX Evaluation Board HSTL BOM - Page 3 of 4 .......................................... 50
Table 15. CYS25G0101DX Evaluation Board HSTL BOM - Page 4 of 4 .......................................... 51
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1. Introduction
Cypress'sCYS25G0101DXSONETOC-48Transceiverisacommunicationsbuildingblockforhigh-speedSONETdatacommunica-
tions.Itprovidescompleteparallel-to-serialandserial-to-parallelconversions,clockgeneration,andclockanddatarecoveryopera-
tionsinasinglechip,optimizedforfullSONET/SDHcompliance.TheCYS25G0101DXEvaluationBoardisdesignedforevaluatingas
well as understanding the characteristics of the CYS25G0101DX SONET/SDH Transceiver. The CYS25G0101DX SONET/SDH
TransceiverEvaluationBoardprovidesthefollowingadvantages.
2. Features
• Flexibleandeasytooperate
• On-boardCypress120-pinTQFPCYS25G0101DXSONET/SDHTransceiver
• SupportsLVPECLandHSTLinterfaces
• Dipswitchforselectingdifferentdiagnosticmodes
• Fourdiagnosticmodes–DiagnosticLoopbackmode,LineLoopbackmode,AnalogLineLoopbackmode,andfactoryTEST0
(ParallelLineLoopback)mode
• LFIandFIFO_ERRLEDs
• OnboardoscillatorfortheREFCLK
• SupportsexternalclocksourcefortheREFCLK
• 16-bitRxD,16-bitTxDbus,RXCLK,TXCLKI,TXCLKOinterface
• SMAconnectorsforCMLinputandoutputbuffers
• SeparateBananaJacksforallvoltagesourcesformeasuringcurrentindividually
3. Kit Contents
• CYS25G0101DXEvaluationBoard
• CertificateofCompliance
• CYS25G0101DXEvaluationKitCD
— UsersGuide
— ApplicationNotes
— DataSheet
4. Functional Description
This board can be used to test the CYS25G0101DX in various modes, such as TEST0 (parallel line loopback mode), LINELOOP,
LOOPA and LOOPTIME. The REFCLK of the CYS25G0101DX is connected to the onboard 155.52-MHz oscillator. The on-board
REFCLK can be replaced by connecting the external reference clock source to J17 and J18. To use the external reference clock
source,theC400andC401(0.01-µFcap)havetoberemovedandplacedonC402andC403positions.Also,theP2,CLKVCC,hasto
bedisconnectedfromthepowersupply(orpowerdown).TheCYS25G0101DXEvaluationBoardprovidesanoptionalopticalmodule
interfaceforconnectingtoanopticalmoduledaughtercard.
The block diagram of the CYS25G0101DX is shown in Figure 1. The detailed functional description can be found in the
CYS25G0101DXdatasheet.Figure 2 showsthepictureoftheCYS25G0101DXEvaluationBoardandthelocationofthejumpers.
Table 1 isthedescriptionofalljumpersandconnectors.Thebusconnectors,J1andJ2,areusedtoconnecttothe16-bitRxDandTxD
busesfortransferringandreceivingtheparalleldata.Table 2 andTable 3 arethepindefinitionsofJ1andJ2.Amulti-functioneight-po-
sitionDipswitchprovidestheselectionofthedifferentdiagnosticmodesaswellasthecontrolfunctions.Table 4 isthefunctionalde-
scriptionoftheDipswitchSW1.TheTEST0jumper,J6,whenclosed,isusedtoenablethefactoryTEST0(ParallelLineLoopBack)
mode.Inthe“ParallelLineLoopBack”mode,paralleloutputbuffersareinternallyjumpedtotheparallelinputbuffers.Thereisnoneed
touseexternaljumpersfortheheaders.J13,J14,J15,J16andJ4areDifferentialCMLinputandoutputandpowersupplyfortheoption-
alopticalmoduledaughtercard.Table 5 idescribestheopticalmoduleinterfaceandTable 6 idescribestheLED.Figure 3 showsthe
jumperorientationsoftheCYS25G0101DXEvaluationBoard.
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Figure 1. The Block Diagram of the CYS25G0101DX
TXD
15:0
TX PLL
x16
/16
RXD
15:0
(155.52MHz)
REFCLK
(155.52MHz)
RXCLKOUT
SHIFTER RX CDR
PLL
TXCLKO
Input
Register
Output
Register
FIFO
(5byte)
SHIFTER
(155.52MHz)
TXCLKI
/16
DIAGLOOP
LINELOOP
LOOPA
IN±
OUT±
Lock-to-Data /
Clock Control
Logic
LOOPTIME
FIFO_RST FIFO_ERR
RESETLFISDLOCKREFPWRDN
Retimed
Data
Recovered
Bit-Clock
Lock-to-Ref
Tx Bit-Clock
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Figure 2. The CYS25G0101DX Evaluation Board
Table 1. Functional Description of the Connectors
Jumpers and
Connectors Name Description
J1 RxDBUS 16-bitRxDDataBusinterfaceheader(seeTable 2 fordetails).Figure 3 showstheorienta-
tionofthisheader
J2 TxDBUS 16-bitTxDDataBusinterfaceheader(seeTable 3 fordetails).Figure 3 showstheorienta-
tionofthisheader
J3 TxCLKO_H HeaderforCYS25G0101DX’sTXCLKO(pin79)andGND.Figure 3 showstheorientation
ofthisjumper
J4 OPTICPOWER Powersupplyforexternalopticalmodule(seeTable 5 fordetails)
SMA13 SMA14 SMA16 SMA15
SW1
J7
D2
J8
J1
SMA11
P1
D1
J6
P4
J5
P5
SMA12
J3
P3
SMA18
P2
SMA17
SMA10
J2
P5
J4
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J5 SD ThisjumperisusedtosettheSDsignal.Whenopen(default),SDsignalwillbedrivenbythe
opticalmodule.When1-2areshorted,SDisforcedtoHIGH.When2-3areshorted,SDis
forcedtoLOW.Figure 3showstheorientationofthisjumper
J6 TEST0 Thisjumper,whenshorted,istoenabletheParallelLineLoopbackmode.
J7 LFI TestTapforCYS25G0101DX’sLFI(pin1).Figure 3 showstheorientationofthisjumper
J8 FIFO_ERR TestTapforCYS25G0101DX’sLIFO(pin51).Figure 3 showstheorientationofthisjumper
SMA10 TXCLKI OptionalSMAconnectorforCYS25G0101DX’sTXCLKI(pin57).R37 need to be popu-
lated, if this connector is used
SMA11 RXCLK OptionalSMAconnectorforCYS25G0101DX’sRXCLK(pin24).C118, R118, R138 and
R158 need to be populated and C116, R116, and R136 need to be unpopulated, if
this connector is used
SMA12 TXCLKO OptionalSMAconnectorforCYS25G0101DX’sTXCLKO(pin79).C119, R119, R139 and
R159 need to be populated and C117, R117, and R137 need to be unpopulated, if
this connector is used
SMA13 IN+ SMAconnectorforCYS25G0101DX’sIN+(pin109).Thisconnectorisalsofortheoptional
opticalmoduleinterface
SMA14 IN- SMAconnectorforCYS25G0101DX’sIN–(pin108).Thisconnectorisalsofortheoptional
opticalmoduleinterface
SMA15 OUT- SMAconnectorforCYS25G0101DX’sOUT–(pin104).Thisconnectorisalsofortheoption-
alopticalmoduleinterface
SMA16 OUT+ SMAconnectorforCYS25G0101DX’sOUT+(pin103).Thisconnectorisalsofortheoption-
alopticalmoduleinterface
SMA17 REFCLKP OptionalSMAconnectorforCYS25G0101DX’sREFCLK+(pin87).Thisconnectorisforus-
ingtheexternalreferenceclockinsteadofusingthe“on-board”oscillator(155.52MHz).To
use the external reference clock, C400 and C401 (0.01-µF cap) have to be removed
and placed on C402 and C403 positions. Also, The CLKVCC, P2, has to be discon-
nected from the power supply
SMA18 REFCLKN OptionalSMAconnectorforCYS25G0101DX’sREFCLK+(pin87).Thisconnectorisforus-
ingtheexternalreferenceclockinsteadofusingthe“on-board”oscillator(155.52MHz).To
use the external reference clock, C400 and C401 (0.01-µF cap) have to be removed
and placed on C402 and C403 positions. Also, The CLKVCC, P2, has to be discon-
nected from the power supply
P1 GND PowerGround.Forexternalpowersupply
P2 CLKVCC Powersupply-+3.3Vfortheclockoscillator
P3 VDDQ Powersupply-+3.3VforLVPECLoutput.+1.5VforHSTLoutputs
P4 VCC_OPTIC Powersupply-+3.3Vfortheoptionalopticalmodule
P5 VCC Powersupply-+3.3Vfordigitalandlow-speedI/Ofunction
P6 V_Par Powersupply-+3.3VforLVPECLoutput.+1.5VforHSTLoutputs
Table 2. Pin Assignment of J1 Header and Description of J10 Header
Pin Number Name I/O Characteristics Description
1 RXD15 HSTLoutput ParallelreceivedataoutputRXD15.Theoutputschangefollowing
RXCLK↓
3 RXD14 HSTLoutput ParallelreceivedataoutputRXD14.Theoutputschangefollowing
RXCLK↓
Table 1. Functional Description of the Connectors (continued)
Jumpers and
Connectors Name Description
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5 RXD13 HSTLoutput ParallelreceivedataoutputRXD13.Theoutputschangefollowing
RXCLK↓
7 RXD12 HSTLoutput ParallelreceivedataoutputRXD12.Theoutputschangefollowing
RXCLK↓
9 RXD11 HSTLoutput ParallelreceivedataoutputRXD11.Theoutputschangefollowing
RXCLK↓
11 RXD10 HSTLoutput ParallelreceivedataoutputRXD10.Theoutputschangefollowing
RXCLK↓
13 RXD9 HSTLoutput ParallelreceivedataoutputRXD9.TheoutputschangefollowingRX-
CLK↓
15 RXD8 HSTLoutput ParallelreceivedataoutputRXD8.TheoutputschangefollowingRX-
CLK↓
17 RXD7 HSTLoutput ParallelreceivedataoutputRXD7.TheoutputschangefollowingRX-
CLK↓
19 RXD6 HSTLoutput ParallelreceivedataoutputRXD6.TheoutputschangefollowingRX-
CLK↓
21 RXD5 HSTLoutput ParallelreceivedataoutputRXD5.TheoutputschangefollowingRX-
CLK↓
23 RXD4 HSTLoutput ParallelreceivedataoutputRXD4.TheoutputschangefollowingRX-
CLK↓
25 RXD3 HSTLoutput ParallelreceivedataoutputRXD3.TheoutputschangefollowingRX-
CLK↓
27 RXD2 HSTLoutput ParallelreceivedataoutputRXD2.TheoutputschangefollowingRX-
CLK↓
29 RXD1 HSTLoutput ParallelreceivedataoutputRXD1.TheoutputschangefollowingRX-
CLK↓
31 RXD0 HSTLoutput ParallelreceivedataoutputRXD0.TheoutputschangefollowingRX-
CLK↓
2,4,6,8,10,
12,14,16,18,
20,22,24,26,
28,30,32
GND Ground Ground
J10 RXCLK HSTLoutput Receiveclockoutput.Thisclockisdividedby16ofthebit-rateclock
extractedfromthereceivedserialstream
Table 3. Pin Assignment of J2 Header and Description of J9 Header
Pin Number Name I/O Characteristics Description
1,3,5,7,9,11,
13,15,17,19,
21,23,25,27,
29,31
GND Ground Ground
2 TXD15 HSTLoutput ParalleltransmitdatainputTXD15.TheinputdataissampledbyTX-
CLKI↑
4 TXD14 HSTLinput ParalleltransmitdatainputTXD14.TheinputdataissampledbyTX-
CLKI↑
6 TXD13 HSTLinput ParalleltransmitdatainputTXD13.TheinputdataissampledbyTX-
CLKI↑
Table 2. Pin Assignment of J1 Header and Description of J10 Header (continued)
Pin Number Name I/O Characteristics Description
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8 TXD12 HSTLinput ParalleltransmitdatainputTXD12.TheinputdataissampledbyTX-
CLKI↑
10 TXD11 HSTLinput ParalleltransmitdatainputTXD10.TheinputdataissampledbyTX-
CLKI↑
12 TXD10 HSTLinput ParalleltransmitdatainputTXD9.TheinputdataissampledbyTX-
CLKI↑
14 TXD9 HSTLinput ParalleltransmitdatainputTXD8.TheinputdataissampledbyTX-
CLKI↑
16 TXD8 HSTLinput ParalleltransmitdatainputTXD8.TheinputdataissampledbyTX-
CLKI↑
18 TXD7 HSTLinput ParalleltransmitdatainputTXD7.TheinputdataissampledbyTX-
CLKI↑
20 TXD6 HSTLinput ParalleltransmitdatainputTXD6.TheinputdataissampledbyTX-
CLKI↑
22 TXD5 HSTLinput Paralleltransmitdata‘inputTXD5.TheinputdataissampledbyTX-
CLKI↑
24 TXD4 HSTLinput ParalleltransmitdatainputTXD4.TheinputdataissampledbyTX-
CLKI↑
26 TXD3 HSTLinput ParalleltransmitdatainputTXD3.TheinputdataissampledbyTX-
CLKI↑
28 TXD2 HSTLinput ParalleltransmitdatainputTXD2.TheinputdataissampledbyTX-
CLKI↑
30 TXD1 HSTLinput ParalleltransmitdatainputTXD1.TheinputdataissampledbyTX-
CLKI↑
32 TXD0 HSTLinput ParalleltransmitdatainputTXD0.TheinputdataissampledbyTX-
CLKI↑
J9 TXCLKI HSTLinput Paralleltransmitdatainputclock
Table 4. Functional Description of DIP Switch 1 (SW1)
Position Name State Description
1 RESET ON* DisableReset-Normaloperation
OFF ResetforalllogicfunctionsexceptthetransmitFIFO
2 DIAGLOOP ON Transmitdata(fromTXD[15:0])isroutedthroughthereceiveclock
anddatarecoveryandpresentedatRXD[15:0]output
OFF* Receivedserialdata(fromIN±)isroutedthroughthereceiveclockand
datarecoveryandpresentedatRXD[15:0]output
3,4 LINELOOP,
LOOPA ON ON Invalidsetting
ON OFF Receivedserialdataisloopedbackfromreceiveinput(IN±)totrans-
mitoutput(OUT±)after being reclocked by the recovered clock
OFF ON Receivedserialdataisloopedbackfromreceiveinput(IN±)totrans-
mitoutput(OUT±),but is not routed through the clock and data
recovery PLL
OFF* OFF* Disableserialdataloopback.
Table 3. Pin Assignment of J2 Header and Description of J9 Header (continued)
Pin Number Name I/O Characteristics Description
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5 LOOPTIME ON Thetransmissionwillbeusingtheextractedreceivebit-clockforthe
transmittedbitclock
OFF* ThetransmissionwillbeusingtheREFCLKinput(155.52MHz),which
ismultipliedby16,togeneratethetransmittedbitclock
6 LOCKREF ON* ThereceivePLLlockstoserialdatastream
OFF ThereceivePLLlockstotheREFCLK
7 PWRDN ON* DisablePowerDown-NormalOperation
OFF EnableDevicePowerDownmode.Allthelogicanddriversaredis-
abledandplacedintoastandbyconditionwhereonlyminimalpoweris
dissipated
8 FIFO_RST ON* DisableFIFOreset-NormalOperation
OFF ResetthetransmitFIFOpointers.Theinandoutpointersofthetrans-
mitFIFOareresettothemaximumseparation
Table 5. Functional Description of J4 Connector
Pin Name Description
1A,1B,3A,3B VCC_OPTIC Powersupplyforopticalmodule
2A,2B,4A,4B GND Powerground
5A NC NoConnection
5B SD SDsignalfromopticalmodule
Table 6. Description of LED Indicators
LED Name LED Status Description
D1 FIFO_ERR ON ThetransmitFIFOhaseitherunderoroverflowed.TheFIFO
mustberesettocleartheerror(byswitchingtheDIPswitch
SW1-8toOFFandthenON.SeeTable 4 fordetails)
OFF IndicatestheFIFOhasneitherunderoroverflowed
D2 LFI ON IndicatesnoLineFault.ItwillappeartobeONevenwhenLFIis
toggling.InsuchacaseobserveLFIusingascopeonJ7
OFF Indicatestheselectedreceivedatastreamhasbeendetectedan
invalideitherLOWinputonSDorbythereceiveVCObeingoper-
atedoutsideitsspecifiedlimits
Table 4. Functional Description of DIP Switch 1 (SW1) (continued)
Position Name State Description
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Figure 3. The Jumper Orientations of the CYS25G0101DX
J7
J8
LFI
GND
GND
FIFO_ERR
RXCLK
GND
J1
Pin 1
Pin 1
GND
GND
TXCLKO
TXCLKI
J2
1
2
3
J5
5B
1B
1A
5A
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5. Diagnostic Modes
The CYS25G0101DX Evaluation Board provides four different diagnostic modes—Diagnostic Loopback mode, Line Loopback
mode,AnalogLoopbackmodeand“ParallelLineLoopback”mode.Figure 4 toFigure 7 illustratethesediagnosticmodesandFigure
8toFigure 10 illustratethetestingequipmentset-upfortestingthecharacteristicsoftheCYS25G0101DX.
5.1 Diagnostic Loopback Mode
IntheDiagnosticLoopbackmode,paralleldatawillloopthroughtheinputbuffer,serializer,CDRblock,deserializerandtheoutputbuff-
er.Figure 4 showsthedatapath(boldline)oftheDiagnosticLoopbackmode.ToselecttheDiagnosticLoopbackmode:
1. SW1-2(DIAGLOOP)mustbeinONposition,SW1-3(LINELOOP)
2. AllotherdipswitchesmustbeintheirdefaultpositionsasstatedinTable 4
3. TEST0,jumperJ6mustbeopened
4. ApplytheTestingHookupillustratedinFigure 8 toFigure 10
Figure 4. Diagnostic Loopback Mode Data Path
TXD
15:0
TX PLL
x16
/16
RXD
15:0
REFCLK RXCLKOUT
SHIFTER RX CDR
PLL
TXCLK
Input
Register
Output
Register
FIFO
(5byte) SHIFTER
TXCLKIN
/16
DIAGLOOP
(SW1-2) = ON
LINELOOP
SW1-3 = OFF
LOOPA
SW1-4 = OFF
IN±
OUT±
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5.2 Line Loopback
In the Line Loopback mode, serial data (from IN±) will loop through the serial input buffer and CDR block to the serial output buffer
(OUT±).Figure 5 showsthedatapath(boldline)oftheLineLoopbackmode.ToselecttheLineLoopbackmode:
1. SW1-3(LINELOOP)mustbeinONposition
2. AllotherdipswitchsettingsmustbeintheirdefaultpositionsasstatedinTable 4
3. TEST0,jumperJ6mustbeopened
4. ApplytheTestingHookupillustratedinFigure 8 toFigure 10
Figure 5. Line Loopback Mode Data Path
TXD
15:0
TX PLL
x16
/16
RXD
15:0
SHIFTER RX CDR
PLL
Input
Register
Output
Register
FIFO
(5byte) SHIFTER
/16
RXCLKOUTREFCLKTXCLKTXCLKIN
DIAGLOOP
(SW1-2) = OFF
LINELOOP
SW1-3 = ON
LOOPA
SW1-4 = OFF
IN±
OUT±
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5.3 Analog Line Loopback
IntheAnalogLineLoopbackmode,serialdata(from IN±) will loopthroughdirectly fromserial inputbufferto theserial outputbuffer
(OUT±).Figure 6 showsthedatapath(boldline)oftheAnalogLineLoopbackmode.ToselecttheAnalogLineLoopbackmode:
1. SW1-4(LOOPA)mustbeinONpositionandSW1-3(LINELOOP)mustbeinOFFposition.
2. AllotherdipswitchesmustbeintheirdefaultpositionsasstatedinTable 4
3. TEST0,jumperJ6mustbeopened
4. ApplytheTestingHookupillustratedinFigure 8 toFigure 10
Figure 6. Analog Line Loopback Mode Data Path
TXD
15:0
TX PLL
x16
/16
RXD
15:0
SHIFTER RX CDR
PLL
Input
Register
Output
Register
FIFO
(5byte) SHIFTER
/16
RXCLKOUTREFCLKTXCLKTXCLKIN
DIAGLOOP
(SW1-2) = OFF
LINELOOP
SW1-3 = OFF
LOOPA
SW1-4 = ON
IN±
OUT±
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5.4 “Parallel Line Loopback” (TEST0) Mode
InParallelLineLoopbackmode,theparalleloutputbuffersareinternallylinkedtotheparallelinputbuffers.Figure 7 showsthedata
path(boldline)oftheParallelLineLoopbackmode.Inthistestmode,theinternalRXCDRPLLandTXPLLcanbetestedbydifferent
configurations.
5.4.1 Test the Internal RX CDR PLL Only
1. TEST0,jumperJ6mustbeshorted
2. SW1-5(LOOPTIME)mustbeinONposition
3. Allotherdipswitchesmustbeintheirdefaultpositions(seeTable 4)
4. ApplytheTestingHookupillustratedinFigure 8 toFigure 10forthemeasurement
5.4.2 Test the Internal RX CDR PLL and TX PLL
1. TEST0,jumperJ6mustbeshorted
2. Alldipswitchesmustbeintheirdefaultpositions(seeTable 4)
3. DisconnectCLKVCC(P2),removethe155.52-MHzoscillator,placeC400onC402andC401onC403positions(seeTable
1,jumpersJ17andJ18fordetails)
4. ApplytheTestingHookupillustratedinFigure 11 forthemeasurement
Figure 7. Parallel Loopback (TEST0) Mode Data Path
TXD
15:0
TX PLL
x16
/16
RXD
15:0
REFCLK RXCLKOUT
SHIFTER RX CDR
PLL
TXCLK
Input
Register
Output
Register
FIFO
(5byte) SHIFTER
TXCLKIN
/16
DIAGLOOP
(SW1-2) = OFF
LINELOOP
SW1-3 = OFF
LOOPA
SW1-4 = OFF
IN±
OUT±
JUMPER J6 (TEST0) = CLOSED
TXD
15:0
TX PLL
x16
/16
RXD
15:0
REFCLK RXCLKOUT
SHIFTER RX CDR
PLL
TXCLK
Input
Register
Input
Register
Output
Register
Output
Register
FIFO
(5byte)
FIFO
(5byte) SHIFTER
TXCLKIN
/16
DIAGLOOP
(SW1-2) = OFF
LINELOOP
SW1-3 = OFF
LOOPA
SW1-4 = OFF
IN±
OUT±
JUMPER J6 (TEST0) = CLOSED
[+] Feedback

CYS25G0101DX-ATC Evaluation Board User’s Guide
16
6. Testing Hookup
6.1 Set-up for BERT Test
Figure 8 illustratestheset-upfortheBERTtest.Theequipmentlist:
1. EvaluationBoard–CypressCYS25G0101DXEvaluationBoard
2. PatternGenerator–TektronixD3186PatternGenerator
3. ErrorDetector–TektronixD3286ErrorDetector
4. PowerSupply–HPE3631ADCPowerSupply
*Allequipmentinthelistisforreferenceonly
Figure 8. Equipment Set-up for BERT Test
IN+ IN- OUT-OUT+
Tektronix D3186
Pattern Generator
Cypress CYS25G0101DX
Evaluation Board
Tektronix D3286
Pattern Analyzer
CLK2 50ΩTerminator
For OUT-
HP E3631A
Power Supply
[+] Feedback

CYS25G0101DX-ATC Evaluation Board User’s Guide
17
6.2 Set-up for Eye Diagram Test
Figure 9 illustratestheset-upfortestingtheEyeDiagram.Theequipmentlist:
1. EvaluationBoard–CypressCYS25G0101DXEvaluationBoard
2. PatternGenerator–TektronixD3186PatternGenerator
3. Oscilloscope–AgilentInfiniiumDCA86100Awith83484ADual-Channel50GHzModule
4. PowerSupply–HPE3631ADCPowerSupply
*Allequipmentinthelistisforreferenceonly
Figure 9. Equipment Set-up For Eye Diagram Test
Trigger
IN+ IN- OUT-OUT+
Tektronix D3186 Pattern Generator Agilent Infinium DAC 86100A Oscilloscope
with 8348A Dual-Channel 50GHz Module
HP E3631A
Power Supply
Cypress CYS25G0101DX
Evaluation Board
Trigger Out
[+] Feedback

CYS25G0101DX-ATC Evaluation Board User’s Guide
18
6.3 SONET Jitter Transfer and Jitter Tolerance Test
Figure 10 illustratestheset-upfortestingthejitter.Theequipmentlist:
1. EvaluationBoard–CypressCYS25G0101DXEvaluationBoard
2. SONETTester–Agilent(HP)OmniBER718CommunicationPerformanceAnalyzer
3. OpticalConverters-Agilent(HP)83446AReceiverand83430ATransmitter
4. PowerSupply–HPE3631ADCPowerSupply
*Allequipmentinthelistisforreferenceonly
Figure 10. Equipment Set-up For Jitter Test
HP OmniBER 718
Communications
Performance Analyzer
HP E3631A
Power Supply
Analog to Optical
Converter (i.e. HP’s 83430A)
Optical to Analog
Converter
(i.e. HP’s 83446A)
Cypress CYS25G0101DX
Evaluation Board
[+] Feedback

CYS25G0101DX-ATC Evaluation Board User’s Guide
19
6.4 Set-up for Testing the TX PLL in Parallel Line Loopback Mode
Figure 11 illustratestheset-upfortestingtheTXPLLinParallelLineLoopbackMode.Theequipmentlist:
1. EvaluationBoard–CypressCYS25G0101DXEvaluationBoard
2. PatternGenerator–TektronixD3186PatternGenerator
3. ErrorDetector–TektronixD3286ErrorDetector
4. PulseGenerator-HP8133APulseGenerator
5. PowerSupply–HPE3631ADCPowerSupply
*Allequipmentinthelistisforreferenceonly
Figure 11. Equipment Set-up For Testing the TX PLL in Parallel Line Loopback Mode
IN+ IN- OUT-OUT+
Tektronix D3186
Pattern Generator
Cypress CYS25G0101DX
Evaluation Board
Tektronix D3286
Pattern Analyzer
CLK2
50ΩTerminator For OUT-
HP E3631A
Power Supply
CLK1
External
Input
External
Input
Output+
Output-
1. Disconnect CLKVCC
2. Remove the OSC
3. Place C400 on C402 and
C401 on C403 positions
HP 8133A Pulse Generator
(configure to Output = Input Clock divided by 16)
[+] Feedback

CYS25G0101DX-ATC Evaluation Board User’s Guide
20
7. Eye Diagram Testing Result
Figure 12 istheEye DiagrammeasurementfromCYS25G0101DXEvaluationBoardbyusingthetestset-up asinFigure 9.Inthis
measurement,theevaluationboardisconfiguredtoparallelloopbackmode(Figure 7)andwithnoSONETfilterattheoscilloscope.
Figure 12. CYS25G0101DX Evaluation Board Eye Diagram
[+] Feedback