Cypress MB90910 Series User manual

MB90911AS/F912BS/V950AMAS
F2MC-16LX MB90910 Series
16-bit Microcontroller
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 002-04578 Rev. *A Revised April 12, 2016
The MB90910 series, loaded 1 channel FULL-CAN controller and Flash ROM, is general-purpose Cypress 16-bit microcontroller
designing for automotive and industrial applications. Its main feature is the on-board CAN controllers, which conform to Ver 2.0 Part
A and Part B, while supporting a very flexible message buffer scheme and so offering more functions than a normal FULL-CAN
approach. With the new 0.18m CMOS technology, Cypress now offers on-chip Flash ROM program memory up to 128 Kbytes.
The power supply (1.8 V) is supplied to the MCU core from an internal regulator circuit. This creates a major advantage in terms of
EMI and power consumption.
The internal PLL clock frequency multiplier provides an internal 31.25 ns instruction execution time from an external 4 MHz clock.
The unit features a 4-channel input capture unit 1 channel 16-bit free-run timer, 2-channel LIN-UART,
1-channel UART, and 16-channel 8/10-bit A/D converter as the peripheral resource.
Features
Clock
■Built-in PLL clock frequency multiplication circuit
■Selection of machine clocks (PLL clocks) is allowed among
frequency division by 2 on oscillation clock and multiplication
of 1 to 8 times of oscillation clock (for 4 MHz oscillation clock,
4 MHz to 32 MHz)
■Minimum execution time of instruction : 31.25 ns (when
operating with 4-MHz oscillation clock and 8-time multiplied
PLL clock)
Instruction system best suited to controller
■16 Mbytes CPU memory space
■24-bit internal addressing
■Wide choice of data types (bit, byte, word, and long word)
■Wide choice of addressing modes (23 types)
■Enhanced multiply-divide instructions with sign and RETI
instructions
■Enhanced high-precision computing with 32-bit accumulator
Instruction system compatible with high-level
language (C language) and multitask
■Employing system stack pointer
■Enhanced various pointer indirect instructions
■Barrel shift instructions
Increased processing speed
4-byte instruction queue
Powerful interrupt function
■Powerful 8-level, 34-condition interrupt feature
■Up to 8 channels external interrupts are supported
CPU-independent automatic data transfer func-
tion
Expanded intelligent I/O service function (EI2OS) : up to 16
channels
Low power consumption (standby) mode
■Sleep mode (a mode that halts CPU operating clock)
■Main timer mode (timebase timer mode that is transferred
from main clock mode)
■PLL timer mode (timebase timer mode that is transferred from
PLL clock mode)
■Stop mode (a mode that stops oscillation clock)
■CPU blocking operation mode
Process
CMOS technology
I/O port
General purpose input/output port (CMOS output) :
- 36 ports
Timer
■Timebase timer, watchdog timer : 1 channel
■8/16-bit PPG timer : 8-bit 6 channels or 16-bit 3 channels
■16-bit reload timer : 2 channels
■16- bit input/output timer
❐-16-bit free-run timer : 1 channel (FRT0 : ICU 0/1/2/3)
❐-16- bit input capture : (ICU) : 4 channels
FULL-CAN controller : 1 channel
■Compliant with CAN specifications Version 2.0 Part A and B
■16 message buffers are built in
■CAN wake-up function
UART (LIN/SCI) : LIN-UART2 channels, UART
1 channel
■Equipped with full-duplex double buffer
■Clock-asynchronous or clock-synchronous serial trans-
mission is available

Document Number: 002-04578 Rev. *A Page 2 of 64
MB90910 Series
DTP/External interrupt : up to 8 channels, CAN
wakeup : up to 1 channel
Module for activation of expanded intelligent I/O service (EI2OS)
and generation of external interrupt by external input
Delay interrupt generator module
Generates interrupt request for task switching
8/10-bit A/D converter : 16 channels
■Resolution is selectable between 8-bit and 10-bit
■Activation by external trigger input is allowed
■Conversion time : 3 s (at 24 MHz machine clock, including
sampling time)
Program patch function
Address matching detection for 6 address pointers
Capable of changing input voltage for port
Automotive/CMOS-Schmitt input level (initial level is Automotive
in single-chip mode)
ROM security function
The content of ROM can be protected (Only MASK ROM
product).
Flash memory security function
Protects the content of Flash memory

Document Number: 002-04578 Rev. *A Page 3 of 64
MB90910 Series
Contents
Product Lineup ................................................................ 4
Pin Assignment ................................................................ 6
Pin Description ................................................................. 7
I/O Circuit Type .............................................................. 10
Handling Devices ............................................................ 15
Block Diagrams .............................................................. 18
Memory Map .................................................................... 20
I/O Map ............................................................................. 21
CAN Controllers .............................................................. 29
Interrupt Factors, Interrupt Vectors,
Interrupt Control Register .............................................. 36
Electrical Characteristics ............................................... 38
Absolute Maximum Ratings ....................................... 38
Recommended Conditions ........................................ 40
DC Characteristics .................................................... 41
AC Characteristics ..................................................... 43
Clock Timing .............................................................. 43
Reset Standby Input .................................................. 45
Power-on Reset ......................................................... 46
UART ......................................................................... 46
Trigger Input Timing .................................................. 51
Timer Related Resource Input Timing ....................... 52
Timer Related Resource Output Timing .................... 52
CAN PLL cycle jitter .................................................. 53
A/D Converter ............................................................ 54
Definition of A/D Converter Terms ........................... 56
Flash Memory Program/Erase Characteristics ......... 59
Ordering Information ..................................................... 60
Package Dimension ........................................................ 61
Major Changes .................................................................62

Document Number: 002-04578 Rev. *A Page 4 of 64
MB90910 Series
1. Product Lineup
(Continued)
Part number
Parameter
MB90V950AMAS MB90F912BS MB90911AS
Type Evaluation product Flash memory product MASK ROM product
CPU F2MC-16LX CPU
System clock On-chip PLL clock multiplier (1, 2, 3, 4, 6, 8, 1/2 when PLL stops)
Minimum instruction execution time : 31.25 ns (4 MHz osc. PLL 8)
ROM External 128 Kbytes 64 Kbytes
RAM 30 Kbytes 8 Kbytes 4 Kbytes
Emulator-specific
power supply*1Yes 
FPGA data*2Rev 050617 
Adaptor board*2MB2147-20 Rev.04C or later 
Technology 0.35 m CMOS with built-in power
supply regulator 0.18 m CMOS with built-in power supply regulator
Operation voltage range 5 V 10 3.0 V to 5.5 V : When normal operating
Operating ambient tem-
perature 40 °C to 105 °C
Package PGA-299 LQFP-48
UART
LIN-UART 7 channels LIN-UART 2 channels, UART 1 channel
Wide range of baud rate settings using a dedicated reload timer
Special synchronous options for adapting to different synchronous serial protocols
LIN functionality working either as master or slave LIN device (Supported by LIN-UART only)
I2C (400 kbps) 2 channels 
A/D converter
24 input channels 16 input channels
10-bit or 8-bit resolution
Conversion time : Min 3 s include sample time (per one channel)
16-bit
Reload timer
4 channels 2 channels
Operation clock frequency : fsys/21, fsys/23, fsys/25(fsys Machine clock frequency)
Supports External Event Count function
16-bit
I/O timer
2 channels 1 channel
Generates an interrupt signal on overflow
Operation clock freq. : fsys, fsys/21, fsys/22, fsys/23, fsys/24, fsys/25, fsys/26, fsys/27
(fsys Machine clock freq.)
I/O Timer 0 (clock input FRCK0) corresponds to ICU0/1/2/3, OCU 0/1/2/3
I/O Timer 1 (clock input FRCK1) corresponds to ICU4/5/6/7, OCU 4/5/6/7
16-bit
Output compare
8 channels 
Generates an interrupt signal when one of the 16-bit I/O timer matches the output compare register
A pair of compare registers can be used to generate an output signal.

Document Number: 002-04578 Rev. *A Page 5 of 64
MB90910 Series
(Continued)
*1: It is setting of Jumper switch (TOOL VCC) when emulator (MB2147-01) is used. Please refer to the Emulator hardware manual
for the details.
*2: Contact the sales or support representative if using other than those above of FPGA data and adaptor boards.
Part number
Parameter
MB90V950AMAS MB90F912BS MB90911AS
16-bit
Input capture
8 channels 4 channels
Rising edge, falling edge or rising & falling edge sensitive
Signals an interrupt upon external event
8/16-bit
PPG
8 channels (16-bit) /16 channels
(8-bit)
Sixteen 8-bit reload counters
Sixteen 8-bit reload registers for L
pulse width
Sixteen 8-bit reload registers for H
pulse width
3 channels (16-bit) /6 channels (8-bit)
Six 8-bit reload counters
Six 8-bit reload registers for L pulse width
Six 8-bit reload registers for H pulse width
Supports 8-bit and 16-bit operation modes
A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as
8-bit prescaler plus 8-bit reload counter
Operating clock freq. : fsys, fsys/21, fsys/22, fsys/23, fsys/24or 128 s@fosc 4 MHz
(fsys Machine clock frequency, fosc Oscillation clock frequency)
CAN
controller
3 channels 1 channel
Conforms to CAN Specification Version 2.0 Part A and B
Automatic re-transmission in case of error
Automatic transmission in response to Remote Frames
Prioritized 16 message buffers for data and ID’s
Supports multiple messages
Flexible configuration of acceptance filtering :
Full bit compare/Full bit mask/Two partial bit masks
Supports up to 1 Mbps
DTP/External
interrupt
(8 channels)
Can be used rising edge, falling edge, starting up by H/L level input, external interrupt,
expanded intelligent I/O services (EI2OS)
D/A Converter 8-bit 2 channels 
I/O Ports
Virtually all external pins can be used as general purpose I/O port
All ports are push-pull outputs
Bit-wise settable as input/output or peripheral signal
Can be configured 8 as CMOS schmitt trigger/ automotive inputs (in blocks of 8 pins)
TTL input level settable for external bus (32-pin only for external bus)
Flash memory
(Flash memory product
only)
Supports automatic programming, Embedded Algorithm
Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the algorithm
Boot block configuration
Erase can be performed on each block
Flash Security

Document Number: 002-04578 Rev. *A Page 6 of 64
MB90910 Series
2. Pin Assignment
■MB90F912BS, MB90911AS
(TOP VIEW)
(FPT-48P-M26)
1
2
3
4
5
6
7
8
9
10
11
12
13 14 15 16 17 18 19 20 21 22 23 24
25
26
27
28
29
30
31
32
33
35
34
36
48 47 46 45 44 43 42 41 40 39 38 37
P66/AN6/PPGC(D)
AVss
RST
Vcc
Vss
C
P40 P41 P82/SIN0/INT14R/TIN2
P50/AN8/SIN2
AVcc
P44/FRCK0
P80/ADTG/INT12R
P51/AN9/SOT2
X0
X1
P67/AN7/PPGE(F)
AVR
P60/AN0
P61/AN1
P62/AN2
P63/AN3
P64/AN4
P65/AN5/PPGA(B) P27/IN3
P26/IN2
P25/IN1
P24/IN0
P23/PPGF(E)*
P22/PPGD(C)*
P21/PPGB(A)*
P20*
MD2 MD1 MD0
P52/AN10/SCK2
P53/AN11/TIN3
P54/AN12/TOT3/INT8
P55/AN13/INT10 P56/AN14/INT11 P57/AN15/INT13
P84/SCK0/INT15R
P83/SOT0/TOT2
P42/RX1/INT9R P43/TX1
P86/SOT1
P87/SCK1
P85/SIN1
LQFP-48
* : High current output port

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MB90910 Series
3. Pin Description
(Continued)
Pin No. Pin name I/O circuit type* Function
1AV
CC IV CC power input pin for analog circuit.
2 AVR Power (Vref) input pin for A/D converter.
It should be below VCC.
3 to 7
P60 to P64
H
General-purpose I/O port.
AN0 to AN4 Analog input pins for A/D converter.
8 to 10
P65 to P67
H
General-purpose I/O port.
AN5 to AN7 Analog input pins for A/D converter.
PPGA (B) ,
PPGC (D) ,
PPGE (F)
Output pins for PPG.
11
P80
F
General-purpose I/O port.
ADTG Trigger input pin for A/D converter.
INT12R External interrupt request input pin for INT12R.
12
P50
L
General-purpose I/O port.
AN8 Analog input pin for A/D converter.
SIN2 Serial data input pin for UART2.
13
P51
H
General-purpose I/O port.
AN9 Analog input pin for A/D converter.
SOT2 Serial data output pin for UART2.
14
P52
H
General-purpose I/O port.
AN10 Analog input pin for A/D converter.
SCK2 Clock I/O pin for UART2.
15
P53
H
General-purpose I/O port.
AN11 Analog input pin for A/D converter.
TIN3 Event input pin for reload timer 3.
16
P54
H
General-purpose I/O port.
AN12 Analog input pin for A/D converter.
TOT3 Output pin for reload timer 3
INT8 External interrupt request input pin for INT8.
17
P55
H
General-purpose I/O port.
AN13 Analog input pin for A/D converter.
INT10 External interrupt request input pin for INT10.

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MB90910 Series
(Continued)
Pin No. Pin name I/O circuit
type* Function
18
P56
H
General-purpose I/O port
(Different I/O circuit type from MB90V950AMAS).
AN14 Analog input pin for A/D converter.
INT11 External interrupt request input pin for INT11.
19
P57
H
General-purpose I/O port
(Different I/O circuit type from MB90V950AMAS).
AN15 Analog input pin for A/D converter.
INT13 External interrupt request input pin for INT13.
20 MD2 D Input pin for operation mode specification.
21, 22 MD1,
MD0 C Input pins for operation mode specification.
23 RST E Reset input pin.
24 VCC Power input pin (3.5 V to 5.5 V) .
25 VSS Power input pin (0 V) .
26 C I Power supply stabilization capacitor pin. It should be connected to a higher
than or equal to 0.1 F ceramic condenser.
27 X0
A
Oscillation input pin.
28 X1 Oscillation output pin.
29 to 32
P27 to P24
G
General-purpose I/O port.
The register can be set to select whether to use a pull-up
resistor. This function is enabled in single-chip mode.
IN3 to IN0 Event input pins for input capture 0 to 3.
33 to 35
P23 to P21
J
General-purpose I/O port.
The register can be set to select whether to use a pull-up
resistor. This function is enabled in single-chip mode.
High current output port
(Different I/O circuit type from MB90V950AMAS).
PPGF (E) , PPGD
(C) ,
PPGB(A)
Output pins for PPG.
36 P20 J
General-purpose I/O port.
The register can be set to select whether to use a pull-up
resistor. This function is enabled in single-chip mode.
High current output port
(Different I/O circuit type from MB90V950AMAS).
37
P85
K
General-purpose I/O port.
SIN1 Serial data input pin for UART1.
38
P87
F
General-purpose I/O port.
SCK1 Clock I/O pin for UART1.
39
P86
F
General-purpose I/O port.
SOT1 Serial data output pin for UART1.

Document Number: 002-04578 Rev. *A Page 9 of 64
MB90910 Series
(Continued)
* : For the I/O circuit type, refer to “I/O Circuit Type”.
Pin No. Pin name I/O circuit
type* Function
40
P43
F
General-purpose I/O port.
TX1 TX output pin for CAN1 controller.
41
P42
F
General-purpose I/O port.
RX1 RX input pin for CAN1 controller.
INT9R External interrupt request input pin for INT9R.
42
P83
F
General-purpose I/O port.
SOT0 Serial data output pin for UART0.
TOT2 Output pin for reload timer 2.
43
P84
F
General-purpose I/O port.
SCK0 Clock I/O pin for UART0.
INT15R External interrupt request input pin for INT15R.
44
P82
K
General-purpose I/O port.
SIN0 Serial data input pin for UART0.
INT14R External interrupt request input pin for INT14R.
TIN2 Event input pin for reload timer 2.
45
P44
F
General-purpose I/O port
(Different I/O circuit type from MB90V950AMAS).
FRCK0 Free-run timer 0 clock input pin.
46, 47 P40, P41 F General-purpose I/O port
48 AVSS IV
SS power input pin for analog circuit.

Document Number: 002-04578 Rev. *A Page 10 of 64
MB90910 Series
4. I/O Circuit Type
Type Circuit Remarks
AOscillation circuit :
High-speed oscillation feedback
resistor approx. 1 M
(MASK ROM product, Flash memory product)
Oscillation circuit :
High-speed oscillation feedback
resistor approx. 1 M
(Evaluation product)
BUnused
C• MASK ROM product / Evaluation
product :
CMOS hysteresis input pin
• Flash memory product :
CMOS input pin
D• MASK ROM product / Evaluation
product :
CMOS hysteresis input pin
• Flash memory product :
- CMOS input pin
- No Pull-down
X1
X0
Xout
Standby control signal
X1
X0
Standby control signal
Xout
Standby control signal
X1A
X0A
Xout
R
CMOS hysteresis
inputs
R
Pull-down
resistor
CMOShysteresis
inputs

Document Number: 002-04578 Rev. *A Page 11 of 64
MB90910 Series
(Continued)
ECMOS hysteresis input pin
Type Circuit Remarks
R
Pull-up
resistor
CMOShysteresis
inputs

Document Number: 002-04578 Rev. *A Page 12 of 64
MB90910 Series
(Continued)
Type Circuit Remarks
F• CMOS level output
(IOL 4 mA, IOH 4 mA)
• CMOS hysteresis inputs
(VIH0.8Vcc VIL0.2Vcc)
(With the standby-time input shutdown func-
tion)
• Automotive input (With the
standby-time input shutdown function)
G• CMOS level output
(IOL 4 mA, IOH 4 mA)
• CMOS hysteresis inputs
(VIH0.8Vcc VIL0.2Vcc)
(With the standby-time input shutdown func-
tion)
• Automotive input (With the
standby-time input shutdown function)
H• CMOS level output
(IOL 4 mA, IOH 4 mA)
• CMOS hysteresis inputs
(VIH0.8Vcc VIL0.2Vcc)
(With the standby-time input shutdown func-
tion)
• Automotive input (With the
standby-time input shutdown function)
• A/D analog input
Pout
Nout
R
CMOShysteresisinputs
Automotive inputs
Standby control for
input shutdown
P-ch
N-ch
R
Pull-up control
Pull-up
resistor
CMOS hysteresis inputs
Automotive inputs
Pout
Nout
Standby control for
input shutdown
P-ch
N-ch
P-ch
Pout
Nout
R
CMOS hysteresis inputs
Analog input
Automotive inputs
Standby control for
input shutdown
P-ch
N-ch

Document Number: 002-04578 Rev. *A Page 13 of 64
MB90910 Series
(Continued)
Type Circuit Remarks
IProtection circuit for power supply input
J• CMOS level output
(IOL 20 mA, IOH 14 mA)
(MB90V950: IOL 4 mA, IOH 4 mA)
• CMOS hysteresis inputs
(VIH0.8Vcc VIL0.2Vcc)
(With the standby-time input shutdown func-
tion)
• Automotive input (With the standby-time input
shutdown function)
K• CMOS level output
(IOL 4 mA, IOH 4 mA)
• CMOS hysteresis input
(VIH0.7Vcc VIL0.3Vcc)
(With standby-time input shutdown function)
• Automotive input (With standby-time
input shutdown function)
• CMOS hysteresis inputs
(VIH0.8Vcc VIL0.2Vcc)
(With the standby-time input shutdown func-
tion)
P-ch
N-ch
Pout high current output
Nout high current output
R
Pull-up control
Pull-up
resistor
CMOS hysteresis inputs
Automotive inputs
Standby control for
input shutdown
P-ch
N-ch
P-ch
Pout
Nout
R
P-ch
N-ch
CMOS hysteresis
inputs
Automotive input
Standby control for
input shutdown
CMOS hysteresis input

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MB90910 Series
(Continued)
Type Circuit Remarks
L• CMOS level output
(IOL = 4 mA, IOH = 4 mA)
• CMOS hysteresis inputs
(VIH0.8Vcc VIL0.2Vcc)
(With the standby-time input shutdown func-
tion)
• Automotive input
(With the standby-time input shutdown func-
tion)
• CMOS hysteresis input
(VIH0.7Vcc VIL0.3Vcc)
(With the standby-time input shutdown func-
tion)
• A/D analog input
Pout
Nout
R
P-ch
N-ch
CMOS hysteresis
inputs
Automotive input
Standby control for
input shutdown
Analog input
CMOS hysteresis input

Document Number: 002-04578 Rev. *A Page 15 of 64
MB90910 Series
5. Handling Devices
1. Preventing latch-up
CMOS IC chips may suffer latch-up under the following conditions :
■A voltage higher than VCC pin or lower than VSS pin is applied to an input or output pin.
■A voltage higher than the rated voltage is applied between VCC pin and VSS pin.
■The AVCC power supply is applied before the VCC voltage.
Latch-up may increase the power supply current drastically, causing thermal damage to the device.
Use meticulous care not to exceed the rating.
For the same reason, also be careful not to let the analog power-supply voltage (AVCC, AVR) exceed the digital power-supply voltage.
2. Treatment of unused pins
Leaving unused input pins open may result in permanent damage of the device due to misbehavior or latch-up. Therefore, they must
be pulled up or pulled down through resistors. In this case, those resistors should be more than 2 k.
Unused bidirectional pins should be set to the output state and can be left open, or the input state with the above described connection.
3. Using external clock
The high-speed oscillator pins (X0, X1) can not be used for external clock inputs.
4. Notes on during operation of PLL clock mode
On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops while the PLL clock mode
is selected, a self-oscillator circuit contained in the PLL may continue its operation at its self-running frequency. However, Cypress
will not guarantee results of operations if such failure occurs.

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MB90910 Series
5. Power supply pins (VCC/VSS)
■If there are multiple VCC and VSS pins, from the point of view of device design, pins to be of the same potential are connected the
inside of the device to prevent malfunction such as latch-up.
To reduce unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of ground level, and observe the standard
for total output current, be sure to connect the VCC and VSS pins to the power supply and ground externally.
■Connect VCC and VSS pins to the device from the current supply source at a low impedance.
■As a measure against power supply noise, connect a capacitor of about 0.1 F as a bypass capacitor between VCC pin and VSS
pin in the vicinity of VCC and VSS pins of the device.
6. Pull-up/down resistors
■The MB90910 series does not support internal pull-up/down resistors (Port 2 : built-in pull-up resistors) . Use external components
where needed.
7. Crystal oscillator circuit
Noises around X0 or X1 pin may be possible causes of malfunctions. Make sure to provide bypass capacitors via shortest distance
from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure, that lines of oscillation circuit do not cross
the lines of other circuits.
It is highly recommended to provide a printed circuit board artwork surrounding X0 and X1 pins with a ground area for stabilizing the
operation. Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device.
8. Turning-on sequence of power supply to A/D converter and analog inputs
Make sure to turn on the A/D converter power supply (AVCC and AVR) and analog inputs (AN0 to AN15) after turning-on the digital
power supply (VCC) .
Turn-off the digital power after turning off the A/D converter power supply and analog inputs. In this case, make sure that the voltage
does not exceed AVRH or AVCC.
9. Connection of unused pins of A/D converter if A/D converter is not used
Connect unused pins of A/D converter to AVCC VCC, AVSS AVR VSS.
10. Notes on energization
To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at
50 s or more (0.2 V to 2.7 V) .
V CC
V CC
V CC
V CC
V CC
V SS
V SS
V SS
V SS
V SS
MB90910
Series

Document Number: 002-04578 Rev. *A Page 17 of 64
MB90910 Series
11. Stabilization of power supply voltage
A sudden change in the power supply voltage may cause the device to malfunction even within the specified VCC power supply voltage
operating guarantee range. Therefore, the VCC power supply voltage should be
stabilized.
For reference, the power supply voltage should be controlled so that VCC ripple variations (peak-to-peak value) at commercial
frequencies (50 Hz/60 Hz) fall below 10of the standard VCC power supply voltage and the coefficient of transient fluctuation does
not exceed 0.1 V/ms at instantaneous power switching.
12. Initialization
In the device, there are internal registers which are initialized only by a power-on reset. To initialize these registers, turn on the power
again.
13. Notes on using CAN function
To use CAN function, please set ’1’ to DIRECT bit of CAN direct mode register (CDMR) .
If DIRECT bit is set to ’0’ (initial value) , wait states will be performed when accessing CAN registers.
Note : Please refer to Hardware Manual of “MB90910 series for detail of CAN Direct Mode Register”.
14. Flash security function
The security bit is located in the area of the Flash memory.
If protection code 01His written in the security bit, the Flash memory is in the protected state by security.
Therefore, please do not write 01Hin this address if you do not use the security function.
Please refer to following table for the address of the security bit.
15. Correspondence with TA105 °C or more
If used exceeding TA105 °C, please consult with us due to the restricted reliability.
It is ensured to write/erase data to the Flash memory between TA40 °C and 105 °C.
Flash memory size Address for security bit
MB90F912BS Embedded 1 Mbit Flash Memory FE0001H

Document Number: 002-04578 Rev. *A Page 18 of 64
MB90910 Series
6. Block Diagrams
■MB90V950AMAS
RAM
30 Kbytes
LIN-UART
7 channels
DMA
SOT6 to SOT0
SCK6 to SCK0
SIN6 to SIN0
AVCC
AVSS
AVRH
AVRL
ADTG
DA01, DA00
PPGF to PPG0
SDA1, SDA0
SCL1, SCL0
FRCK0
IN7 to IN0
OUT7 to OUT0
FRCK1
RX2 to RX0
TX2 to TX0
TIN3 to TIN0
TOT3 to TOT0
AD15 to AD00
A23 to A16
ALE
RD
WRL
WRH
HRQ
HAK
RDY
CLK
INT15 to INT8
(INT15R to INT8R)
INT7 to INT0
CKOT
AN23 to AN0
Clock
controller
F2MC-16LX
core
16-bit
I/O timer 0
16-bit
free-run
timer 1
Input
capture
8 channels
Output
compare
8 channels
CAN
controller
3 channels
16-bit
reload timer
4 channels
External
bus
DTP/
External
interrupt
Clock
monitor
Prescaler
(7 channels)
8/10-bit
A/D
converter
24 channels
8-bit
D/A converter
2 channels
Internal databus
8/16-bit
PPG
16 channels
I2C
interface
2 channels
X0, X1
RST

Document Number: 002-04578 Rev. *A Page 19 of 64
MB90910 Series
■MB90F912BS, MB90911AS
RAM
PPGF(E), PPGD(C),
PPGC(D), PPGE(F)
FRCK0
RX1
TX1
TIN2, TIN3
TOT2, TOT3
INT8, INT9R,
INT10, INT11,
INT12R, INT13,
INT14R, INT15R
X0, X1
RST
ADTG
AVR
AN15 to AN0
AVSS
AVCC
SIN0, SIN1, SIN2
SCK0, SCK1, SCK2
IN0 to IN3
PPGA(B), PPGB(A),
SOT0, SOT1, SOT2
*1 : Only for MB90F912BS
*2 : Only for MB90911AS
Clock
controller F2MC-16LX
core
Input
capture
4 channels
16-bit
I/O timer 0
CAN
controller
1 channel
16-bit
reload
timer
2 channels
Flash*1
MASK
ROM*2
Prescaler
3 channels
LIN-UART
2 channels
UART
1 channel
8/10-bit
A/D
converter
16 channels
8/16-bit
PPG
3 channels
DTP/
External
interrupt
Internal data bus

Document Number: 002-04578 Rev. *A Page 20 of 64
MB90910 Series
7. Memory Map
Note : The high-order portion of bank 00 gives the image of the FF bank ROM to make the small model of the C compiler effective.
Since the low-order 16 bits are the same, the table in ROM can be referred without using the far specification in the pointer
declaration.
For example, an attempt to access 00C000Hpractically accesses the value at FFC000Hin ROM.
The ROM area in bank FF exceeds 32 Kbytes, and its entire image cannot be shown in bank 00.
The image between FF8000Hand FFFFFFHis visible in bank 00, while the image between FF0000Hand FF7FFFHis visible
only in bank FF.
FFFFFFH
FF0000H
FEFFFFH
FE0000H
FDFFFFH
FD0000H
FCFFFFH
FC0000H
FBFFFFH
FB0000H
FAFFFFH
FA0000H
F9FFFFH
0000EFH
000000H
F90000H
F8FFFFH
F80000H
00FFFFH
007FFFH
007900H
0078FFH
000100H
008000H
MB90V950AMAS
FFFFFFH
FF0000H
0000EFH
000000H
00FFFFH
007FFFH
007900H
0020FFH
000100H
008000H
MB90F912BS
010000H
FEFFFFH
0000F0H
0000FFH
FE0000H
F70000H
F77FFFH
FFFFFFH
FF0000H
0000EFH
000000H
00FFFFH
007FFFH
007900H
0010FFH
000100H
008000H
MB90911AS
0000F0H
0000FFH
ROM (FF bank)
ROM (FE bank)
ROM (FD bank)
ROM (FC bank)
ROM (FB bank)
ROM (FA bank)
ROM (F9 bank)
ROM (F8 bank)
ROM (FF bank)
ROM
(image of FF bank)
Peripheral
ROM
(image of FF bank)
Peripheral
Peripheral Peripheral
: Not accessible
RAM 30 Kbytes
RAM 8 Kbytes
External access area
External access area
ROM (FE bank)
ROM
(image of FF bank)
Peripheral
Peripheral
RAM4 Kbytes
ROM (FF bank)