Cypress S29CD032J User manual

S29CD032J
S29CD016J
S29CL032J
S29CL016J
32/16 Mbit, 2.6/3.3 V, Dual Boot,
Simultaneous Read/Write, Burst Flash
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 002-00948 Rev. *C Revised November 08, 2017
General Description
The Cypress S29CD-J and S29CL-J devices are Floating Gate products fabricated in 110-nm process technology. These burst-
mode Flash devices are capable of performing simultaneous read and write operations with zero latency on two separate banks,
using separate data and address pins. These products can operate up to 75 MHz (32 Mb) or 66 MHz (16 Mb), and use a single VCC
of 2.5V to 2.75V (S29CD-J) or 3.0V to 3.6V (S29CL-J) that make them ideal for today’s demanding automotive applications.
Distinctive Characteristics
Single 2.6V (S29CD-J) or 3.3V (S29CL-J) for read/program/
erase
110 nm Floating Gate Technology
Simultaneous Read/Write operation with zero latency
x32 Data Bus
Dual Boot Sector Configuration (top and bottom)
Flexible Sector Architecture
– CD016J and CL016J: Eight 2k Double word, Thirty 16k
Double word, and Eight 2k Double Word sectors
– CD032J and CL032J: Eight 2k Double word, Sixty-two 16k
Double Word, and Eight 2k Double Word sectors
VersatileI/O™ control (1.65V to 3.6V)
Programmable Burst Interface
– Linear for 2, 4, and 8 double word burst with wrap around
Secured Silicon Sector that can be either factory or
customer locked
20 year data retention (typical)
Cycling Endurance: 1 million write cycles per sector (typical)
Command set compatible with JEDEC (JC42.4) standard
Supports Common Flash Interface (CFI)
Extended Temperature range
Persistent and Password methods of Advanced Sector
Protection
Unlock Bypass program command to reduce programming
time
ACC input pin to reduce factory programming time
Data Polling bits indicate program and erase operation
completion
Hardware (WP#) protection of two outermost sectors in the
large bank
Ready/Busy (RY/BY#) output indicates data available to
system
Suspend and Resume commands for Program and Erase
Operation
Offered Packages
– 80-pin PQFP
– 80-ball Fortified BGA (13 x 11 mm and 11 x 9mm versions)
– Pb-free package option available
– Known Good Die

Document Number: 002-00948 Rev. *C Page 2 of 74
S29CD032J
S29CD016J
S29CL032J
S29CL016J
Performance Characteristics
Notice for the 32Mb S29CD-J and S29CL-J devices only:
Refer to the application note “Recommended Mode of Operation for Cypress®110 nm S29CD032J/S29CL032J Flash Memory”
publication number S29CD-CL032J_Recommend_AN for programming best practices.
Read Access Times
Speed Option (MHz) 75 (32 Mb only) 66 56 40
Max Asynch. Access Time, ns (tACC)54545454
Max Synch. Burst Access, ns (tBACC)8888
Min Initial Clock Delay (clock cycles) 5 5 5 4
Max CE# Access Time, ns (tCE)54545454
Max OE# Access time, ns (tOE)20202020
Current Consumption (Max values)
Continuous Burst Read @ 75 MHz 90 mA
Program 50 mA
Erase 50 mA
Standby Mode 60 µA
Typical Program and Erase Times
Double Word Programming 18 µs
Sector Erase 1.0 s

Document Number: 002-00948 Rev. *C Page 3 of 74
S29CD032J
S29CD016J
S29CL032J
S29CL016J
Contents
1. Ordering Information................................................... 4
1.1 Valid Combinations ........................................................ 5
2. Input/Output Descriptions
and Logic Symbols...................................................... 6
3. Block Diagram.............................................................. 7
4. Block Diagram of Simultaneous
Read/Write Circuit ........................................................ 8
5. Physical Dimensions/Connection Diagrams............. 9
5.1 80-Pin PQFP Connection Diagram ................................ 9
5.2 PQR080–80-Lead Plastic Quad Flat
Package Physical Dimensions..................................... 10
5.3 80-Ball Fortified BGA Connection Diagram ................. 11
5.4 Special Package Handling Instructions........................ 11
5.5 LAA080–80-ball Fortified Ball Grid Array
(13 x 11 mm) Physical Dimensions.............................. 12
5.6 LAD080–80-ball Fortified Ball Grid Array
(11 x 9 mm) Physical Dimensions................................ 13
6. Product Overview ...................................................... 14
6.1 Memory Map ................................................................ 14
7. Device Operations ..................................................... 19
7.1 Device Operation Table ............................................... 19
7.2 Asynchronous Read..................................................... 20
7.3 Hardware Reset (RESET#).......................................... 21
7.4 Synchronous (Burst) Read Mode
and Configuration Register .......................................... 21
7.5 Autoselect .................................................................... 26
7.6 VersatileI/O (VIO) Control............................................. 27
7.7 Program/Erase Operations .......................................... 27
7.8 Write Operation Status................................................. 32
7.9 Reset Command.......................................................... 36
8. Advanced Sector Protection/Unprotection ............. 37
8.1 Advanced Sector Protection Overview ........................ 38
8.2 Persistent Protection Bits............................................. 39
8.3 Persistent Protection Bit Lock Bit................................. 41
8.4 Dynamic Protection Bits............................................... 41
8.5 Password Protection Method ....................................... 42
8.6 Hardware Data Protection Methods............................. 43
9. Secured Silicon Sector Flash Memory Region ....... 44
9.1 Secured Silicon Sector Protection Bit .......................... 45
9.2 Secured Silicon Sector Entry
and Exit Commands...................................................... 45
10. Electronic Marking...................................................... 46
11. Power Conservation Modes....................................... 46
11.1 Standby Mode............................................................... 46
11.2 Automatic Sleep Mode.................................................. 46
11.3 Hardware RESET# Input Operation.............................. 46
11.4 Output Disable (OE#).................................................... 46
12. Electrical Specifications............................................. 47
12.1 Absolute Maximum Ratings .......................................... 47
13. Operating Ranges ....................................................... 48
14. DC Characteristics...................................................... 49
14.1 Zero Power Flash.......................................................... 50
15. Test Conditions ........................................................... 51
16. Test Specifications ..................................................... 51
16.1 Switching Waveforms ................................................... 51
17. AC Characteristics...................................................... 52
17.1 VCC and VIO Power-up.................................................. 52
17.2 Asynchronous Operations............................................. 52
17.3 Synchronous Operations .............................................. 54
17.4 Hardware Reset (RESET#)........................................... 56
17.5 Write Protect (WP#)...................................................... 57
17.6 Erase/Program Operations ........................................... 57
17.7 Alternate CE# Controlled
Erase/Program Operations ........................................... 62
17.8 Erase and Programming Performance ......................... 63
17.9 PQFP and Fortified BGA Pin Capacitance ................... 63
18. Appendix 1 .................................................................. 64
18.1 Common Flash Memory Interface (CFI) ....................... 64
19. Appendix 2 .................................................................. 67
19.1 Command Definitions.................................................... 67
20. Revision History.......................................................... 69
Sales, Solutions, and Legal Information .......................... 74
Worldwide Sales and Design Support ........................... 74
Products ........................................................................ 74
PSoC® Solutions .......................................................... 74
Cypress Developer Community ..................................... 74
Technical Support ......................................................... 74

Document Number: 002-00948 Rev. *C Page 4 of 74
S29CD032J
S29CD016J
S29CL032J
S29CL016J
1. Ordering Information
The order number (Valid Combination) is formed by the following:
S29CD032J
S29CL032J 0JFAI 00 0
Packing Type
0 = Tray, FBGA: 180 per tray, min. 10 trays per box
Tray, PQFP: 66 per tray, min. 10 trays per box
2 = 7” Tape and Reel, FBGA: 400 per reel
3 = 13” Tape and Reel, FBGA: 1600 per reel
13” Tape and Reel, PQFP: 500 per reel
Boot Sector Option (16th Character)
0 = Top Boot with Simultaneous Operation
1 = Bottom Boot with Simultaneous Operation
2 = Top Boot without Simultaneous Operation
3 = Bottom Boot without Simultaneous Operation
Autoselect ID Option (15th Character)
0 = 7E, 08, 01/00 Autoselect ID
1 = 7E, 36, 01/00 Autoselect ID S29CD016J only
0 = 7E, 46, 01/00 Autoselect ID S29CL016J only
0 = 7E, 09, 01/00 Autoselect ID S29CD032J only
0 = 7E, 49, 01/00 Autoselect ID S29CL032J only
Temperature Range
I = Industrial (–40 °C to +85 °C)
M = Extended (–40 °C to +125 °C)
Material Set
A = Standard
F = Pb-free Option
Package Type
Q = Plastic Quad Flat Package (PQFP)
F = Fortified Ball Grid Array, 1.0 mm pitch package, 13  11 mm package
B = Fortified Ball Grid Array, 1.0 mm pitch package, 11  9 mm package
Clock Frequency (11th Character)
J = 40 MHz
M = 56 MHz
P = 66 MHz
R = 75 MHz
Initial Burst Access Delay (10th Character)
0 = 5-1-1-1, 6-1-1-1, and above
1 = 4-1-1-1 (40 MHz only)
Device Number/Description
S29CD032J/S29CD016J (2.5 volt-only), S29CL032J/S29CL016J (3.3 Volt-only)
32 or 16 Mbit (1M or 512k  32-Bit) CMOS Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory
Manufactured on 110 nm floating gate technology

Document Number: 002-00948 Rev. *C Page 5 of 74
S29CD032J
S29CD016J
S29CL032J
S29CL016J
1.1 Valid Combinations
Valid Combinations lists configurations planned to be supported in volume for this device. Consult your local sales office to confirm
availability of specific valid combinations and to check on newly released combinations.
Notes
1. The ordering part number that appears on BGA packages omits the leading “S29”.
2. Contact factory for availability.
S29CD-J/CL-J Valid Combinations
Device
Number
Initial Burst
Access Delay
Clock
Frequency
Package
Type
Material
Set
Temperature
Range
Autoselect ID
Option
Boot Sector
Option
Packing
Type
S29CD016J
0, 1 J
Q
A, F I, M
0, 1
0, 1, 2, 3
0, 3
B, F 0, 2, 3
0M, P
Q0, 3
B, F 0, 2, 3
S29CL016J
0, 1 J Q
0
0, 3
B, F 0, 2, 3
0M, P
Q0, 3
B, F 0, 2, 3
S29CD032J
0, 1 J Q0, 3
B, F 0, 2, 3
0
M, P Q0, 3
B, F 0, 2, 3
R
Q
0, 1 (2)
0, 3
2, 3
B, F 0, 1 (2) 0, 2, 3
2, 3
S29CL032J
0, 1 J Q
0, 1, 2, 3
0, 3
B, F 0, 2, 3
0
M, P
Q0, 3
B, F 0, 2, 3
R
Q0, 1 (2) 0, 3
2, 3
B, F 0, 1 (2) 0, 2, 3
2, 3

Document Number: 002-00948 Rev. *C Page 6 of 74
S29CD032J
S29CD016J
S29CL032J
S29CL016J
2. Input/Output Descriptions and Logic Symbols
Table identifies the input and output package connections provided on the device.
Symbol Type Description
A19-A0 Input Address lines for S29CD-J and S29CL-J (A18-A0 for 16 Mb and A19-A0 for 32 Mb). A9 supports
12V autoselect input.
DQ31-DQ0 I/O Data input/output
CE# Input Chip Enable. This signal is asynchronous relative to CLK for the burst mode.
OE# Input Output Enable. This signal is asynchronous relative to CLK for the burst mode.
WE# Input Write Enable
VCC Supply Device Power Supply. This signal is asynchronous relative to CLK for the burst mode.
VIO Supply VersatileI/OTM Input.
VSS Supply Ground
NC No Connect Not connected internally
RY/BY# Output
Ready/Busy output and open drain which require a external pull up resistor.
When RY/BY# = VOH, the device is ready to accept read operations and commands. When RY/BY#
= VOL, the device is either executing an embedded algorithm or the device is executing a hardware
reset operation.
CLK Input Clock Input that can be tied to the system or microprocessor clock and provides the fundamental
timing and internal operating frequency.
ADV# Input Load Burst Address input. Indicates that the valid address is present on the address inputs.
IND# Output End of burst indicator for finite bursts only. IND is low when the last word in the burst sequence is at
the data outputs.
WAIT# Output Provides data valid feedback only when the burst length is set to continuous.
WP# Input Write Protect Input. At VIL, disables program and erase functions in two outermost sectors of the
large bank.
ACC Input Acceleration input. At VHH, accelerates erasing and programming. When not used for acceleration,
ACC = VSS or VCC.
RESET# Input Hardware Reset.

Document Number: 002-00948 Rev. *C Page 7 of 74
S29CD032J
S29CD016J
S29CL032J
S29CL016J
3. Block Diagram
Note
3.Address bus is A19–A0 for 32 Mb device, A18–A0 for 16 Mb device. Data bus is D31–DQ0.
IND/
WAIT#
Input/Output
Buffers
X-Decoder
Y-Decoder
Chip Enable
Output Enable
Erase Voltage
Generator
PGM Voltage
Generator
Timer
VCC
Detector
State
Control
Command
Register
VCC
VSS
WE#
RESET#
ACC
WP#
CE#
OE#
DQmax–DQ0
Data
Y-Gating
Cell Matrix
Address Latch
Burst
State
Control
Burst
Address
Counter
ADV#
CLK
VIO
Amax-A0
Amax-A0

Document Number: 002-00948 Rev. *C Page 8 of 74
S29CD032J
S29CD016J
S29CL032J
S29CL016J
4. Block Diagram of Simultaneous Read/Write Circuit
V
CC
V
SS
Upper Bank Address
RESET#
WE#
CE#
ADV#
S TAT E
CONTROL
&
COMMAND
REGISTER
Upper Bank
X-Decoder
Y-Decoder
Latches and Control Logic
OE#
DQ
max
–DQ0
DQ
max
–DQ0
Lower Bank
Y-Decoder
X-Decoder
Latches and
Control Logic
Lower Bank Address
Status
Control
A
max
–A0
Amax–A0 Amax–A0
A
max
–A0
A
max
–A0
DQmax–DQ0DQmax–DQ0

Document Number: 002-00948 Rev. *C Page 9 of 74
S29CD032J
S29CD016J
S29CL032J
S29CL016J
5. Physical Dimensions/Connection Diagrams
5.1 80-Pin PQFP Connection Diagram
Notes
4. On 16 Mb device, pin 44 (A19) is NC.
5. Pin 69 (RY/BY#) is Open Drain and requires an external pull-up resistor.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
DQ16
DQ17
DQ18
DQ19
VIO
VSS
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
VIO
VSS
DQ28
DQ29
DQ30
DQ31
NC
A0
A1
A2
DQ15
DQ14
DQ13
DQ12
VSS
VIO
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
VSS
VIO
DQ3
DQ2
DQ1
DQ0
A19
A18
A17
A16
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
NC IND/WAIT# NC WP# WE# OE# CE# V
CC
NC
V
SS
ADV# RY/BY# NC CLK RESET#
V
IO
A3 A4 A5 A6 A7 A8
V
SS
ACC
V
CC
A9
A10 A11 A12 A13 A14
A15
25
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
80-Pin PQFP

Document Number: 002-00948 Rev. *C Page 10 of 74
S29CD032J
S29CD016J
S29CL032J
S29CL016J
5.2 PQR080–80-Lead Plastic Quad Flat Package Physical Dimensions
3213\38.4C
PACKAGE PQR 080
JEDEC MO-108(B)CB-1 NOTES
SYMBOL MIN NOM MAX
A -- -- 3.35
A1 0.25 -- --
A2 2.70 2.80 2.90
b 0.30 -- 0.45 SEE NOTE 4
c 0.15 -- 0.23
D 17.00 17.20 17.40
D1 13.90 14.00 14.10 SEE NOTE 3
D3 -- 12.0 -- REFERENCE
e -- 0.80 -- BASIC, SEE NOTE 7
E 23.00 23.20 23.40
E1 19.90 20.00 20.10 SEE NOTE 3
E3 -- 18.40 -- REFERENCE
aaa --- 0.20 ---
ccc 0.10
L 0.73 0.88 1.03
P24
Q40
R64
S80
NOTES:
1. ALL DIMENSIONS AND TOLERANCES CONFORM TO
ANSI Y14.5M-1982.
2. DATUM PLANE -A- IS LOCATED AT THE MOLD PARTING LINE
AND IS COINCIDENT WITH THE BOTTOM OF THE LEAD WHERE
THE LEAD EXITS THE PLASTIC BODY.
3. DIMENSIONS "D1" AND "E1" DO NOT INCLUD MOLD PROTRUSION.
ALLOWABLE PROTRUSION IS 0.25 mm PER SIDE.
DIMENSIONS "D1" AND "E1" INCLUDE MOLD MISMATCH AND
ARE DETERMINED AT DATUM PLANE -A-
4. DIMENSION "B" DOES NOT INCLUDE DAMBAR PROTRUSION.
5. CONTROLLING DIMENSIONS: MILLIMETER.
6. DIMENSIONS "D" AND "E" ARE MEASURED FROM BOTH
INNERMOST AND OUTERMOST POINTS.
7. DEVIATION FROM LEAD-TIP TRUE POSITION SHALL BE WITHIN
±0.0076 mm FOR PITCH > 0.5 mm AND WITHIN ±0.04 FOR
PITCH < 0.5 mm.
8. LEAD COPLANARITY SHALL BE WITHIN: (REFER TO 06-500)
1 - 0.10 mm FOR DEVICES WITH LEAD PITCH OF 0.65 - 0.80 mm
2 - 0.076 mm FOR DEVICES WITH LEAD PITCH OF 0.50 mm.
COPLANARITY IS MEASURED PER SPECIFICATION 06-500.
9. HALF SPAN (CENTER OF PACKAGE TO LEAD TIP) SHALL BE
WITHIN ±0.0085".
b
c
SECTION S-S
6
3
36
-B-
PIN R
PIN S
-A-
PIN ONE I.D.
D1
D
D3
PIN Q
-D-
PIN P
E
E1
E3
SEE NOTE 3
A
A1 A2
-C-
-A- SEATING PLANE
2
eBASIC
SEE DETAIL X
S
S
DETAIL X
0.25
A
C
ccc
SDS
4
CABM
aa
b
0˚-7˚ a
0˚MIN.
L
GAGE
PLANE 7˚
TYP.
0.30 ± 0.05 R
7˚
TYP.
0.20 MIN. FLAT SHOULDER

Document Number: 002-00948 Rev. *C Page 11 of 74
S29CD032J
S29CD016J
S29CL032J
S29CL016J
5.3 80-Ball Fortified BGA Connection Diagram
Notes
6. On 16 Mb device, ball D3 (A19) is NC.
7. Ball F5 (RY/BY#) is Open Drain and requires an external pull-up resistor.
5.4 Special Package Handling Instructions
Special handling is required for Flash Memory products in molded packages (BGA). The package and/or data integrity may be
compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time.
B3 C3 D3 E3 F3 G3 H3
B4 C4 D4 E4 F4 G4 H4
B5 C5 D5 E5 F5 G5 H5
B6 C6 D6 E6 F6 G6 H6
B7 C7 D7 E7 F7 G7 H7
B8 C8 D8 E8 F8 G8 H8
DQ20V
IO
V
SS
V
IO
DQ29A0A1
DQ18DQ23DQ24DQ26DQ30NCA4
DQ19
DQ21DQ25DQ28DQ31A7A5
DQ17DQ22RY/BY#DQ27NCNCA8
WP#DQ9DQ5DQ1NCA10A9
DQ11DQ10DQ6DQ2A19A11A12
A3
A4
A5
A6
A7
A8
A2
A3
A6
V
SS
ACC
V
CC
B2 C2 D2 E2 F2 G2 H2
DQ12DQ8DQ7DQ4DQ0A18A13
A2
A14
B1 C1 D1 E1 F1 G1 H1
DQ13
J3
J4
J5
J6
J7
J8
DQ16
IND/WAIT#
OE#
CE#
NC
ADV#
J2
DQ14
J1
DQ15
K3
K4
K5
K6
K7
K8
NC
NC
WE#
V
CC
V
SS
CLK
K2
RESET#
K1
V
IO
V
IO
V
SS
V
IO
DQ3A17A16
A1
A15

Document Number: 002-00948 Rev. *C Page 12 of 74
S29CD032J
S29CD016J
S29CL032J
S29CL016J
5.5 LAA080–80-ball Fortified Ball Grid Array (13 x 11 mm) Physical Dimensions
3214\38.12C
PACKAGE LAA 080
JEDEC N/A
13.00 x 11.00 mm NOTE
PACKAGE
SYMBOL MIN NOM MAX
A -- -- 1.40 PROFILE HEIGHT
A1 0.40 -- -- STANDOFF
A2 0.60 -- -- BODY THICKNESS
D 13.00 BSC. BODY SIZE
E 11.00 BSC. BODY SIZE
D1 9.00 BSC. MATRIX FOOTPRINT
E1 7.00 BSC. MATRIX FOOTPRINT
MD 10 MATRIX SIZE D DIRECTION
ME 8 MATRIX SIZE E DIRECTION
N 80 BALL COUNT
φb 0.50 0.60 0.70 BALL DIAMETER
eD 1.00 BSC. BALL PITCH - D DIRECTION
eE 1.00 BSC. BALL PITCH - E DIRECTION
SD/SE 0.50 BSC SOLDER BALL PLACEMENT
NOTES:
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010
(EXCEPT AS NOTED).
4. e REPRESENTS THE SOLDER BALL GRID PITCH.
5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE "D"
DIRECTION. SYMBOL "ME" IS THE BALL COLUMN MATRIX
SIZE IN THE "E" DIRECTION. N IS THE TOTAL NUMBER OF
SOLDER BALLS.
6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER
OF SOLDER BALLS IN THE OUTER ROW PARALLEL TO THE D
OR E DIMENSION, RESPECTIVELY, SD OR SE = 0.000.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW , SD OR SE = e/2
8. N/A
9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
BOTTOM VIEW
SIDE VIEW
TOP VIEW 2X
2X C
0.20
C0.20
67
7
AC
C
φ0.10
φ0.25 M
MB
C0.25
0.15 C
A
B
C
SEATING PLANE
JK
eD
(INK OR LASER)
CORNER
A1
A2
D
E
φ0.50
A1 CORNER ID.
1.00±0.5
1.00±0.5
A
A1
CORNER
A1
NXφbSD
SE
eE
E1
D1
1
2
3
4
5
6
7
8
ACBDFEGH

Document Number: 002-00948 Rev. *C Page 13 of 74
S29CD032J
S29CD016J
S29CL032J
S29CL016J
5.6 LAD080–80-ball Fortified Ball Grid Array (11 x 9 mm) Physical Dimensions
g1064 \ f16-038.12 \ 01.31.12
NOTES:
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
3. BALL POSITION DESIGNATION PER JEP95, SECTION
4.3, SPP-010.
4. e REPRESENTS THE SOLDER BALL GRID PITCH.
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE
"D" DIRECTION.
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS
A AND B AND DEFINE THE POSITION OF THE CENTER
SOLDER BALL IN THE OUTER ROW.
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN
THE OUTER ROW SD OR SE = 0.000.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN
THE OUTER ROW, SD OR SE = e/2
8. “+” INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS.
9 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
PACKAGE LAD 080
JEDEC N/A
D X E 11.00 mm x 9.00 mm
PACKAGE
SYMBOL MIN NOM MAX NOTE
A --- --- 1.40 PROFILE
A1 0.35 0.45 0.55 BALL HEIGHT
D 11.00 BSC BODY SIZE
E 9.00 BSC BODY SIZE
D1 9.00 BSC MATRIX FOOTPRINT
E1 7.00 BSC MATRIX FOOTPRINT
MD 10 MATRIX SIZE D DIRECTION
ME 8 MATRIX SIZE E DIRECTION
N 80 BALL COUNT
b 0.55 0.65 0.75 BALL DIAMETER
eE 1.00 BSC BALL PITCH
eD 1.00 BSC BALL PITCH
SD / SE 0.50 BSC SOLDER BALL PLACEMENT
N/A DEPOPULATED SOLDER BALLS

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6. Product Overview
The S29CD-J and S29CL-J families consist of 32 Mb and 16 Mb, 2.6 volt-only (CD-J) or 3.3 volt-only (CL-J), simultaneous read/
write, dual boot burst mode Flash devices optimized for today's automotive designs.
These devices are organized in 1,048,576 double words (32 Mb) or 524,288 double words (16 Mb) and are capable of linear burst
read (2, 4, or 8 double words) with wraparound. (Note that 1 double word = 32 bits.) These products also offer single word
programming with program/erase suspend and resume functionality. Additional features include:
Advanced Sector Protection methods for protecting sectors as required.
256 bytes of Secured Silicon area for storing customer or factory secured information. The Secured Silicon Sector is One-Time
Programmable.
Electronic marking.
6.1 Memory Map
The S29CD-J and S29CL-J devices consist of two banks organized as shown in Table 1, Table 2, Table 3 and Table 4.
Table 1. S29CD016J/CL016J (Top Boot) Sector and Memory Address Map
Sector Sector Group x32 Address Range
(A18:A0)
Sector Size
(KDwords) Sector Sector Group x32 Address Range (A18:A0)
Sector Size
(KDwords)
Bank 0 (Note 9)
SA0 (Note 8) SG0 00000h–007FFh 2
Bank 1 (Note 9)
SA15
SG10
20000h–23FFFh 16
SA1 SG1 00800h–00FFFh 2 SA16 24000h–27FFFh 16
SA2 SG2 01000h–017FFh 2 SA17 28000h–2BFFFh 16
SA3 SG3 01800h–01FFFh 2 SA18 2C000h–2FFFFh 16
SA4 SG4 02000h–027FFh 2 SA19
SG11
30000h–33FFFh 16
SA5 SG5 02800h–02FFFh 2 SA20 34000h–37FFFh 16
SA6 SG6 03000h–037FFh 2 SA21 38000h–3BFFFh 16
SA7 SG7 03800h–03FFFh 2 SA22 3C000h–3FFFFh 16
SA8
SG8
04000h–07FFFh 16 SA23
SG12
40000h–43FFFh 16
SA9 08000h–0BFFFh 16 SA24 44000h–47FFFh 16
SA10 0C000h–0FFFFh 16 SA25 48000h–4BFFFh 16
SA11
SG9
10000h–13FFFh 16 SA26 4C000h–4FFFFh 16
SA12 14000h–17FFFh 16 SA27
SG13
50000h–53FFFh 16
SA13 18000h–1BFFFh 16 SA28 54000h–57FFFh 16
SA14 1C000h–1FFFFh 16 SA29 58000h–5BFFFh 16
SA30 5C000h–5FFFFh 16
SA31
SG14
60000h–63FFFh 16
SA32 64000h–67FFFh 16
SA33 68000h–6BFFFh 16
SA34 6C000h–6FFFFh 16
SA35
SG15
70000h–73FFFh 16
SA36 74000h–77FFFh 16
SA37 78000h–7BFFFh 16
SA38 SG16 7C000h–7C7FFh 2
SA39 SG17 7C800h–7CFFFh 2
SA40 SG18 7D000h–7D7FFh 2
SA41 SG19 7D800h–7DFFFh 2
SA42 SG20 7E000h–7E7FFh 2
SA43 SG21 7E800h–7EFFFh 2
SA44
(Note 10) SG22 7F000h–7F7FFh 2
SA45
(Note 10) SG23 7F800h–7FFFFh 2

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Notes
8. Secured Silicon Sector overlays this sector when enabled.
9. The bank address is determined by A18 and A17. BA = 00 for Bank 0 and BA = 01, 10, or 11 for Bank 1.
10. This sector has the additional WP# pin sector protection feature.
Notes
11. This sector has the additional WP# pin sector protection feature.
12. The bank address is determined by A18 and A17. BA = 00, 01, or 10 for Bank 0 and BA = 11 for Bank 1.
13. Secured Silicon Sector overlays this sector when enabled.
Table 2. S29CD016J/CL016J (Bottom Boot) Sector and Memory Address Map
Sector Sector
Group
x32 Address Range
(A18:A0)
Sector Size
(KDwords) Sector Sector Group
x32
Address Range
(A18:A0)
Sector Size
(KDwords)
Bank 0 (Note 12)
SA0 (Note 11) SG0 00000h–007FFh 2
Bank 1 (Note 12)
SA31
SG14
60000h–63FFFh 16
SA1 (Note 11) SG1 00800h–00FFFh 2 SA32 64000h–67FFFh 16
SA2 SG2 01000h–017FFh 2 SA33 68000h–6BFFFh 16
SA3 SG3 01800h–01FFFh 2 SA34 6C000h–6FFFFh 16
SA4 SG4 02000h–027FFh 2 SA35
SG15
70000h–73FFFh 16
SA5 SG5 02800h–02FFFh 2 SA36 74000h–77FFFh 16
SA6 SG6 03000h–037FFh 2 SA37 78000h–7BFFFh 16
SA7 SG7 03800h–03FFFh 2 SA38 SG16 7C000h–7C7FFh 2
SA8
SG8
04000h–07FFFh 16 SA39 SG17 7C800h–7CFFFh 2
SA9 08000h–0BFFFh 16 SA40 SG18 7D000h–7D7FFh 2
SA10 0C000h–0FFFFh 16 SA41 SG19 7D800h–7DFFFh 2
SA11
SG9
10000h–13FFFh 16 SA42 SG20 7E000h–7E7FFh 2
SA12 14000h–17FFFh 16 SA43 SG21 7E800h–7EFFFh 2
SA13 18000h–1BFFFh 16 SA44 SG22 7F000h–7F7FFh 2
SA14 1C000h–1FFFFh 16 SA45
(Note 13) SG23 7F800h–7FFFFh 2
SA15
SG10
20000h–23FFFh 16
SA16 24000h–27FFFh 16
SA17 28000h–2BFFFh 16
SA18 2C000h–2FFFFh 16
SA19
SG11
30000h–33FFFh 16
SA20 34000h–37FFFh 16
SA21 38000h–3BFFFh 16
SA22 3C000h–3FFFFh 16
SA23
SG12
40000h–43FFFh 16
SA24 44000h–47FFFh 16
SA25 48000h–4BFFFh 16
SA26 4C000h–4FFFFh 16
SA27
SG13
50000h–53FFFh 16
SA28 54000h–57FFFh 16
SA29 58000h–5BFFFh 16
SA30 5C000h–5FFFFh 16

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Table 3. S29CD032J/CL032J (Top Boot) Sector and Memory Address Map
Sector Sector Group x32 Address Range
(A19:A0)
Sector Size
(KDwords) Sector Sector Group x32 Address Range (A19:A0)
Sector Size
(KDwords)
Bank 0 (Note 15) Bank 1 continued (Note 15)
SA0
(Note 14) SG0 00000h–007FFh 2 SA39
SG16
80000h–83FFFh 16
SA1 SG1 00800h–00FFFh 2 SA40 84000h–87FFFh 16
SA2 SG2 01000h–017FFh 2 SA41 88000h–8BFFFh 16
SA3 SG3 01800h–01FFFh 2 SA42 8C000h–8FFFFh 16
SA4 SG4 02000h–027FFh 2 SA43
SG17
90000h–93FFFh 16
SA5 SG5 02800h–02FFFh 2 SA44 94000h–97FFFh 16
SA6 SG6 03000h–037FFh 2 SA45 98000h–9BFFFh 16
SA7 SG7 03800h–03FFFh 2 SA46 9C000h–9FFFFh 16
SA8
SG8
04000h–07FFFh 16 SA47
SG18
A0000h–A3FFFh 16
SA9 08000h–0BFFFh 16 SA48 A4000h–A7FFFh 16
SA10 0C000h–0FFFFh 16 SA49 A8000h–ABFFFh 16
SA11
SG9
10000h–13FFFh 16 SA50 AC000h–AFFFFh 16
SA12 14000h–17FFFh 16 SA51
SG19
B0000h–B3FFFh 16
SA13 18000h–1BFFFh 16 SA52 B4000h–B7FFFh 16
SA14 1C000h–1FFFFh 16 SA53 B8000h–BBFFFh 16
SA15
SG10
20000h–23FFFh 16 SA54 BC000h–BFFFFh 16
SA16 24000h–27FFFh 16 SA55
SG20
C0000h–C3FFFh 16
SA17 28000h–2BFFFh 16 SA56 C4000h–C7FFFh 16
SA18 2C000h–2FFFFh 16 SA57 C8000h–CBFFFh 16
SA19
SG11
30000h–33FFFh 16 SA58 CC000h–CFFFFh 16
SA20 34000h–37FFFh 16 SA59
SG21
D0000h–D3FFFh 16
SA21 38000h–3BFFFh 16 SA60 D4000h–D7FFFh 16
SA22 3C000h–3FFFFh 16 SA61 D8000h–DBFFFh 16
Bank 1 (Note 15) SA62 DC000h–DFFFFh 16
SA23
SG12
40000h–43FFFh 16 SA63
SG22
E0000h–E3FFFh 16
SA24 44000h–47FFFh 16 SA64 E4000h–E7FFFh 16
SA25 48000h–4BFFFh 16 SA65 E8000h–EBFFFh 16
SA26 4C000h–4FFFFh 16 SA66 EC000h–EFFFFh 16
SA27
SG13
50000h–53FFFh 16 SA67
SG23
F0000h–F3FFFh 16
SA28 54000h–57FFFh 16 SA68 F4000h–F7FFFh 16
SA29 58000h–5BFFFh 16 SA69 F8000h–FBFFFh 16
SA30 5C000h–5FFFFh 16 SA70 SG24 FC000h–FC7FFh 2
SA31
SG14
60000h–63FFFh 16 SA71 SG25 FC800h–FCFFFh 2
SA32 64000h–67FFFh 16 SA72 SG26 FD000h–FD7FFh 2
SA33 68000h–6BFFFh 16 SA73 SG27 FD800h–FDFFFh 2
SA34 6C000h–6FFFFh 16 SA74 SG28 FE000h–FE7FFh 2

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Notes
14. Secured Silicon Sector overlays this sector when enabled.
15. The bank address is determined by A19 and A18. BA = 00 for Bank 0 and BA = 01, 10, or 11 for Bank 1.
16. This sector has the additional WP# pin sector protection feature.
SA35
SG15
70000h–73FFFh 16 SA75 SG29 FE800h–FEFFFh 2
SA36 74000h–77FFFh 16 SA76
(Note 16) SG30 FF000h–FF7FFh 2
SA37 78000h–7BFFFh 16 SA77
(Note 16) SG31 FF800h–FFFFFh 2
SA38 7C000h–7FFFFh 16
Table 3. S29CD032J/CL032J (Top Boot) Sector and Memory Address Map (Continued)
Sector Sector Group x32 Address Range
(A19:A0)
Sector Size
(KDwords) Sector Sector Group x32 Address Range (A19:A0)
Sector Size
(KDwords)
Bank 0 (Note 15) Bank 1 continued (Note 15)

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Notes
17. This sector has the additional WP# pin sector protection feature.
18. The bank address is determined by A19 and A18. BA = 00, 01, or 10 for Bank 0 and BA = 11 for Bank 1.
19. The Secured Silicon Sector overlays this sector when enabled.
Table 4. S29CD032J/CL032J (Bottom Boot) Sector and Memory Address Map
Sector Sector Group x32 Address Range
(A19:A0)
Sector Size
(KDwords) Sector Sector Group x32 Address Range (A19:A0)
Sector Size
(KDwords)
Bank 0 (Note 18) Bank 0 continued (Note 18)
SA0 (Note 19) SG0 00000h–007FFh 2 SA39
SG16
80000h–83FFFh 16
SA1 (Note 19) SG1 00800h–00FFFh 2 SA40 84000h–87FFFh 16
SA2 SG2 01000h–017FFh 2 SA41 88000h–8BFFFh 16
SA3 SG3 01800h–01FFFh 2 SA42 8C000h–8FFFFh 16
SA4 SG4 02000h–027FFh 2 SA43
SG17
90000h–93FFFh 16
SA5 SG5 02800h–02FFFh 2 SA44 94000h–97FFFh 16
SA6 SG6 03000h–037FFh 2 SA45 98000h–9BFFFh 16
SA7 SG7 03800h–03FFFh 2 SA46 9C000h–9FFFFh 16
SA8
SG8
04000h–07FFFh 16 SA47
SG18
A0000h–A3FFFh 16
SA9 08000h–0BFFFh 16 SA48 A4000h–A7FFFh 16
SA10 0C000h–0FFFFh 16 SA49 A8000h–ABFFFh 16
SA11
SG9
10000h–13FFFh 16 SA50 AC000h–AFFFFh 16
SA12 14000h–17FFFh 16 SA51
SG19
B0000h–B3FFFh 16
SA13 18000h–1BFFFh 16 SA52 B4000h–B7FFFh 16
SA14 1C000h–1FFFFh 16 SA53 B8000h–BBFFFh 16
SA15
SG10
20000h–23FFFh 16 SA54 BC000h–BFFFFh 16
SA16 24000h–27FFFh 16 Bank 1 (Note 18)
SA17 28000h–2BFFFh 16 SA55
SG20
C0000h–C3FFFh 16
SA18 2C000h–2FFFFh 16 SA56 C4000h–C7FFFh 16
SA19
SG11
30000h–33FFFh 16 SA57 C8000h–CBFFFh 16
SA20 34000h–37FFFh 16 SA58 CC000h–CFFFFh 16
SA21 38000h–3BFFFh 16 SA59
SG21
D0000h–D3FFFh 16
SA22 3C000h–3FFFFh 16 SA60 D4000h–D7FFFh 16
SA23
SG12
40000h–43FFFh 16 SA61 D8000h–DBFFFh 16
SA24 44000h–47FFFh 16 SA62 DC000h–DFFFFh 16
SA25 48000h–4BFFFh 16 SA63
SG22
E0000h–E3FFFh 16
SA26 4C000h–4FFFFh 16 SA64 E4000h–E7FFFh 16
SA27
SG13
50000h–53FFFh 16 SA65 E8000h–EBFFFh 16
SA28 54000h–57FFFh 16 SA66 EC000h–EFFFFh 16
SA29 58000h–5BFFFh 16 SA67
SG23
F0000h–F3FFFh 16
SA30 5C000h–5FFFFh 16 SA68 F4000h–F7FFFh 16
SA31
SG14
60000h–63FFFh 16 SA69 F8000h–FBFFFh 16
SA32 64000h–67FFFh 16 SA70 SG24 FC000h–FC7FFh 2
SA33 68000h–6BFFFh 16 SA71 SG25 FC800h–FCFFFh 2
SA34 6C000h–6FFFFh 16 SA72 SG26 FD000h–FD7FFh 2
SA35
SG15
70000h–73FFFh 16 SA73 SG27 FD800h–FDFFFh 2
SA36 74000h–77FFFh 16 SA74 SG28 FE000h–FE7FFh 2
SA37 78000h–7BFFFh 16 SA75 SG29 FE800h–FEFFFh 2
SA38 7C000h–7FFFFh 16 SA76 SG30 FF000h–FF7FFh 2
SA77 (Note 17) SG31 FF800h–FFFFFh 2

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7. Device Operations
This section describes the read, program, erase, simultaneous read/write operations, and reset features of the Flash devices.
Operations are initiated by writing specific commands or a sequence with specific address and data patterns into the command
register (see Table 5). The command register itself does not occupy any addressable memory location; rather, it is composed of
latches that store the commands, along with the address and data information needed to execute the command. The contents of the
register serve as input to the internal state machine; the state machine outputs dictate the function of the device. Writing incorrect
address and data values or writing them in an improper sequence may place the device in an unknown state, in which case the
system must write the reset command in order to return the device to the reading array data mode.
7.1 Device Operation Table
The device must be set up appropriately for each operation. Table 5 describes the required state of each control pin for any
particular operation.
Legend
L = Logic Low = VIL, H = Logic High = VIH, X = Don’t care.
Notes
20. WP# controls the two outermost sectors of the top boot block or the two outermost sectors of the bottom boot block.
21. DQ0 reflects the sector PPB (or sector group PPB) and DQ1 reflects the DYB.
Table 5. Device Bus Operation
Operation CE# OE# WE# RESET# CLK ADV# Addresses Data
(DQ0–DQ31)
Read LLH H X X A
IN DOUT
Asynchronous Write LH L H X X A
IN DIN
Synchronous Write LH L H A
IN DIN
Standby (CE#) H X X H H X X High-Z
Output Disable L H H H X X High-Z High-Z
Reset X X X L X X X High-Z
PPB Protection Status (Note 2) LLH H X X
Sector Address,
A9 = VID,
A7 – A0 = 02h
00000001h, (protected)
A6 = H
00000000h (unprotect)
A6 = L
Burst Read Operations
Load Starting Burst Address LX H H A
IN X
Advance Burst to next address
with appropriate Data presented
on the Data bus
L L H H H X Burst Data Out
Terminate Current Burst Read Cycle H X H H X X High-Z
Terminate Current Burst
Read Cycle with RESET# X X H L X X X High-Z
Terminate Current Burst Read Cycle;
Start New Burst Read Cycle LH H H A
IN X

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7.2 Asynchronous Read
All memories require access time to output array data. In an asynchronous read operation, data is read from one memory location at
a time. Addresses are presented to the device in random order, and the propagation delay through the device causes the data on its
outputs to arrive asynchronously with the address on its inputs.
The internal state machine is set for asynchronously reading array data upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this
mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce
valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered.
The device has two control functions which must be satisfied in order to obtain data at the outputs. CE# is the power control and
should be used for device selection (CE# must be set to VIL to read data). OE# is the output control and should be used to gate data
to the output pins if the device is selected (OE# must be set to VIL in order to read data). WE# should remain at VIH (when reading
data).
Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable access time (tCE) is the
delay from the stable addresses and stable CE# to valid data at the output pins. The output enable access time (tOE) is the delay
from the falling edge of OE# to valid data at the output pins (assuming the addresses have been stable for at least a period of tACC-
tOE and CE# has been asserted for at least tCE-tOE time). Figure 1 shows the timing diagram of an asynchronous read operation.
Figure 1. Asynchronous Read Operation
Note
22.Operation is shown for the 32-bit data bus. For the 16-bit data bus, A-1 is required.
Refer to Asynchronous Operations on page 52 for timing specifications and to Figure 19 Conventional Read Operations Timings
on page 53 for another timing diagram. ICC1 in the DC Characteristics table represents the active current specification for reading
array data.
D0 D1 D2 D3 D3
CE#
CLK
ADV#
Addresses
Data
OE#
WE#
IND/WAIT#
VIH
Float VOH
Address 0 Address 1 Address 2 Address 3
Float