Datum 5094-101 User manual

-c:c·1

1111111

PERIPHERAL

EQUIPMENT

DIVISION

INSTRUCTION

MANUAL

MODEL

5094-101

TWO-PORT

MULTIPLEXER

PUBLICATION

NO.

1802.3

••••••••••••••••

••••••••••

SEPTEMBER

1974

DATUM

I

NC.

1363

South

State

College

Boulevard

Anaheim,

California

92806

PERIPHERAL

EQUIPMENT

DIVISION

INSTRUCT

ION

MANUAL

MODEL

5094-101

TWO-PORT

MULTIPLEXER

PUBLICATION

NO.

1802.3

Section

II

111

IV

v

TABLE

OF

CONTENTS

GENERAL

DESCRIPTION

1•1

1•2

1.3

1.4

Introduction

••••••••••

0

•••••••••••••••.••

Purpose

of

Equipment

•••••••.••••••••••••

Physical

Description

•••••••••••.••••••••

Functional

Description

••••••••••••••••••

INSTALLATION

AND

OPERATION

2.

1

2.2

2.

1

2.2.2

2.3

Genera1

Installation

••••.•••••••••

~

•••••••••••••

Power

•••.•••••••••••••••••••••••••••••

• •

Interface

Connectors

••••••••••••••••••••

Operation

•••••••••••••••••••••••••••••••

THEORY

OF

OPERATION

3. 1

3.2

3.3

3

.3.

1

3.3.2

3.3.3

3.3.4

3.3.5

3.4

3.5

Genera1

Block Diagram

Description

•••••••••••••••

Logic

Description

•••••.•••••••••••••••••

Cont

ro

1

Log

i c

••••••

~

•••.••••••••••••••••

Data Input

Bus

••••••••.•••••••••••••••••

Address

Bus

••••.••••••••••••••••••••••••

Data Output

Bus

•••••••••••••••••••••••.•

Control

Signals

Repowering

•••••••••.••••

Logic Elements

······················~···

Logic

Symbols

•..•.•.••••••••••••.•.•••••

MAINTENANCE

4.

1

4.2

4.2.l

DRAWINGS

General

Maintenance Aids

•••.••••.••.••••••••••••

Drawings

••••••••••••••••••••••••••••••••

1-1

1-2

2-1

2-2

3-1

3-2

3-3

4-1

1.1

INTRODUCTION

SECTION

I

GENERAL

DESCRIPTION

This

technical

manual

contains

operating,

installation,

and

maintenance

information

for

the

DATUM

Model

5094-101

Multiplexer.

The

manual

is

organized

in

five

sections.

Section

I

contains

general

phy-

sical

and

functional

information,

Section

II

contains

information

for

installing

and

operating

the

Multiplexer,

and

Section

Ill

includes

Mul-

tiplexer

theory

at

the

block

diagram and

logic

level.

Sections

IV

and

V,

respectively,

contain

maintenance

information

and

the

reference

draw-

ings.

1.2

PURPOSE

OF

EQUIPMENT

The

Model

5094-101

Multiplexer

allows

the

connection

of

two

peripheral

devices

to

the

IBM

1130

SAC

channel.

A

typical

application

would be

the

connection

of

a

magnetic

tape

system and a

high-speed

line

printer

to

the

IBM

1130.

1.3

PHYSICAL

DESCRIPTION

The

Multiplexer

(Drawing 5094-101)

consists

of

a

printed

cir-

cuit

card

and a power

supply

mounted

in

a 19"

x·

3.5

11

x

13

11

box. The box

is

furnished

with

standard

RETMA

hole

spacing

for

the

3.5

11

high

front

panel.

The

front

panel

contains

the

power

on-off

pushbutton,

and

the

rear

panel

contains

the

connectors

for

interfacing

the

computer and

per-

ipheral

devices.

1.4

FUNCTIONAL

DESCRIPTION

The

Model

5094-101

Multiplexer

receives

and

repowers

all

the

signals

to

and from

the

computer and

peripheral

devices.

It

controls

and

determines

the

priority

of

the

cycle

steal

operations

of

the

two

peripheral

devices.

Connectors

Jl02

and J103

are

identical

to

the

IBM

SAC

channel.

1-2

SECTION

11

INSTALLATION

AND

OPERATION

2.

1

GENERAL

This

section

of

the

manual

describes

the

installation

and

operation

of

the

Model

5094-101

Multiplexer.

2.2

INSTALLATION

The

Multiplexer

is

shipped

fully

assembled

and

ready

for

oper-

ation.

No

assembly

is

required

other

thar'I

connection

of

the

Multi_Plexer

to

a

source

of

AC

power and

connection

of

the

computer and

peripheral

device

interface

cables.

2.2.

l Power

The

Multiplexer

operates

on

120/230-volt,

60 Hz,

single-phase

power. Connect

the

AC

source

to

the

Hubbel

connector

provided

on

the

rear

panel

of

the

Multiplexer.

Ensure

that

a 2-ampere

Slo~Blo

fuse

is

installed

in

the

fuse

socket.

2.2.2

Interface

Connectors

The

functions

of

the

interface

connectors

located

at

the

rear

of

the

Multiplexer

are

listed

in

Table

2.1.

2-1

The

signal

cable

from

the

IBM

1130

SAC

channel

is

plugged

into

connector

JlOl.

The

signal

cable

from

the

higher

priority

device

connects

to

Jl02,

and

the

signal

cable

from

the

lower

priority

device

connects

to

Jl03.

2.3

OPERATION

If

only

one

device

is

to

be

operated,

the

connector

for

the

second

device

must be

left

open.

It

makes

no

difference

which

connec-

tor

is

used

for

a

single

device.

Tab 1e

2.

1.

I

nte

rf

ace

Connector

Functions

CONNECTOR

FUNCTION

JlOl

Interface

to

the

computer

J

lo2

Channel I ] I -

highest

priority

Jl

03

Channel •

2•

-1

owe

st pr io r i ty

2:-2

SECTION

Ill

THEORY

OF

OPERATION

3.1

GENERAL

The

theory

of

operation

describes

the

detailed

functions

of

the

Model

5094-101

Multiplexer.

The

descriptions

begin

at

the

block

diagram

level

and

then

proceed

through

descriptions

of

the

logic

dia-

gram.

3.2

BLOCK

DIAGRAM

DESCRIPTION

(DRAWING

800526)

The

block

diagram shows

the

flow

of

the

data

to

and from

the

computer and

peripheral

devices.

The

arrows show

the

direction

of

the

data

flow.

The

sheet

numbers

shown

in

each

box

refer

to

the

sheet

numbers

of

Drawing 76085 where

that

particular

logic

is

shown.

The

control

lines

(out

of

the

control

logic)

which

control

some

of

the

gating

functions

are

now

shown.

The

block

diagram shows

the

IBM

1130

SAC

channel

on

the

right-

hand

side

of

the

drawing;

the

two

peripheral

devices

are

shown on

the

left-hand

side.

The

SAC

Device #1

is

the

higher

priority

device.

3.3

LOGIC

DESCRIPTION

3

.3.

l

Control

Logic (76085,

Sheet

1)

This

logic

handles

the

priority

of

the

cycle

steal

requests

from

the

two

peripheral

devices.

3-1

Flip-flop

REQ

is

the

channel

cycle

steal

request.

B

is

used

to

synchronize

the

incoming

cycle

steal

request

with

the

phase A

signal

from

the

computer

when

the

computer

is

in

the

wait

mode

and

no

T

clocks

are

available.

SELl

determines

which

device

is

to

be

serviced.

3.3.2 Data Input Bus (76085,

Sheet

2)

This

logic

receives

the

16-bit

data

words from

the

two

peri-

pheral

devices

and

OR

1s them

to

drive

the

data

input

bus

of

the

SAC

channe1.

3.3.3 Address

Bus

(76085,

Sheet

3)

This

logic

receives

the

16-bit

address

words from

the

two

per-

ipheral

devices

and

gates

one

of

them, depending on which

is

being

ser-

Viced

at

the

time,

out

onto

the

address

bus

of

the

SAC

channel.

3.3.4

Data Output

Bus

(76085,

Sheet

4)

This

logic

receives

the

16-bit

data

word from

the

SAC

channel

and repowers

it

for

the

two

peripheral

devices.

3.3.5

·control

Signals

Repowering (76085,

Sheets

5 and 6)

This

logic

receives

the

control

signals

from

the

SAC

channel

and repowers them

for

the

two

peripheral

devices.

3.4

LOGIC

ELEMENTS

All

logic

elements

are

Signetics

TTL

or

Utilogic

integrated

circuits

in

dua1-inline

packages.

Logic diagrams

for

these

elements

can be found

at

the

back

of

this

section.

3-2

The

logic

elements

are

mounted in

wire-wrap

sockets

on

printed

circuit

cards.

All

circJit

interconnections

are

made

by

wire-wrap

con-

nections.

Circuit

elements

are

easily

replaceable

by removing them from

their

sockets

and

replacing

them

with

equ!valent

elements.

Integrated

circuits

are

used

throughout

wherever

possible.

Exceptions

are

relay

and

lamp

drivers.

3.5

LOGIC

SYMBOLS

The

logic

symbols

are

derived

from MIL-STD-806B, and

they

are

utilized

in such a manner

that

signals

can be

traced

through

the

logic

in

terms

of

''high

11

and

"low"

(+2.5

to

+5V)

and

(OV)

by

examination

of

the

logic

symbols

without

the

need

to

memorize

the

electrical

characteristics

(NANO,

NOR,

AND,

OR,

etc.)

of

the

circuits

(which most

other

logic

draw-

ing schemes

require).

The

"high"

and "low"

signal

level

indication

is

illustrated

by

a

straight

line

for

a

11

high"

signal

and a

small

circle

for

a

11

low

11

·signal

level.

The

following

symbol

shapes

are

used:

D

"OR"

SYMBOL

D

11

AND

11

SYMBOL

The use

of

straight

lines

or

circles

at

inputs

and

outputs

of

these

basic

symbols

completely

defines

the

function

the

circuit

performs,

the

input

signal

levels

required

to

activate

the

circuit,

and

the

output

signal

level

when

the

circuit

is

activated.

3-3

Some

examples

follow:

) >

NOR

Either

(or

both)

'ii

Inputs

11

High

11

·

TYPE

7402

INTEGRATED

CIRCUIT

-~o

Both

Inputs

11

Low

11

NANO

Output

is

11

Low

11

Output

is

11

High

11

) )

OR

Either

A

(or

both)

Inputs

11

High"

TYPE

SP384

INTEGRATED

CIRCUIT

Output

is

11

High"

-Oo~

Both

Inputs

''Low''

3-4

AND

Output

is

"Low'

1

0

NOR

Either

A Output

(or

both)

is

Inputs

11

High

11

''Low''

TYPE

7400

INTEGRATED

CIRCUIT

··-

.

Both

Inputs

11

High

11

NANO

Output

is

11

LovJ';

Note

that

the

Type 7402

integrated

circuit

can

be

used

as

a

"high"

input

NOR

or

a

11

low

1

input

NANO.

Note

also

that

the

Type 7400

integrated

circuit

can

be

used

as

a

11

low

1

input

NOR

or

a

'.'high"

input

NANO.

Note

that

the

Type

SP

384

integrated

circuit

can

be

used

as

. a

"high"

input

OR

or

a

11

low

11

input

AND.

A

11

low

wired

OR

11

or

a

''high

wired

AND

11

function

can

also

be

Implemented

with

certain

integrated

circuits

by

tying

the

outputs

together

and

adding

an

external

discrete

resistor

"pull

up."

+5

"Pull

Up

11

'Resistor

1.

11

Low

Wired

OR"

(Any

NANO

gate

output

goes

11

Jow

11

the

bus

goes

11Jow.

11

)

2.

11

Hi gh

Wired

AND"

All

NANO

gate

outputs

must

be

11

high

11

"'frlorder

for

the

bus

to

be

"high.

11

3-5

Four-To-Ten-Line

Decoder

Decodes

"High"

8-4-2-1

BCD

Inputs

2 4 8

0 2 3 4 5 6 7 8 9

,

11.

I I I I I I I t

"/'

Decoded

Output

Goes

11

Low

11

114..;TO-lO-LINE

DECODER"

SYMBOL

J-K

Flip-Flop

sets

ff

(when 1'1ow'1)

J

enable·

(when

11

high

11

)

·.Clock

(upon

transition

to

11

Jow

11

)

K

enable

(when

"high")

resets

ff

(when

11

Jow

11

)

J

9

CL

K

3-6

6

s

R.

J

Q

True

output.

(ff

·is

11

set

11

when Q

is.

11

high

11

)

False

output.

(ff

is

11

reset"

when Q

is

11

high

11

)

J-K

FLIP-FLOP

TRUTH

TABLE

Input

Levels

Flip-Flop

State

Before

C1ock

After

Clock

J K

Low

Same

as

Before

Clock

Low

High

Reset

,

High

Low

Set

High High

Opposite

of

Be-

fore

Clock

As

illustrated

in

the

Truth

Table,

the

J-K

flip-flop

has

no

"forbidden"

combination

for

its

J and K

inputs.

If

both

inputs

are

enabled,

the

clock

merely

causes

the

flip-flop

to

toggle

to

the

.QE.E.Q.-

site

state.

3-7

SECTION

IV

MAINTENANCE

4.

I

GENERAL

This

section

contains

corrective

and

preventive

maintenance

information

for

the

Model

5094-101

Multiplexer.

Effective

maintenance

of

the

Multiplexer

requires

an

adequate

understanding

of

the

logic

theory.

4.2

MAINTENANCE

AIDS

The

maintenance

aids

associated,with

the

Multiplexer

are

the

drawings in

Section

V.

4.

2.

I Drawings

The drawing complement

consists

of

the

following:

a.

Top

Assembly Drawing 5094-101

·b.

Block Diagram 800526

c.

Logic Diagrams 76085

d.

Card Assembly Drawings 76085

e.

Power Supply

Schematic

940015

f.

Power Supply Assembly 940015

g.

AC

Wiring Diagram 800918

The

block

diagram

illustrates

the

system

in

terms

of

each

functional

logic

block.

The

sheet

number

in

each

block

refers

to

the

sheet

number

of

Drawing 76085 where

that

logic

is

located.

4-1

The

logic

diagrams

furnish

the

logic

mechanization

details

of

the

Multiplexer.

The.physical

location

of

each

logic

element

is

designated

on

the

diagrams

by

chip

location

on

the

card.

The

chip

location

designation

corresponds

to

the

column

(A

through

N)

and

row

(1

through

6) in which

the

chip

is

located

on

the

card.

The

IC

chip

type

can be

determined

either

by

examination

of

the

chip

on

the

card

in

the

column/row

given,

or

by

inspection

of

the

assembly drawing

for

the

card.

4-2

Drawing

Number

Rev.

800526

None

940015

c

940015

c

5094-101

A

76085,

of

7 C

76085,

2

of

7 C

76085,

3

of

7 C

76085,

4

of

7 C

76085,

5

of

7 C

76085,

6

of

7 C

76085,

7

of

7 C

800918

None

SECTION

V

DRAWINGS

Title

1130

Multiplexer

Block Diagram

Power Supply Assembly

Power

Supply Schematic

Top

Assembly,

1130

Multiplexer

1130

Multiplexer

Control

1t30

Multiplexer

Data Input

Bus

Address

Bus

·

Data Output

Bus

Re-Powering

Control

Signals

Re-Powering

Control

Signals

Re-Powering

AC

Wiring Diagram

5-1

SAC

DEVICE

#1

SAC

DEVICE

#2

Jl02

I

,I

I

,I

'.

I

'1

LTR

DATA

INPUT

ADORE

SS

DATA

OUTPUT

REVISIONS

DESCRIPTION

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Datum 5094-101 User manual

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