DDC Total-AceXtreme MIL-STD-1553 Guide

Total-AceXtreme®
Ultra-Small, Ultra-Low Power
MIL-STD-1553 Single Package Solution
Data Sheet
© 2011 Data Device Corporation. All trademarks are the property of their respective owners.
Model: BU-67301B
For more information: www.ddc-web.com/BU-67301B
• Small, Fully Integrated 1553 Terminal with
Transformers Inside:
- 16 x 16 x 4.7 mm (0.63 x 0.63 x 0.185 in.)
- Protocol, RAM, Transceivers and Transformers in a
Single Package
- 324 Ball JEDEC Design Guide 4.5 Standard Size
Fine Pitch Ball Grid Array with 0.8 mm Ball Pitch
• Ultra Low Transceiver Power
• Comprehensive Built-in Self Test
• Versatile User Selectable High-Speed Backend for
PCI or CPU Interface
- Access Time as low as 12.5ns
- DMA Engine with 264MB/sec Burst Transfer Rate
• 1 Dual Redundant MIL-STD-1553 Channel
- BC or Multi-RT with Concurrent Bus Monitor
- Supports MIL-STD-1553 A/B and MIL-STD-1760
- 2 Mb (64K x 36) RAM
- Tx Inhibit Ball for MT Only Applications
- BC Disable Ball for RT Only Applications
- 48-bit/100ns Time Stamp
- IRIG-106 Chapter 10 MT Support
• Supports JTAG Boundary Scan
• IRIG-B Input
• 8 Digital Discrete I/O
• Hardware/Software Development Kit with PCI
Evaluation Board and Reference Design Artifacts
Features
World's smallest, ultra low power, fully integrated MIL-STD-1553 BGA package, complete with 1553 protocol,
2 Mb (64K x 36) RAM, transceivers, and isolation transformers inside a single package — saves board space and
simplifies 1553 design and layout. Available with development kit to ease integration.

DDC's Data Networking Solutions
MIL-STD-1553 | ARINC 429 | Fibre Channel
As the leading global supplier of data bus components, cards, and software solutions for the military, commercial,
and aerospace markets, DDC’s data bus networking solutions encompass the full range of data interface
protocols from MIL-STD-1553 and ARINC 429 to USB, and Fibre Channel, for applications utilizing a spectrum of
form-factors including PMC, PCI, Compact PCI, PC/104, ISA, and VME/VXI.
DDC has developed its line of high-speed Fibre Channel and Extended 1553 products to support the real-time
processing of field-critical data networking netween sensors, compute notes, data storage displays, and weapons
for air, sea, and ground military vehicles.
Whether employed in increased bandwidth, high-speed serial communications, or traditional avionics and ground
support applications, DDC's data solutions fufill the expanse of military requirements including reliability,
determinism, low CPU utilization, real-time performance, and ruggedness within harsh environments. Out use of
in-house intellectual property ensures superior mutli-generational support, independent of the life cycles of
commercial devices. Moreover, we maintain software compatibility between product generations to protect our
customers' investments in software development, system testing, and end-product qualification.
DDC provides an assortment of quality MIL-STD-1553 commercial, military, and COTS grade cards and
components to meet your data conversion and data interface needs. DDC supplies MIL-STD-1553 board level
products in a variety of form factors including AMC, USB, PCI, cPCI, PCI-104, PCMCIA, PMC, PC/104, PC/104-
Plus, VME/VXI, and ISAbus cards. Our 1553 data bus board solutions are integral elements of military, aerospace,
and industrial applications. Our extensive line of military and space grade components provide MIL-STD-1553
interface solutions for microprocessors, PCI buses, and simple systems. Our 1553 data bus solutions are
designed into a global network of aircraft, helicopter, and missle programs.
DDC also has a wide assortment of quality ARINC-429 commercial, military, and COTS grade cards and
components, which will meet your data conversion and data interface needs. DDC supplies ARINC-429 board
level products in a variety of form factors including AMC, USB, PCI, PMC, PCI-104, PC/104 Plus, and PCMCIA
boards. DDC's ARINC 429 components ensure the accurate and reliable transfer of flight-critical data. Our 429
interfaces support data bus development, validation, and the transfer of flight-critical data aboard commercial
aerospace platforms.
MIL-STD-1553
ARINC 429
DDC has developed its line of high-speed Fibre Channel network access controllers and switches to support the
real-time processing demands of field-critical data networking between sensors, computer nodes, data storage,
displays, and weapons, for air, sea, and ground military vehicles. Fibre Channel's architecture is optimized to
meet the performance,reliability, and demanding environmental requirements of embedded, real time, military
applications, and designed to endure the multi-decade life cycle demands of military/aerospace programs.
Fibre Channel

DATA DEVICE CORPORATION
Data Device Corporation DS-BU-67301B-G
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i
ULTRA-SMALL, ULTRA-LOW POWER MIL-STD-1553
SINGLE PACKAGE SOLUTION
BU-67301B DATA SHEET
The information provided in this Data Sheet is believed to be accurate; however, no
responsibility is assumed by Data Device Corporation for its use, and no license or rights
are granted by implication or otherwise connection therewith.
Specifications are subject to change without notice.
Please visit our Web site at http://www.ddc-web.com/ for the latest information.
All rights reserved. No part of this Data Sheet may be reproduced or transmitted in any
form or by any mean, electronic, mechanical photocopying recording, or otherwise,
without the prior written permission of Data Device Corporation.
105 Wilbur Place
Bohemia, New York 11716-2426
Tel: [phone], Fax: [phone]
World Wide Web - http://www.ddc-web.com
For Technical Support -1-800-DDC-5757 ext. 7771
United Kingdom -Tel: [phone], Fax: [phone]
France -Tel: [phone], Fax: [phone]
Germany - Tel: [phone], Fax: [phone]
Japan -Tel: [phone], Fax: [phone]
Asia -Tel: [phone] © 2010 Data Device Corp.

RECORD OF CHANGE
Data Device Corporation DS-BU-67301B-G
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Revision Date Pages Description
Pre Rev A Sept., 2010 All Preliminary release
Rev. A Sept., 2011 All Initial Release
Rev. B Dec., 2011 6, 7, 9, 38, 113, 25-93, 95, 101-
115
Table 1: removed part numbers from Supply Voltage
section, changed Storage Temperature Max. from:
+150°C to: +125°C., added Ramp Rate specs, added
Junction Temperature (TJ)
Table 7: Changed Tah min from 2ns to 7ns.
Table 25: removed redundant B1 listing in NC section.
Section 6: changed heading to Host Interface.
Added Section 7: Power Inputs
Tables 15 - 22: Added Pullup/Pulldown column and
values
Rev. C Dec., 2011 10, 15, 96-97, 99,
100, 115
Table 1: Eliminated reference to “(Hottest Die)”.
Figure 5: Eliminated “MT 100 µs Timer (16-bit)” block.
Added Figure 56, Timing of CLK_IN, Logic_VDDIO,
PLL_+1.8V, and Core_+1.8V.
Figure 58: Made corrections
Figure 59: Made corrections
Table 22: Changed second column signal description
for nSINGEND(I).
Rev. D January, 2012
7, 36-39, 55-58,
89. 96-98, 104,
107-108, 110,
122, 125
Figure 2: Added nPOR and PLL_LOCKED
Figures 7-10 and Figures 19-22: Added nPOR,
supervisor circuit, and PLL_LOCKED, modifed use of
nMSTCLR
Figure 48: Added nPOR and PLL_LOCKED
Paragraph 7.2: updated power-up sequence, modified
Figure 56
Table 15: Added nPOR and PLL_LOCKED
Table 18: Modified RST#
Table 19: Modified nMSTCLR
Table 26: Added nPOR and PLL_LOCKED
Figure 61: Added nPOR and PLL_LOCKED
Rev. E Feb., 2012 98 Updated Figure 56
Rev. F June, 2012 7, 104, 105 Figure 2: Corrected CH. A 1553 Stub designation
Tables 15 – 17: Adjusted column widths
Rev. G January, 2014 11, 89 Updated Table 1 and Figure 48

TABLE OF CONTENTS
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1PREFACE.............................................................................................................1
1.1 Text Usage..................................................................................................................1
1.2 Standard Definitions....................................................................................................1
1.3 Trademarks.................................................................................................................1
1.4 Technical Support .......................................................................................................2
2OVERVIEW ..........................................................................................................3
2.1Features......................................................................................................................3
2.2 Specifications..............................................................................................................8
2.3 Additional Support Documents..................................................................................12
2.4 Total-AceXtreme® Development Kit..........................................................................13
3MIL-STD-1553 MODES AND ARCHITECTURE................................................15
3.1 Bus Controller Mode..................................................................................................15
4GLOBAL FEATURES ........................................................................................22
4.1 Transceivers and Isolation Transformers...................................................................22
4.2 Time Tags.................................................................................................................22
4.3 Local Timer ...............................................................................................................22
4.4 DMA Controller..........................................................................................................23
5BUILT-IN TEST ..................................................................................................25
5.1 Total-AceXtreme® Self-Test......................................................................................25
5.2 JTAG Boundary Scan................................................................................................25
6HOST INTERFACE ............................................................................................27
6.1 Host Interface Configuration Options.........................................................................27
6.2 Parallel CPU Interface...............................................................................................27
6.3 Asynchronous Interface Mode...................................................................................35
6.4 Synchronous Host Processor Interface .....................................................................51
6.5 PCI Interface.............................................................................................................88
7POWER INPUTS................................................................................................97
7.1 Decoupling Capacitors..............................................................................................97
7.2 Power Sequencing....................................................................................................97
8MIL-STD-1553 TRANSCEIVER OPTIONS ......................................................100
8.1 Using the Internal Transceivers...............................................................................100
8.2 Using External Fiber Optic Transceivers .................................................................102
9THERMAL MANAGEMENT FOR TOTAL-ACEXTREME................................104
10 REGISTER AND MEMORY ADDRESSING.....................................................107
10.1 Memory Address Space..........................................................................................107
10.2 Register Address Space..........................................................................................107

TABLE OF CONTENTS
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11 TOTAL-ACEXTREME® SIGNALS...................................................................108
11.1 Signal Descriptions and Pinout by Functional Groups.............................................108
11.2 Host Interface Signals.............................................................................................110
11.3 Pinout Table............................................................................................................124
11.4 Total-AceXtreme® Pin Diagram ..............................................................................128
12 MECHANICAL OUTLINE.................................................................................129
13 ORDERING INFORMATION ............................................................................130

LIST OF FIGURES
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Figure 1. BU-67301B Total-AceXtreme® ..................................................................................6
Figure 2. Total-AceXtreme® Block Diagram..............................................................................7
Figure 3. Bus Controller Block Diagram - Remote Terminal Operation...................................16
Figure 4. Remote Terminal Block Diagram - Monitor Mode Operation....................................18
Figure 5. Monitor Block Diagram - Advanced Data Handler (ADH).........................................19
Figure 6. PCI DMA Block Diagram - Digital I/O .......................................................................23
Figure 7. 32-bit, Non-Multiplexed Address, Asynchronous Interface.......................................37
Figure 8. 32-bit, Multiplexed Address, Asynchronous Interface...............................................38
Figure 9. 16-bit, Non-Multiplexed Address, Asynchronous Interface.......................................39
Figure 10. 16-bit, Multiplexed Address, Asynchronous Interface.............................................40
Figure 11. Asynchronous Non-Multiplexed Address 32-bit Read Timing.................................43
Figure 12. Asynchronous Non-Multiplexed Address 32-bit Write Timing.................................44
Figure 13. Asynchronous Non-Multiplexed Address 16-bit Read Timing.................................45
Figure 14. Asynchronous Non-Multiplexed Address 16-bit Write Timing.................................46
Figure 15. Asynchronous Multiplexed Address 32-bit Read Timing ........................................47
Figure 16. Asynchronous Multiplexed Address 32-bit Write Timing.........................................48
Figure 17. Asynchronous Multiplexed Address 16-bit Read Timing ........................................49
Figure 18. Asynchronous Multiplexed Address 16-bit Write Timing.........................................50
Figure 19. 32-bit, Non-Multiplexed Address, Synchronous Interface.......................................56
Figure 20. 32-bit, Multiplexed Address, Synchronous Interface ..............................................57
Figure 21. 16-bit, Non-Multiplexed Address, Synchronous Interface.......................................58
Figure 22. 16-bit, Multiplexed Address, Synchronous Interface ..............................................59
Figure 23. Synchronous, Non-Multiplexed Address - 32-bit Single-Word Memory Read Timing
..........................................................................................................................................63
Figure 24. Synchronous, Non-Multiplexed Address - 32-bit Single-Word Register Read Timing
..........................................................................................................................................64
Figure 25. Synchronous, Non-Multiplexed Address - 32-bit Single-Word Write Timing...........65
Figure 26. Synchronous, Non-Multiplexed Address 16-bit - Single-Word Memory Read Timing
..........................................................................................................................................66
Figure 27. Synchronous, Non-Multiplexed Address 16-bit - Single-Word Register Read Timing
..........................................................................................................................................67
Figure 28. Synchronous, Non-Multiplexed Address - 16-bit Single-Word Memory Write Timing
..........................................................................................................................................68
Figure 29. Synchronous, Non-Multiplexed Address - 16-bit Single-Word Register Write Timing
..........................................................................................................................................69
Figure 30. Synchronous, Multiplexed Address 32-bit - Single-Word Memory Read Timing ....70
Figure 31. Synchronous, Multiplexed Address 32-bit - Single-Word Register Read Timing....71
Figure 32. Synchronous, Multiplexed Address 32-bit Single-Word Write Timing.....................72
Figure 33. Synchronous, Multiplexed Address 16-bit - Single-Word Memory Read Timing ....73
Figure 34. Synchronous, Multiplexed Address 16-bit Single-Word Register Read Timing......74
Figure 35. Synchronous, Multiplexed Address 16-bit Single-Word Memory Write Timing.......75
Figure 36. Synchronous, Multiplexed Address 16-bit Single-Word Register Write Timing ......76
Figure 37. Synchronous, Non-Multiplexed Address, 32-bit - Sequential Burst Memory Read
Transfer Timing .................................................................................................................77

LIST OF FIGURES
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Figure 38. Synchronous, Non-Multiplexed Address - 32-bit Sequential Burst Write Transfer
Timing................................................................................................................................78
Figure 39. Synchronous, Non-Multiplexed Address 32-bit - Random Burst Write Transfer
Timing................................................................................................................................79
Figure 40. Synchronous, Non-Multiplexed Address - 16-bit Sequential Burst Memory Read
Transfer Timing.................................................................................................................80
Figure 41. Synchronous, Non-Multiplexed Address - 16-bit Sequential Burst Write Transfer
Timing................................................................................................................................81
Figure 42. Synchronous, Non-Multiplexed Address - 16-bit Random Burst Write Transfer
Timing................................................................................................................................82
Figure 43. Synchronous, Multiplexed Address - 32-bit Sequential Burst Memory Read
Transfer Timing.................................................................................................................83
Figure 44. Synchronous, Multiplexed Address - 32-bit Sequential Burst Write Transfer Timing
..........................................................................................................................................84
Figure 45. Synchronous, Multiplexed Address - 16-bit Sequential Burst Memory Read
Transfer Timing.................................................................................................................85
Figure 46. Synchronous, Multiplexed Address - 16-bit Sequential Burst Write Transfer Timing
..........................................................................................................................................86
Figure 47. Timing for Assertion of CPU_nSTOP - Output During Synchronous Burst Write
Transfer.............................................................................................................................87
Figure 48. Interface Between Host PCI Bus and Total-AceXtreme® - PCI Signal List............90
Figure 49. PCI Parametric Timing ...........................................................................................93
Figure 50. PCI Slave Burst Write.............................................................................................93
Figure 51. PCI Slave Burst Read - PCI Initiator Timing...........................................................94
Figure 52. PCI DMA Start Delay..............................................................................................95
Figure 53. PCI DMA Burst Write..............................................................................................95
Figure 54. PCI DMA Burst Read..............................................................................................96
Figure 55. Recommended +1.8V_PLL Filter Network.............................................................97
Figure 56. Power-Up Initialization Sequence Timing...............................................................99
Figure 57. Total-AceXtreme® Internal Transceiver and Isolation Transformer Connection to
MIL-STD-1553 Bus..........................................................................................................100
Figure 58. Mandatory Connections for Integrated Transceivers Connection to External
Transceivers....................................................................................................................101
Figure 59. Total-AceXtreme Interface to External McAir Transceiver....................................102
Figure 60. Total-AceXtreme® Interface to Fiber Optic Transceivers.....................................103
Figure 61. Total-AceXtreme® Pin Diagram...........................................................................128
Figure 62. Total-AceXtreme® Mechanical Outline Drawing ..................................................129

LIST OF TABLES
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Table 1. Total-AceXtreme® Series Specifications.....................................................................8
Table 2. Supported JTAG Functions .......................................................................................26
Table 3. Total-AceXtreme® Host Interface Configuration Options..........................................28
Table 4. Summary of the Operation of the nDATA_RDY Output Signal for Synchronous
Single-Word Memory and Register Accesses...................................................................33
Table 5. Asynchronous 16-bit Mode Configuration Options ....................................................36
Table 6. Asynchronous Transfers............................................................................................41
Table 7. Asynchronous Timing Information.............................................................................41
Table 8. Synchronous 16-bit Mode Configuration Options......................................................55
Table 9. Single-Word Synchronous Transfers.........................................................................60
Table 10. Synchronous Burst Transfers..................................................................................60
Table 11. Synchronous Timing Parameters.............................................................................61
Table 12. Total-AceXtreme® PCI Interface Characteristics.....................................................88
Table 13. PCI Bus Interface Signals........................................................................................91
Table 14. PCI Timing Information............................................................................................92
Table 15. Protocol Configuration...........................................................................................108
Table 16. JTAG Test .............................................................................................................109
Table 17. General Purpose Discrete I/O................................................................................109
Table 18. PCI Signals............................................................................................................110
Table 19. CPU Data Bus.......................................................................................................112
Table 20. RT Address Signals...............................................................................................117
Table 21. Miscellaneous Signals...........................................................................................117
Table 22. Additional Connections & Interface to External Transceiver..................................120
Table 23. MIL-STD-1553 Interface........................................................................................122
Table 24. Power and Ground Connections............................................................................122
Table 25. No User Connections.............................................................................................123
Table 26. Signal Pinout by Ball Location...............................................................................124

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1 PREFACE
This manual uses typographical conventions to assist the reader in understanding the
content. This section will define the text formatting used in the rest of the manual
1.1 Text Usage
•BOLD–indicates important information and table, figure, and chapter
references.
•BOLD ITALIC–designates DDC Part Numbers.
•Courier New–indicates code examples.
•<…> - indicates user-entered text or commands.
1.2 Standard Definitions
E2MA Extended Enhanced Mini-ACE®
EMACE Enhanced Mini-ACE®
BC MIL-STD-1553 Bus Controller
MT MIL-STD-1553 Monitor Terminal
RT MIL-STD-1553 Remote Terminal
Multi-RT MIL-STD-1553 Multiple Remote Terminals
ADH DDC Advanced Data Handler
Host Controller connected to the Host Interface
PCI Peripheral Component Interconnect
Rx Receive by RT
Tx Transmit by RT
Bcst Broadcast
MC Mode Code
BIT Built-In Test
PCB Printed Circuit Board
FGPI Flexible Generic Processor Interface
1.3 Trademarks
All trademarks are the property of their respective owners.

PREFACE
Data Device Corporation DS-BU-67301B-G
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1.4 Technical Support
In the event that problems arise beyond the scope of this manual, you can contact
DDC by the following:
US Toll Free Technical Support:
1-800-DDC-5757, ext. 7771
Outside of the US Technical Support:
1-631-567-5600, ext. 7771
Fax:
1-631-567-5758 to the attention of DATA BUS Applications
DDC Website:
www.ddc-web.com/ContactUs/TechSupport.aspx
Please note that the latest revisions of Software and Documentation are available for
download at DDC’s Web Site, www.ddc-web.com.

Data Device Corporation 3 DS-BU-67301B-G
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2 OVERVIEW
The Total-AceXtreme®provides a complete, compact solution for providing MIL-
STD-1553 interfaces for embedded systems. It provides the required isolation
transformers, MIL-STD-1553 transceivers, protocol, and 64K x 36 of internal memory
within a single BGA device. It is ideal for extended temperature range applications
where PCB space is at a premium, due to its very small size of just 16 mm x 16 mm,
and its low power dissipation.
The Host interface can be configured as either a flexible generic processor interface
(FGPI), or as a PCI initiator/target interface. The FGPI allows direct connection with
little or no glue logic to a variety of 16-, and 32-bit processors. The PCI interface
allows for a direct connection to a 32-bit PCI bus and supports PCI clock speeds up
to 66 MHz. The PCI Initiator interface provides DMA, allowing host software to
initialize arbitrary sized read or write bursts between the Total-AceXtreme’s shared
memory and PCI host space.
The device provides a dual redundant MIL-STD-1553 channel with very low power,
less than 1 W maximum dissipation. It includes an IEEE 1149.1 compliant JTAG test
interface to support boundary scan testing of circuit assemblies, a digital IRIG-B
input, and 8 digital discrete I/O lines. The IRIG-B input can be used to create a
common time tag reference for the 1553 messages.
The Total-AceXtreme can be used as a MIL-STD-1553 Bus Controller (BC), single
Remote Terminals (RT), multiple (up to 32) Remote Terminals, a Bus Monitor (MT),
combined BC/Monitor, or combined single RT/Monitor, or Multi-RT/Monitor.
2.1 Features
•Small Integrated BGA with Transformers Inside:
- 324 Ball BGA 16 mm x 16 mm x 4.7 mm (0.63 in. x 0.63 in. x 0.185 in.)
- Protocol, RAM, Transceivers and Transformers in a single package
•Ultra Low Power, under 1 Watt dissipation at 100% duty cycle
•Configurable Host Interface
- 16-bit and 32-bit Options for Parallel CPU Interface
Synchronous and Asynchronous Options
•Asynchronous Access Time 70 ns to read, 40 ns to write
•Synchronous Access Time for first word as low as 125 ns to read,
50 ns to write
•Synchronous Word Bursts at Host Clock Rate, up to 80 MHz

OVERVIEW
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- 32-bit PCI Target/Initiator Interface
Operates at up to 66 MHz
Target single-word reads as low as 125 ns for reads, and 60 ns for
writes
Target Word Bursts at PCI Clock Rate
PCI Initiator with built-in DMA Engine with 264MB/sec Burst Transfer
Rate for reduced host resources.
•1 Dual Redundant MIL-STD-1553 Channel
- BC or Multi-RT with Concurrent Bus Monitor
- Support of MIL-STD-1553 A/B, STANAG-3838, and MIL-STD-1760
- 2 Mb (64K x 36) RAM
- Transmit Inhibit Ball for Monitor-only Applications
- BC Disable Ball for RT-only Applications
- 48-bit/100ns Time Stamp
- IRIG-106 Chapter 10 Monitor
•1553 Bus Controller (BC)
- Highly Autonomous Controller, with 32-Instruction Set
- Streaming and Minor/Major Frame Scheduling of Messages
- High and Low Priority Asynchronous Message Insertion
- Modify Messages or Data while BC is running
•1553 Remote Terminal (RT)
- Emulate up to 31 RT Addresses Simultaneously
- Multiple Buffering Techniques
- Programmable Command Illegalization
- Programmable Busy by Sub-address
- RT Auto-Boot Option for MIL-STD-1760
•1553 Bus Monitor (MT)
- IRIG-106 Chapter 10 Compatibility
- Filter Based on RT Address, T/R bit, Sub-Address
- Advanced Bit Level Error Detection to Isolate Bus Failures
•Advanced Data Handler (ADH)
- For BC, RT, and Multi-RT modes, Option to Combine Control/Status and
Data Structures into Consolidated Structures for each Message.

OVERVIEW
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- Options for Transferring based on transmit and/or received messages.
- Transfer control/status structures and/or data words.
- For RT, can filter based on RT Address/T-R bit/Subaddress.
- Filter on Valid and/or Invalid Messages.
- Host Interrupts Based on Time, Number of Messages, or Number of Words.
- Can work in Conjunction with DMA Controller and PCI Initiator Interface.
•Autonomous Built-In Self-Test
- Host Initiated Protocol & RAM Self-Test
- Automatic Power On Self-Test
- Online Loopback Test
- Capability for Channel A-to-B Wraparound Test
- Capability to Test Transmitter Timeout Function
•Provides JTAG Boundary Scan
•IRIG-B Input
•8 Digital Discrete I/O
•High-Level C Software Development Kits with Drivers for Windows®, Linux®, and
VxWorks®
•Optional Hardware/Software Development Kit with PCI Evaluation Board and
Design Artifacts (see section 2.4)
- PCI Evaluation Board with Cable
- 1 Total-AceXtreme® Component
- BusTrACEr®with Application Code Generation for Software Development
- Drivers for Windows®, Linux®, and VxWorks®
- Thermal Model, IBIS Model and Schematic Symbols
- PCI Card Reference Design Schematic
•Extended Industrial Temperature Range, -40°C to +100°C
•Thermal Balls for Improved Heatsinking
•Leaded and RoHS Versions Available
Total-AceXtreme Architectural Reference Guide. This document, which DDC can
provide under an NDA, includes detailed information about the Total-AceXtreme
architecture. This includes register bit maps and definitions, and detailed information
about the AceXtreme’s data structures and operations for BC, Multi-RT, and Monitor
modes.

OVERVIEW
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Figure 1. BU-67301B Total-AceXtreme®

OVERVIEW
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Figure 2. Total-AceXtreme®Block Diagram

OVERVIEW
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2.2 Specifications
Table 1. Total-AceXtreme®Series Specifications
PARAMETER MIN TYP MAX UNITS
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (Note 11)
Logic +3.3V (VDDIO) -0.3 — 4.0 V
Core +1.8V -0.3 — 2.0 V
PLL +1.8V -0.3 — 2.0 V
• Transceivers +3.3V (during transmit)
• DC Input or Output Logic Voltage -0.3 -0.3 — —
4.5
VDDIO +0.3, or
4.0 (which ever
is less)
V
V
Logic
3.3V Logic Input or Output Range -0.3 — VDDIO +0.3, or
4.0 (which ever
is less)
V
RECEIVER
Differential Input Impedance (Notes 1 – 6)
• +3.3V Transformer Coupled 1.0 KΩ
Input Voltage Range
Threshold Voltage (Transformer Coupled) 0.86 0.200 — 14.0 0.860 VPK-PK VPK-PK
Common Mode Voltage ±10 Vpeak
TRANSMITTER
Differential Output Voltage
Transformer Coupled Across 70
Ω
, Measured on Bus (Note 9)
20 21.5 27 VPK-PK
Output Noise, Differential 14 mVRMS
Output Offset Voltage, Transformer Coupled Across 70 Ω-250 250 mVPK
Rise/Fall Time 100 150 300 ns
LOGIC
VIH
All logic inputs, including HOST_CLK/PCI_CLK and CLK_IN 2.0 VDDIO + 0.3 V
VIL
All logic inputs, including HOST_CLK/PCI_CLK and CLK_IN -0.3 0.8 V
Schmidt Hysteresis
HOST_CLK/PCI_CLK and CLK_IN 0.4 0.7 V

OVERVIEW
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Table 1. Total-AceXtreme®Series Specifications
PARAMETER MIN TYP MAX UNITS
TRANSMITTER (con’t)
IIH, IIL
Signals with Pullups
IIH (VIN = 3.3V) -10 +10 µA
IIL (VIN = 0V) 37 114 µA
Signals with Pulldowns
IIH (VIN = 3.3V) 38 97 µA
IIL (VIN = 0V) -10 +10 µA
Signals without bias
IIH (0 < VIN < VCC) -10 +10 µA
IIL (0 < VIN < VCC) -10 +10 µA
VOH VDDIO – 0.4 V
VOL 0.4 V
PCI_ADx/CPU_DATAx, nINT, IRDY#, REQ#, FRAME#, TRDY#,
DEVSEL#, STOP#, PERR#, PAR, CBEx
IOL 8 mA
IOH -8 mA
JTAG_TDO, CPU_STOP_L, CPU_RDY_L, TXDATA_OUT_x,
TX_INH_OUT_x, USER_OUTPUT_x
IOL 4 mA
IOH -4 mA
CI (Input Capacitance) All signals except for
HOST_CLK/PCI_CLK, CLK_IN, and IDSEL 10 pF
CCLK (HOST_CLK and CLK_IN pin capacitance)
Pin inductance 5 12
20 pF nH
PCI COMPATIBLE LOGIC (see PCI spec 3.3V signaling
environment)
INTA#, nMSTCLR/RST#, GNT#, IDSEL#, SERR#, and
HOST_CLK/PCI_CLK
VIH 0.5* VDDIO VDDIO + 0.3 V
VIL -0.3 0.3* VDDIO V
C
I
(Input Capacitance) all PCI except PCI_CLK/HOST_CLK
& IDSEL
10 pF
CI (Input Capacitance) PCI_CLK/HOST_CLK 5 12 pF
CI (Input Capacitance) IDSEL 8 pF

OVERVIEW
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10
Table 1. Total-AceXtreme®Series Specifications
PARAMETER MIN TYP MAX UNITS
POWER SUPPLY REQUIREMENTS
Voltages/Tolerances
• Logic +3.3V (VDDIO)
• Logic +3.3V (VDDIO) Ramp Rate 3.0
3.3 3.6 1.85 V V/µs
• Core and PLL +1.8V (VCORE and VPLL)
• Core and PLL +1.8V (VCORE and VPLL) Ramp Rate 1.65
1.8 1.95 1.85 V V/µs
• Transceivers +3.3V 3.135 3.3 3.465 V
Current Drain (Total Hybrid) (Note 10)
3.3V (I/O and transceiver) (Note 10):
• Idle — — 40 mA
• 25% Duty Transmitter Cycle — — 214 mA
• 50% Duty Transmitter Cycle — — 344 mA
• 100% Duty Transmitter Cycle
1.8V (logic core) (Note 10) — — — — 624 160 mA mA
POWER DISSIPATION: TOTAL HYBRID (Note 10)
• Idle — — 0.42 W
• 25% Duty Transmitter Cycle — — 0.58 W
• 50% Duty Transmitter Cycle — — 0.70 W
• 100% Duty Transmitter Cycle — — 0.90 W
POWER DISSIPATION: TRANSCEIVER CHIP (Note 10)
• Idle — — 0.09 W
• 25% Duty Transmitter Cycle — — 0.23 W
• 50% Duty Transmitter Cycle — — 0.33 W
• 100% Duty Transmitter Cycle — — 0.50 W
CLOCK INPUTS
PCI CLOCK INPUT FREQUENCY 0 — 66 MHz
HOST_CLK (CPU) CLOCK INPUT FREQUENCY 0 — 80 MHz
CLOCK_IN (MIL-STD-1553) FREQUENCY
• Nominal Value — 40 — MHz
Long Term Tolerance
• 1553A Compliance 0.01 — -0.01 %
• 1553B Compliance 0.10 — -0.10 %
Short Term Tolerance, 1 second
• 1553A Compliance -0.001
—
0.001 %
• 1553B Compliance -0.01
—
0.01 %
Duty Cycle 40
—
60 %
Jitter Tolerance —
—
100 Ps

OVERVIEW
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11
Table 1. Total-AceXtreme®Series Specifications
PARAMETER MIN TYP MAX UNITS
1553 MESSAGE TIMING
BC Intermessage Gap (Note 7) 10 µs
BC/RT/MT No-Response Timeout – mid-parity-to-mid-sync
programmable range (Note 8)
4 511.5 µs
RT Response Time (mid-parity to mid-sync) 4 — 7 µs
Transmitter Watchdog Timeout — 660.5 — µs
THERMAL
TOTAL-ACEXTREME BGA 324-BALL BGA PACKAGE
(See Thermal Management Section)
Active Transceiver
• Junction Temperature (TJ)
• Junction-to-Ambient (θJA via simulation) 150
°C
- Per JESD 51-2 standard at 25°C
θJA in Still Air — 68.8 — °C/W
THERMAL (Con’t)
- Per JESD 51-6 standard at 25°C
θJA @ 1M/S — 52.9 — °C/W
θJA @ 2M/S — 47.1 — °C/W
θJA @ 3M/S — 43.6 — °C/W
• Junction-to-case (θJC via simulation)
- Per JESD 51-12 standard at 25°C
θJC — 24.5 — °C/W
• Junction-to-board (θJB via simulation)
- Per JESD 51-8
θJB — 46.9 — °C/W
ALL PACKAGES
Operating Case Temperature
- EXX -40 — +100 °C
- 1XX (Note 11) -55 — +125 °C
Operating Junction Temperature
- Transceiver -55 — +150 °C
- Protocol -55 — +135 °C
Storage Temperature -65 — +150 °C
SOLDERING
324-BALL BGA PACKAGE
The reflow profile detailed in IPC/JEDEC J-STD-020 is applicable for both the leaded and lead-free versions of Total-
AceXtreme.