Denon DN-X1500 User manual

SERVICE MANUAL
MODEL DN-X1500
DJ MIXER
For U.S.A., Canada, Europe,
Oceania & Asia model
16-11, YUSHIMA 3-CHOME, BUNKYO-KU, TOKYO 113-0034 JAPAN
X-0196V.01 DE/CDM 0401
注 意
サービスをおこなう前に、このサービスマニュアルを
必ずお読みください。本機は、火災、感電、けがなど
に対する安全性を確保するために、さまざまな配慮を
おこなっており、また法的には「電気用品安全法」に
もとづき、所定の許可を得て製造されております。
従ってサービスをおこなう際は、これらの安全性が維
持されるよう、このサービスマニュアルに記載されて
いる注意事項を必ずお守りください。
● 本機の仕様は性能改良のため、予告なく変更すること
があります。
● 補修用性能部品の保有期間は、製造打切後 8年です。
Some illustrations using in this service manual are
slightly different from the actual set.
●
●
Please use this service manual with referring to
the operating instructions without fail.
●
For purposes of improvement, specifications and
design are subject to change without notice.
●
修理の際は､必ず取扱説明書を参照の上、作業を行って,
ください。
● 本文中に使用しているイラストは、説明の都合上現物
と多少異なる場合があります。
Ver. 1

2
2
DN-X1500
SAFETY PRECAUTIONS
Thefollowingcheckshouldbeperformedforthecontinuedprotectionofthecustomerandservicetechnician.
LEAKAGE CURRENT CHECK
Beforereturningtheunittothecustomer,makesureyoumakeeither(1)aleakagecurrentcheckor(2)alinetochassis
resistancecheck.Iftheleakagecurrentexceeds0.5milliamps,oriftheresistancefromchassistoeithersideofthe
powercordislessthan460kohms,theunitisdefective.
LASER RADIATION
Donotstareintobeamorviewdirectlywithopticalinstruments,class3Alaserproduct.
(1)
(2)
500V
1M
(1)
(2)

3
3
DN-X1500
DISASSEMBLY
(Follow the procedure below in reverse order when reassembling.)
1. Top Panel Unit
(1)Remove 9 screws and pull up Top Panel Unit.
(2)Disconnect FFC cable and Connector.
(3)Detach Top Panel Unit.
Note: ●Do not pull out aslsnt to prevent FFC cable damage.
●Do not fail to pull AC cord from wall outlet before
disconnect the FFC cable.
if AC cord is remained plugged into wall outlet,
power is kept supplied in the unit, which may cause
danger.
2. Cross Feder Unit
(1)Remove 2 screws and pull up Cross Feder Unit.
(2)Disconnect Connector.
Top Panel Unit
Cross Feder Unit
Connector
Label face

4
4
DN-X1500
3. CH Fader Unit
(1)Remove 4 knobs.
(2)Remove 4 screws and pull up CH Fader Panel.
(3)Remove 2 screws for each CH.
(4)Disconnect Connector.
(5)Detach CH Fader Unit.
4. Front Panel
(1)Pull out the knobs.
(2)Remove 8 screws.
(3)Pull up Front Panel.
5'0514.'8'4
Front Panel

5
5
DN-X1500
SERVICE MODE SPECIFICATION
*How the product performs when the operation buttons for μcom control are pressed (including control input) is described in
the table below.
1. POWER ON
2. CH GAIN VR
3. MASTER LEVEL VR
4. (SAMPLER) CROSSFADER ASSIGN switch
Function Description Display Remarks
POWER (1)Turns power ON/OFF.
Service
Mode
(2)Switches power ON when OFF.
①Enters in the service mode when power on
while pressing MIC POST ON/OFF button and
E F F E C T L O O P O N / O F F b u t t o n .
②For canceling the service mode, turn power off/on.
①Displays Service.①Refer to CH GAIN VR.
②Refer to MASTER LEVEL VR.
③Refer to SAMPER ASSIGN.
④Refer to CROSSFADER ASSIGN.
Function Description Display Remarks
CH LEVEL
METER
(1) When you turn this VR, LED of CH level meter
is lit.
①VR position is 0 : LED is not lit.
②VR position is 10 : All LED is lit.
Function Description Display Remarks
MASTER
LEVEL
METER
(1) When you turn this VR, LED of master level
meter is lit.
①VR position is 0 : LED is not lit.
②VR position is 10 : All LED is lit.
Function Description Display Remarks
FL mode
(1) You can select FL display mode. ①A : FL tube is not lit.
②B : All FL tube is lit.
③POST : Displays VR checking or
LED checking.

6
6
DN-X1500
5. SAMPLER ASSIGN switch
6. μCOM VERSION CHECK
You can check the μcom version at "Preset Functions".
Please refer to the Instructions Manual.
Function Description Display Remarks
FADER VR
CHECK
(1)When CROSSFADER ASSIGN switch is set
to POST, you can check the fader VR and LED.
①Refer to CROSSFAER ASSGIN.
OFF (1)When selected OFF, it becomes the LED off
modde.
①Displays LED OFF.
CH1
(1)When selected CH1, it becomes the mode of
reading/displaying CH1 fader VR value.
①Displays 0〜100.
②Fader position is 0 : 0
③Fader position is 10 :100
CH2
(1)When selected CH2, it becomes the mode of
reading/displaying CH2 fader VR value.
①Displays 0〜100.
②Fader position is 0 : 0
③Fader position is 10 : 100
CH3
(1)When selected CH3, it becomes the mode of
reading/displaying CH3 fader VR value.
①Displays 0〜100.
②Fader position is 0 : 0
③Fader position is 10 : 100
CH4
(1)When selected CH4, it becomes the mode of
reading/displaying CH4 fader VR value.
①Displays 0〜100.
②Fader position is 0 :0
③Fader position is 10 : 100
MAIN
MIC
(1)When selected MAIN MIC, it becomes the
LED on mode.
①Displays LED ON.
MASTER
(1)When selected MASTER, it becomes the
mode of reading/displaying crossfader VR value.
①Displays 0〜100.
②Fader position is Left side : 0
③Fader position is Right side : 100

7
7
DN-X1500
SEMICONDUCTORS
Only major semiconductors are shown, general semiconductors etc. are omitted to list.
●IC's
Note: Abbreviation ahead of IC No. indicates the name of P.W.B., etc.
MN102H74D (IC101)
MN102H74D Terminal Function
75
76
100
125
26
50
51
No. Pin Name Symbol I/O DET
Int
PU Ext Res Ini Function
1 P50,WAIT _WAIT I - - Pu H - HI R/W timing wait signal
2 P51,_RE _RD O - - Pu H - Read signal
3 P52,_WEL _WEL O - - Pu H - Write signal
4 P53,_WEH _DSP_REQ O - ON - Hi-z H System <-> DSP REQ signal
5 P60,_CS0 _CS0 O - - Pu H - Chip select signal 1st address of Flash ROM:
6 P61,_CS1 _CS_DSP O - - Pu H - Chip select of expansion port
7 P62,_CS2 _HBR O - - Pu H - DSP select signal Host Interface
8 P63,_CS3 _DSP_ACK I - ON - Hi-z - System <-> DSP ACK signal
9 P64,TM0IO,_BREQ _BREQ I - - Pu H -
Panel ucom control: When DSP boot, system bus
open. 'L': open
10 P65,TM1IO,_BRACK _BRACK O - Pu H - When bus open, 'L' output.
11 P66,_WR _DAC_RST O - ON - H H Reset of ADC, DAC, and DIT
12 _WORD _WORD I - - L L - Select width of data bit bus 'L': 16bit
13 P20,A00 A00 A/O - ON - Hi-z - Address bus
14 P21,A01 A01 A/O - ON - Hi-z - Address bus
15 P22,A02 A02 A/O - ON - Hi-z - Address bus
16 P23,A03 A03 A/O - ON - Hi-z - Address bus
17 Vdd Vdd - - - - - - Power supply(+3.3V)
18 P54,BOSC,SYSCLK RESERVE1 O - ON - L H Signal for test
19 Vss Vss - - - - - - GND(0V)
20 XI XI - - - - - - Not used
21 XO XO - - - - - - Not used
22 Vdd Vdd - - - - - - Power supply(+3.3V)
23 OSCI OSCI I - - - - - This Need 12MHz for USB communication
24 OSCO OSCO O - - - - - Output OSCI
25 MODE MODE I - - H H -
Mode set
'H': Memory expansion/single chip mode
26 P24,A04 A04 A/O - ON - Hi-z - Address bus
27 P25,A05 A05 A/O - ON - Hi-z - Address bus
28 P26,A06 A06 A/O - ON - Hi-z - Address bus
29 P27,A07 A07 A/O - ON - Hi-z - Address bus
30 P30,A08 A08 A/O - ON - Hi-z - Address bus
31 P31,A09 A09 A/O - ON - Hi-z - Address bus
32 P32,A10 A10 A/O - ON - Hi-z - Address bus
33 P33,A11 A11 A/O - ON - Hi-z - Address bus
34 Vdd Vdd - - - - - - Power supply(+3.3V)
35 P34,A12 A12 A/O - ON - Hi-z - Address bus
36 P35,A13 A13 A/O - ON - Hi-z - Address bus
37 P36,A14 A14 A/O - ON - Hi-z - Address bus
38 P37,A15 A15 A/O - ON - Hi-z - Address bus
※Internal Pull Up is 10〜90 ( KΩ), Ave : 30 ( KΩ)

8
8
DN-X1500
No. Pin Name Symbol I/O DET
Int
PU Ext Res Ini Function
39 P40,A16 A16 A/O - ON - Hi-z - Address bus
40 P41,A17 A17 A/O - ON - Hi-z - Address bus
41 P42,A18 A18 A/O - ON - Hi-z - Address bus
42 P43,(TM2IO),A19 A19 A/O - - Pu H -
Address bus
Need pull up to extension for DSP boot control
43 Vss Vss - - - - - - GND(0V)
44 P44,(TM3IO),A20 _CDDEC_L
C
O - ON - Hi-z H Latch to codec1 'L': available
45 P45,(TM4IO),A21 _CDDEC_L
C
O - ON - Hi-z H Latch to codec2 'L': available
46 P46,(TM5IO),A22 _DAC_CS O - ON - Hi-z H DAC chip select 'L': available
47 P47,_CS0S,(TM6IO),A23 _DIT_CS O - - Pd L H
DIT chip select
'L': available (be pull down in DSP)
48 P70,_CS1S,(TM7IO),SBI3 DIT_DIN I - ON - Hi-z H DIT data input
49 P71,_CS2S,(TM8IO),SBO3 CLOCK_A O - - Pd L L
CODEC(AD1838A)/DAC(PCM1791A)/DIT(AK4103)
data output clock signal
50 P72,_CS3S,(TM9IO),SBT3 DATA_A O - ON - Hi-z L
CODEC(AD1838A)/DAC(PCM1791A)/DIT(AK4103)
data signal
51 P80,TM10IOA,WDOUT PLGIN_L I - - Pu H H
Lch SEND/RETURN connection status
'H': connect
52 P81,TM10IOB,STOP PLGIN_R I - - Pu H H
Rch SEND/RETURN connection status
'H': connect
53 USBMODE USBMODE - - - - - - USB mode selectable terminal, connect to GND
54 Vdd Vdd - - - - - - Power supply(+3.3V)
55 D+ D+ - - - Pu - -
Connect USB terminal D+. 24
Ω
resistance is
connected in series.
56 D- D- - - - - - -
Connect USB terminal D-. 24
Ω
resistance is
connected in series.
57 Vss Vss - - - - - - GND(0V)
58 P82,SBI2 RxD I - - Pu H - 75000bps Need to convert level
59 P83,SBO2,TM11IOA TxD O - - Pu H H 75000bps Need to convert level
60 P84,SBT2,TM11IOB _MONO I - ON - Hi-z - MONO/STEREO SW 'L': MONO
61 Vss Vss - - - - - - GND(0V)
62 P90,AN0,TM12IOA ATT I Ad - - - - Adjust VR for Master output (BAL/UNBAL)
63 P91,AN1,TM12IOB _STB_CLR O - - Pd L L
TC94A32/TC9162 ALL STB set to L
'L': L set , CODEC reset
64 P92,AN2,TM13IOA CLOCK_B O - - Pd L L
Electric VR(TC94A32)/SelectorTC9162 data output
clock signal
65 P93,AN3,TM13IOB DATA_B O - ON - Hi-z L Electric VR(TC94A32)/SelectorTC9162 data signal
66 Vdd Vdd - - - - - - Power supply(+3.3V)
67 PA0,SBI1,AN4 _FPLAY1 O - - Pu H H Ch1 Fader PLAY output 20msec 'L' pulse
68 PA1,SBO1,AN5,SDA1 _FCUE1 O - - Pu H H Ch1 Fader CUE output 20msec 'L' pulse
69 PA2,SBT1,AN6,SCL1 _FPLAY2 O - - Pu H H Ch2 Fader PLAY output 20msec 'L' pulse
70 PA3,SBI0,AN7 _FCUE2 O - - Pu H H Ch2 Fader CUE output 20msec 'L' pulse
71 PA4,SBO0,SDA0 _FPLAY3 O - - Pu H H Ch3 Fader PLAY output 20msec 'L' pulse
72 PA5,SBT0,SCL0 _FCUE3 O - - Pu H H Ch3 Fader CUE output 20msec 'L' pulse
73 TEST1 SBD4 I - - Pu - -
Pull up 4.7kΩ〜10kΩConnection output for
onboard write of internal form.
74 TEST2 SBT4 I - - Pu - -
Pull up 4.7kΩ〜10kΩConnection output for
onboard write of internal form.
75 _NMI _NMI I Lv - - H H
76 PB0,_IRQ0 _DSP_BPM I Ed ON - - Trigger terminal for BPM counter by DSP
77 PB1,_IRQ1 DSP_COM O - - Pu H - System <-> DSP REQ2 signal
78 PB2,_IRQ2 RESERVE4 I - - Pu H - Signal for test
79 PB3,_IRQ3 MUTE O - - Pu H H Analog/Digital mute 'H': Mute ON
80 PB4,_IRQ4 _FPLAY4 O - - Pu H H Ch4 Fader PLAY output 20msec 'L' pulse
81 PB5,_IRQ5 _FCUE4 O - - Pu H H Ch4 Fader CUE output 20msec 'L' pulse
82 _RST _RESET I Lv - - L - Reset signal 'L': Reset
83 Vdd Vdd - - - - - - Power supply(+3.3V)
84 P00,D00 D00 D/O - ON - Hi-Z - Data bus
85 P01,D01 D01 D/O - ON - Hi-Z - Data bus
86 P02,D02 D02 D/O - ON - Hi-Z - Data bus
87 P03,D03 D03 D/O - ON - Hi-Z - Data bus
88 P04,D04 D04 D/O - ON - Hi-Z - Data bus
89 P05,D05 D05 D/O - ON - Hi-Z - Data bus
90 P06,D06 D06 D/O - ON - Hi-Z - Data bus
91 P07,D07 D07 D/O - ON - Hi-Z - Data bus
92 Vss Vss - - - - - - GND(0V)
93 P010,D08,(TM2IO) D08 D/O - ON - Hi-Z - Data bus
94 P011,D09,(TM3IO) D09 D/O - ON - Hi-Z - Data bus
95 P012,D10,(TM4IO) D10 D/O - ON - Hi-Z - Data bus
96 P013,D11,(TM5IO) D11 D/O - ON - Hi-Z - Data bus
97 P014,D12,(TM6IO) D12 D/O - ON - Hi-Z - Data bus
98 P015,D13,(TM7IO) D13 D/O - ON - Hi-Z - Data bus
99 P016,D14,(TM8IO) D14 D/O - ON - Hi-Z - Data bus
100 P017,D15,(TM9IO) D15 D/O - ON - Hi-Z - Data bus

9
9
DN-X1500
TMP86CM47U (IC301)
TMP86CM47U Terminal Function
111
12
22
23
33
34
44
TOP VIEW
Pin No. Pin Name Symbol I/O DET Ext Res Ini Function
1VSS VSS -----
GND (0V)
2XIN XIN -----
Oscillation input 16MHz
3XOUT XOUT -----
Oscillation output
4TEST TEST -----
Fixed to GND
5VDD VDD -----
Power (+5.0V)
6P21 ADR1 O-Pu-H
Address decode signal 1
7P22 ADR2 O-Pu-H
Address decode signal 2
8RESET_ RESET_ -----
Reset input
9P20 DSPBSY I-PuH-
Boot flag (L: during boot)
10 P00 ADR3 O-Pu-H
Address decode signal 3
11 P01 ADR4 O-Pu-H
Address decode signal 4
12 RXD RXD I--H-
Serial receive signal
13 TXD TXD O-PuHH
Serial send signal
14 SO FLSD O-PuHH
M66005AFP-SDATA
15 P05 FLCS O-PuHH
M66005AFP-CA
16 SCK FLCLK O-PuHH
M66005AFP-CLK
17 P07 TEST1 O- --H
Not used
18 P17 FLRST O-PdLL
M66005AFP reset signal (L: Reset)
19 P16 DRST O-PdLL
DSP reset (L: Reset)
20 P15 BREQ O-PuHH
System ucom stop signal
21 P14 LDLCH O-PuHH
LED driver latch signal
22 P13 LDCLK O-Pu-H
Clock for LED driver data sending
23 P12 LDDAT1 O-Pd-L
LED driver data 1
24 P11 LDDAT2 O-Pd-L
LED driver data 2
25 P10 LDDAT3 O- LLL
LED driver data 3
26 AIN0 KEYIN0 I----
Key input 0 (Volume)
27 AIN1 KEYIN1 I----
Key input 1 (Volume)
28 AIN2 KEYIN2 I----
Key input 2 (Volume)
29 AIN3 KEYIN3 I----
Key input 3 (Volume)
30 AIN4 KEYIN4 I----
Key input 4 (Volume)
31 AIN5 KEYIN5 I----
Key input 5 (Volume)
32 AIN6 KEYIN6 I----
Key input 6 (Volume)
33 AIN7 KEYIN7 I----
Key input 7 (Volume)
34 VAREF VARFF -----
Power (+5.0V), Analog ref.V for A/D conversion
35 AVDD AVDD -----
Power (+5.0V)
36 AVSS AVSS -----
GND (0V), Analog GND for A/D conversion
37 P40 KEYIN8 I-Pu-H
Key input 8 (Key matrix)
38 P41 KEYIN9 I-Pu-H
Key input 9 (Key matrix)
39 P42 KEYIN10 I-Pu-H
Key input 10 (Key matrix)
40 P43 KEYIN11 I-Pu-H
Key input 11 (Key matrix)
41 P44 KEYIN12 I-Pu-H
Key input 12 (Key matrix)
42 P45 KEYIN13 I-Pu-H
Key input 13 (Key matrix)
43 P46 KEYIN14 I-Pu-H
Key input 14 (Key matrix)
44 P47 KEYIN15 I-Pu-H
Key input 15 (Key matrix)

10
10
DN-X1500
ADSST-MEL100 (DSP:IC101)
ADSST-MEL100 Terminal Function
TOP VIEW
BOTTOM VIEW
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
B
C
D
E
F
G
H
J
K
L
M
N
P
R
Pin Name Pin Name Pin Name Pin Name Pin Name
A1
NC B1 TRST_ C1 TMS D1 TD0 E1 FLAG10
A2
BMSTR B2 TDI C2 EMU_ D2 TCK E2 RESET_
A3
BMS_ B3 RPBA C3 GND D3 FLAG11 E3 FLAG8
A4
SPIDS_ B4 MOSI C4 SPICLK D4 MISO E4 D0A
A5
EBOOT B5 FS0 C5 D0B D5 SCLK0 E5 VDDEXT
A6
LBOOT B6 SCLK1 C6 D1A D6 D1B E6 VDDINT
A7
SCLK2 B7 D2B C7 D2A D7 FS1 E7 VDDEXT
A8
D3B B8 D3A C8 FS2 D8 VDDINT E8 VDDINT
A9
L0DAT[4] B9 L0DAT[7] C9 FS3 D9 SCLK3 E9 VDDEXT
A10
L0ACK B10 L0CLK C10 L0DAT[6] D10 L0DAT[5] E10 VDDINT
A11
L0DAT[2] B11 L0DAT[1] C11 L1DAT[7] D11 L0DAT[3] E11 VDDEXT
A12
L1DAT[6] B12 L1DAT[4] C12 L1DAT[3] D12 L1DAT[5] E12 L0DAT[0]
A13
L1CLK B13 L1ACK C13 L1DAT[1] D13 DATA[42] E13 DATA[39]
A14
L1DAT[2] B14 L1DAT[0] C14 DATA[45] D14 DATA[46] E14 DATA[43]
A15
NC B15 RSTOUT_ C15 DATA[47] D15 DATA[44] E15 DATA[41]
Pin Name Pin Name Pin Name Pin Name Pin Name
F1
FLAG5 G1 FLAG1 H1 FLAG0 J1 IRQ2_ K1 TIMEXP
F2
FLAG7 G2 FLAG2 H2 IRQ0_ J2 ID1 K2 ADDR[22]
F3
FLAG9 G3 FLAG4 H3 VDDINT J3 ID2 K3 ADDR[20]
F4
FLAG6 G4 FLAG3 H4 IRQ1_ J4 ID0 K4 ADDR[23]
F5
VDDINT G5 VDDEXT H5 VDDINT J5 VDDEXT K5 VDDINT
F6
GND G6 GND H6 GND J6 GND K6 GND
F7
GND G7 GND H7 GND J7 GND K7 GND
F8
GND G8 GND H8 GND J8 GND K8 GND
F9
GND G9 GND H9 GND J9 GND K9 GND
F10
GND G10 GND H10 GND J10 GND K10 GND
F11
VDDINT G11 VDDEXT H11 VDDINT J11 VDDEXT K11 VDDINT
F12
DATA[37] G12 DATA[34] H12 DATA[29] J12 DATA[26] K12 DATA[22]
F13
DATA[40] G13 DATA[35] H13 DATA[28] J13 DATA[24] K13 DATA[19]
F14
DATA[38] G14 DATA[33] H14 DATA[30] J14 DATA[25] K14 DATA[21]
F15
DATA[36] G15 DATA[32] H15 DATA[31] J15 DATA[27] K15 DATA[23]
Pin Name Pin Name Pin Name Pin Name Pin Name
L1
ADDR[19] M1 ADDR[16] N1 ADDR[14] P1 ADDR[13] R1 NC
L2
ADDR[17] M2 ADDR[12] N2 ADDR[15] P2 ADDR[9] R2 ADDR[11]
L3
ADDR[21] M3 ADDR[18] N3 ADDR[10] P3 ADDR[8] R3 ADDR[7]
L4
ADDR[2] M4 ADDR[6] N4 ADDR[5] P4 ADDR[4] R4 ADDR[3]
L5
VDDEXT M5 ADDR[0] N5 ADDR[1] P5 MS2 R5 MS3
L6
VDDINT M6 MS1 N6 MS0 P6 SBTS_ R6 PA
L7
VDDEXT M7 BR6 N7 BR5 P7 BR4 R7 BR3
L8
VDDINT M8 VDDEXT N8 BR2 P8 BR1 R8 RD
L9
VDDEXT M9 WR N9 BRST P9 SDCLK1 R9 CLKOUT
L10
VDDINT M10 SDA10 N10 SDCKE P10 SDCLK0 R10 HBR
L11
VDDEXT M11 RAS_ N11 CS_ P11 REDY R11 HBG
L12
CAS_ M12 ACK N12 CLK_CFG1 P12 CLKIN R12 CLKDBL
L13
DATA[20] M13 DATA[17] N13 CLK_CFG0 P13 DQM R13 XTAL
L14
DATA[16] M14 DMAG2 N14 AVDD P14 AVSS R14 SDWE_
L15
DATA[18] M15 DMAG1 N15 DMAR1 P15 DMAR2 R15 NC
No.
No. No. No. No. No.
No. No. No. No.
No. No. No.No. No.

11
11
DN-X1500
128M-SDRAM (DSP:IC102)
Block Diagram
Note: The # symbol indicates signal is active LOW.
V DD
DQ0
V
DD Q
DQ1
DQ2
V
SS Q
DQ3
DQ4
V
DD Q
DQ5
DQ6
V
SS Q
DQ7
NC
V
DD
DQM0
WE#
CAS#
RAS#
CS#
A11
BA0
BA1
A10
A0
A1
A2
DQM2
V
DD
NC
DQ16
V
SS Q
DQ17
DQ18
V
DD Q
DQ19
DQ20
V
SS Q
DQ21
DQ22
V
DD Q
DQ23
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
V SS
DQ15
V
SS Q
DQ14
DQ13
V
DD Q
DQ12
DQ11
V
SS Q
DQ10
DQ9
V
DD Q
DQ8
NC
V
SS
DQM1
NC
NC
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
DQM3
V
SS
NC
DQ31
V
DD Q
DQ30
DQ29
V
SS Q
DQ28
DQ27
V
DD Q
DQ26
DQ25
V
SS Q
DQ24
V
SS
12
RAS#
CAS#
CLK
CS#
WE#
CKE
8
A0–A11,
BA0, BA1
DQM0–
DQM3
14
256
(x32)
8192
I/O GATING
DQM MASK LOGIC
READ DATA LATCH
WRITE DRIVERS
COLUMN
DECODER
BANK0
MEMORY
ARRAY
(4,096 x 256 x 32)
BANK0
ROW-
ADDRESS
LATCH
&
DECODER
4096
SENSE AMPLIFIERS
BANK
CONTROL
LOGIC
DQ0–
DQ31
32
32
DATA
INPUT
REGISTER
DATA
OUTPUT
REGISTER
32
BANK1
BANK0
BANK2
BANK3
12
8
2
4
4
2
REFRESH
COUNTER
12
12
MODE REGISTER
CONTROL
LOGIC
COMMAND
DECODE
ROW-
ADDRESS
MUX
ADDRESS
REGISTER
COLUMN-
ADDRESS
COUNTER/
LATCH

12
12
DN-X1500
128M-SDRAM Terminal Function
Pin NO. Symbol Type Description
68 CLK I Clock
67 CKE I Clock Enable
20 CS# I Chip Select
17, 18, 19 WE#, CAS#, RAS# I Command Inputs
16, 71, 28, 59 DQM0-DQM3 I Input/Outout Mask
22, 23 BA0, BA1 I Bank Address Input(s)
21, 24-27, 60-66 A0-A11 I Address Inputs
2, 4, 5, 7, 8, 10, 11, 13, 31, 33, 34, 36, 37, 39,
40, 42, 45, 47, 48, 50, 51, 53, 54, 56, 74, 76,
77, 79, 80, 82, 83, 85
DQ0-DQ31 I/O Data I/Os
14, 30, 57, 69, 70, 73 NC - No Connect
3, 9, 35, 41, 49, 55, 75, 81 VDDQ Supply DQ Power Supply
6, 12, 32, 38, 46, 52, 78, 84 VSSQ Supply DQ Ground
1, 15, 29, 43 VDD Supply Power Supply: +3.3V ±0.3V
44, 58, 72, 86 VSS Supply Ground

13
13
DN-X1500
AD1838A (IC401,501)
1
2
3
4
5
6
7
8
9
10
11
12
13
AGND
AVDD
OUTRP2
OUTRN2
OUTLP2
OUTLN2
OUTRP1
OUTRN1
OUTLP1
OUTLN1
PD/RST
CIN
CLATCH
DVDD
OUTLN3
OUTLP3 DGND
52 51 50 49 48 47 46 45 44 43 42 41 40
FILTD FILTR
AGND
DAUXDATA
AGND
AVDD
ADCLN
ADCLP
ADCRN
ADCRP
AGND
DGND CCLK COUT ASDATA ODVDD MCLK ALRCLK ABCLK AAUXDATA3 DSDATA3 DSDATA2 DSDATA1
AD1838A
TOP VIEW
(Not to Scale
)
OUTRN3
OUTRP3
N/C
N/C
N/C
AGND
AGND
DLRCLK
DBCLK
27
28
29
30
31
32
33
34
35
36
37
38
39
M/S
DVDD
AVDD
14 15 16 17 18 19 20 21 22 23 24 25 26
PIN FUNCTION DESCRIPTIONS
Input/
Pin No. Mnemonic Output Description
1, 39 DVDD Digital Power Supply. Connect to digital 5 V supply.
2 CLATCH I Latch Input for Control Data.
3 CIN I Serial Control Input.
4PD/RST I Power-Down/Reset.
5, 10, 16, 24, 30, 34 AGND Analog Ground.
6, 12, 25 OUTLNx O DACx Left Channel Negative Output.
7, 13, 26 OUTLPx O DACx Left Channel Positive Output.
8, 14, 27 OUTRNx O DACx Right Channel Negative Output.
9, 15, 28 OUTRPx O DACx Right Channel Positive Output.
11, 19, 29 AVDD Analog Power Supply. Connect to analog 5 V supply.
17 FILTD Filter Capacitor Connection. Recommended 10 µF/100 nF.
18 FILTR Reference Filter Capacitor Connection. Recommended 10 µF/100 nF.
20 ADCLN I ADC Left Channel Negative Input.
21 ADCLP I ADC Left Channel Positive Input.
22 ADCRN I ADC Right Channel Negative Input.
23 ADCRP I ADC Right Channel Positive Input.
31–33 N/C Not Connected.
35 M/S I ADC Master/Slave Select.
36 DAUXDATA O Auxiliary DAC Output Data.
37 DLRCLK I/O DAC LR Clock.
38 DBCLK I/O DAC Bit Clock.
40, 52 DGND Digital Ground.
41–43 DSDATAx I DACx Input Data (Left and Right Channels).
44 AAUXDATA3 I Auxiliary ADC3 Digital Input.
45 ABCLK I/O ADC Bit Clock.
46 ALRCLK I/O ADC LR Clock.
47 MCLK I Master Clock Input.
48 ODVDD Digital Output Driver Power Supply.
49 ASDATA O ADC Serial Data Output.
50 COUT O Output for Control Data.
51 CCLK I Control Clock Input for Control Data.
FUNCTIONAL BLOCK DIAGRAM
ADCLP
ADCLN
ADCRP
ADCRN
DLRCLK
DBCLK
DSDATA1
DSDATA2
DSDATA3
DAUXDATA
AAUXDATA3
OUTLP1
OUTLN1
CONTROL PORT CLOCK
FILTD
FILTR
MCLKASDATAABCLKALRCLKODVDDDVDD AVDD
AVDD
DVDD
AGND AGNDAGNDAGNDDGNDDGND
CINCLATCHCCLK COUT
DIGITAL
FILTER
PD/RST M/S
⌺−∆
∆
ADC
VOLUME
SERIAL DATA
I/O PORT DIGITAL
FILTER
⌺-⌬
DAC
VREF
OUTRP1
OUTRN1
VOLUME
OUTLP2
OUTLN2
VOLUME DIGITAL
FILTER
⌺-⌬
DAC OUTRP2
OUTRN2
VOLUME
OUTLP3
OUTLN3
VOLUME DIGITAL
FILTER
⌺-⌬
DAC OUTRP3
OUTRN3
VOLUME
DIGITAL
FILTER
⌺−∆
∆
ADC
AD1838A

14
14
DN-X1500
AK4103A (IC502)
Block Diagram
AK4103A PIN/FUNCTION
6
5
4
3
2
1V1
TRANS
MCLK
PDN
SDTI
BICK
LRCK 7
FS0/CSN 8
U1
DIF2
DIF1
DIF0
TXP
TXN
VSS
VDD
Top
View
10
9FS1/CDTI
FS2/CCLK
FS3/CDTO 11
C1 12
CKS1
CKS0
BLS
ANS
19
20
21
22
23
24
18
17
15
16
14
13
Host Serial
Interface
Audio Serial
Interface
BICK
LRCK
SDTI
TXP
MUX
CRCC Generator
Prescaler
RS422 Line Driver
Biphase
Encoder
DIF2 DIF1 DIF0 CKS1 CKS0 MCLK BLS TRANS VSS VDD
TXN
C1
U1
V1
FS0
FS1
FS2
FS3
Register
CSN
CCL
K
CDT
I
CDT
O
ANS
PDN
No. Pin Name I/O Description
1 V1 I Validity Bit Input Pin
2 TRANS I Audio Routing Mode (Transparent Mode) Pin at Synchronous mode
0: Normal mode, 1: Audio routing mode (transparent mode)
3 PDN I Power Down & Reset Pin (Pull-up Pin)
When “L”, the AK4103A is powered-down, TXP/N pins are “L” and the
control registers are reset to default values.
4 MCLK I Master Clock Input Pin
5 SDTI I Audio Serial Data Input Pin
6 BICK I/O Audio Serial Data Clock Input/Output Pin
Serial Clock for SDTI pin which can be configured as an output based on
the DIF2-0 inputs.
7 LRCK I/O Input/Output Channel Clock Pin
Indicates left or right channel, and can be configured as an output based on
the DIF2-0 inputs.
FS0 I Sampling Frequency Select 0 Pin at Synchronous mode (Pull-down Pin)
CSN I Host Interface Chip Select Pin at Asynchronous mode (Pull-down Pin)
8
AKMODE I AK4112B Mode Pin at Audio routing mode (Pull-down Pin)
0: Non-AKM receivers mode, 1: AK4112B mode
FS1 I Sampling Frequency Select 1 Pin at Synchronous mode (Pull-down Pin)9
CDTI I Host Interface Data Input Pin at Asynchronous mode (Pull-down Pin)
FS2 I Sampling Frequency Select 2 Pin at Synchronous mode (Pull-down Pin)10
CCLK I Host Interface Bit Clock Input Pin at Asynchronous mode (Pull-down Pin)
FS3 I Sampling Frequency Select 3 Pin at Synchronous mode (Pull-down Pin)11
CDTO O Host Interface Data Output Pin at Asynchronous mode (Pull-down Pin)
12 C1 I Channel Status Bit Input Pin
13 ANS I Asynchronous/Synchronous Mode Select Pin (Pull-up Pin)
0: Asynchronous mode, 1: Synchronous mode
14 BLS I/O Block Start Input/Output Pin (Pull-down Pin)
In normal mode, the channel status block output is “H” for the first four
bytes. In audio routing mode, the pin is configured as an input. When PDN
pin = “L”, BLS pin goes “H” at Normal mode.
15 CKS0 I Clock Mode Select 0 Pin (Pull-up Pin)
16 CKS1 I Clock Mode Select 1 Pin (Pull-down Pin)
17 VDD - Power Supply Pin, 4.75V∼5.25V
18 VSS - Ground Pin, 0V
19 TXN O Negative Differential Output Pin
20 TXP O Positive Differential Output Pin
21 DIF0 I Audio Serial Interface Select 0 Pin (Pull-down Pin)
22 DIF1 I Audio Serial Interface Select 1 Pin (Pull-down Pin)
23 DIF2 I Audio Serial Interface Select 2 Pin (Pull-down Pin)
24 U1 I User Data Bit Input Pin for Channel 1 (Pull-down Pin)
Notes:
1. Internal pull-up and pull-down resistors are connected on-chip. The value of the resistors is 43kΩ(typ).
2. All input pins except internal pull-down/pull-up pins should not be left floating.

15
15
DN-X1500
PCM1791A (IC402)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
LRCK
BCK
DATA
MUTE
SCK
RST
VDD
DGND
AGNDF
VCCR
AGNDR
VOUTR–
VOUTR+
VCOM
MS
MC
MDI
MDO
MSEL
ZEROL
ZEROR
VCCF
VCCL
AGNDL
VOUTL–
VOUTL+
AGNDC
VCCC
(TOP VIEW)
FUNCTIONAL BLOCK DIAGRAM
Power Supply
RST
SCK
Advanced
Segment
DAC
Modulator
VOUTL+
VOUTL–
Bias
and
Vref
VCCF
VDD
AGNDR
VCCR
AGNDL AGNDF
D/S and Filter
8
Oversampling
Digital
Filter
and
Function
Control
Audio
Data Input
I/F
LRCK
BCK
DATA
MDO
MDI
MC
MS
AGNDC
VCCC
DGND
Current
Segment
DAC
and
I/V Buffer
VCOM
Function
Control
I/F
Zero
Detect
ZEROL
ZEROR
System
Clock
Manager
MSEL
MUTE
VCCL
VOUTR–
VOUTR+
D/S and Filter
Current
Segment
DAC
and
I/V Buffer
Terminal Functions
TERMINAL
I/O
DESCRIPTIONS
NAME PIN I/O DESCRIPTIONS
AGNDC 16 –Analog ground (internal bias and current DAC)
AGNDF 9 – Analog ground (DACFF)
AGNDL 19 –Analog ground (L-channel I/V)
AGNDR 11 –Analog ground (R-channel I/V)
BCK 2 I Bit clock input. Connected to GND for DSD mode (1)
DATA 3 I Serial audio data input for normal operation. L-channel audio data input for external DF and DSD
modes (1)
DGND 8 – Digitalground
LRCK 1 I Left and right clock (fS) input for normal operation. WDCK clock input in external DF mode.
R-channel audio data for DSD mode (1)
MC 27 IShift clock for function control register (1)
MDI 26 I/O Serial data input for function control register (2)
MDO 25 OSerial data output for function control register (3)
MS 28 I/O Mode control chip select and latch signal (4)
MSEL 24 I I2C/SPI select (1)
MUTE 4 I Analog output mute control for normal operation. R-channel audio data input for external DF mode (1)
RST 6 I Reset (1)
SCK 5 I System clock input. BCK (64 fS) clock input for DSD mode (1)
VCCC15 –Analog power supply (internal bias and current DAC), 5 V
VCCF21 –Analog power supply (DACFF), 5 V
VCCL20 –Analog power supply (L-channel I/V), 5 V
VCCR10 –Analog power supply (R-channel I/V), 5 V
VCOM 14 –Internal bias decoupling pin
VDD 7 – Digital power supply, 3.3 V
VOUTL+ 17 OL-channel analog voltage output +
VOUTL– 18 OL-channel analog voltage output –
VOUTR+ 13 OR-channel analog voltage output +
VOUTR– 12 OR-channel analog voltage output –
ZEROL 23 OZero flag for L-channel
ZEROR 22 OZero flag for R-channel
(1) Schmitt-trigger input, 5-V tolerant
(2) Schmitt-trigger input and output. 5-V tolerant input. In I2C mode, this pin becomes an open-drain 3-state output; otherwise, this pin is a CMOS
output.
(3) 3-state output
(4) Schmitt-trigger input and output. 5-V tolerant input and CMOS output

16
16
DN-X1500
PCM1804 (IC301,305,309,313)
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VREFL
AGNDL
VCOML
VINL+
VINL-
FMT0
FMT1
S/M
OSR0
OSR1
OSR2
BYPAS
DGND
VDD
VREFR
AGNDR
VCOMR
VINR+
VINR-
AGND
VCC
OVFL
OVFR
RST
SCKI
LRCK/DSDBCK
BCK/DSDL
DATA/DSDR
TOP VIEW
SN74LV244APW (IC709,DSP:IC106)
1
2
3
4
5
6
7
8
20
19
18
17
16
15
14
13
1OE
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
Vcc
2OE
1Y1
2A4
1Y2
2A3
1Y3
2A2
SCKI
V
IN
L+
V
COM
L
AGNDL
V
REF
L
V
REF
R
AGNDR
V
COM
R
V
IN
R+
V
IN
R -
OSR0
OSR1
OSR2
S/M
FMT0
FMT1
LRCK/
DSDBCK
BCK/DSDL
DATA/DSDR
OVFL
OVFR
BYPAS
RST
CLK Control
V
IN
L -
DGND V
DD
AGNDV
CC
Delta-sigma
Modulator (L)
V
REF
L
V
REF
R
Delta-sigma
Modulator (R)
Power Supply
Decimation
Filter (L)
Decimation
Filter (R)
HPF
HPF
Serial
Output
Interface
9
10
12
11
2Y1
GND
1Y4
2A1
1OE
1
1A1
2
1A2
4
1A3
6
1A4
8
18
16
14
12
1Y1
1Y2
1Y3
1Y4
2OE
19
2A1
11
2A2
13
2A3
15
2A4
17
9
7
5
3
2Y1
2Y2
2Y3
2Y4
Pin Name Function
PCM1804 Terminal Function
Pin
No.
1VREFLL-channel voltage reference output, requires capacitors for decoupling to AGND.
2 AGNDL Analog ground for VREFL.
3VCOMLL-channel analog common mode output.
4VINL+ I L-channel analog input, positive pin.
5VINL−I L-channel analog input, negative pin.
6 FMT0 I Audio data format 0. See TABLE V. *
7 FMT1 I Audio data format 1. See TABLE V. *
8 S/M I Master/slave mode selection. See TABLE IV. *
9 OSR0 I Oversampling ratio 0. See TABLE I. TABLE II. *
10 OSR1 I Oversampling ratio 1. See TABLE I. TABLE II. *
11 OSR2 I Oversampling ratio 2. See TABLE I. TABLE II. *
12 BYPAS I HPF bypass control. HIGH: HPF disable, LOW: HPF enable. ***
13 DGND Digital ground.
14 VDD Digital power supply.
15 DATA/DSDR O L-channel and R-channel audio data output in PCM mode. R-channel Audio data output in DSD mode.(DSD output, when DSD mode)
16 BCK/DSDL I/O Bit clock input/output in PCM mode. L-channel audio data output in DSD mode. ***
17 LRCK/DSDBCK I/O Sampling clock input/output in PCM and DSD mode. ***
18 SCKI I System clock input; 128fs, 256fs, 384fs, 512fs or 768fs. **
19 RST I Reset, power down input, active LOW. *
20 OVFR O Overflow signal of R-channel in PCM mode. This is available in PCM mode only.
21 OVFL O Overflow signal of L-channel in PCM mode. This is available in PCM mode only.
22 VCC Analog power supply.
23 AGND Analog ground.
24 VINR−I R-channel analog input, negative pin.
25 VINR+ I R-channel analog input, positive pin.
26 VCOMRR-channel analog common mode output.
27 AGNDR Analog ground for VREFR.
28 VREFRR-channel voltage reference output, requires capacitors for decoupling to AGND.
I/O
* Schmitt trigger input with internal pull-down (51kW typically), 5V tolerant.
** Schmitt trigger input, 5V tolerant.
*** Schmitt trigger input.

17
17
DN-X1500
TC94A32F (IC502,505,508,511,513)
BU2152FS (IC305,701,702,703,704)
L/R-TVR-REF 20kohm
L/R-TVR-IN
L/R-TVR-OUT
L/R-MVR-OUT
50kohm
20kohm
L/R-MVR-AGND
L/R-MVR-IN
28
272
1613
1712
1811
1910
209
218
227
236
245
254
26
VDD
Trim VR
0~+24dB/
1dB step
Trim VR
0~+24dB/
1dB step
Main VR
0~-95dB/
0.5dB step
Main VR
0~-95dB/
0.5dB step
DATA
STB
CS2
NC
MVR-IN
NC
MVR-A-GND
MVR-OUT
TVR-OUT
TVR-IN
TVR-REF
3
VSS
CK
GND
CS1
NC
MVR-IN
NC
MVR-A-GND
MVR-OUT
TVR-OUT
TVR-IN
TVR-REF
1
NCNC
1514
NCNC
Function
Pin
No. Pin Name
2 VSS
27 VDD
12 GND
3 L-TVR-REF Trim volume circuit
26 R-TVR-REF
4 L-TVR-IN
25 R-TVR-IN
5 L-TVR-OUT
24 R-TVR-OUT
6 L-MVR-OUT Main volume circuit
23 R-MVR-OUT
7 L-MVR-AGND
22 R-MVR-AGND
9 L-MVR-IN
20 R-MVR-IN
Chip select code switching input
11 CS1
18 CS2
13 CK Clock input pin for data transfer
16 DATA A-SW control data input pin
17 STB Strobe input pin for data writing
1, 28,
8, 21, NC
10,19,
14,15
CS1 CS2
L L0001
HL1001
L H0101
HH1101
Chip select code
TC94A32F Terminal Function
34567891011121314
28 27 26 25 24 23 22 21 20 19 18 17
16 15
V
S
S
C
L
K
V
S
S
D
A
T
A
P
1
P
2
P
3
P
4
P
5
P
6
P
7
P
8
P
9
P
10
P
11
P
12
V
D
D
C
L
B
S
T
B
S
0
P
15
P
14
P
13
P
18
P
17
P
16
P
21
P
20
P
19
P
24
P
23
P
22
12
30 2932 31
BU2152FS Terninal Function
Pin No. Pin Name FunctionI/O
1VSS
CLK
2
VSS
3
DATA4
P1
P2
P3
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
P24
P23
P22
P21
P20
P19
P18
P17
P16
P15
P14
P13
P12
P11
P10
P9
P8
P7
P6
P5
P4
28
S0
CLB
STB
29
VDD
30
31
32
Ground pin
Clock signal input
Strobe signal input
Cascade output
Clear signal input
"L"active
"L"active
Ground pin
Parallel data output
Ground pin
Power Supply pin
I
I
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
-
-
I
-

18
18
DN-X1500
TC4051BF (IC306,307,705,706,707,708)
1
2
3
4
5
6
7
8
4
6
7
COM
5
INH
V
EE
V
DD
V
SS
16
15
14
13
12
11
10
9
2
1
0
3
A
B
C

19
19
DN-X1500
M66005AFP (IC201)
RESET Reset Input
CS Chip Select Input
SCK Shift Clock Input
SDATA Serial Data Input
X
IN Clock Input
X
OUT Clock Output
DIG 00~ Digit Output
DIG 15
SEG 00~ Segment Output
SEG 35
P0, P1
V CC1
V CC2
Vss
Vp
Symbol Name Function
(Forwarding connection of segment output terminal.)
M66005AFP Terminal Function
Initialzes internal state of M66005.
Able to communicate with MCU in "L" mode.
Command from MCU will be disregareded in "H" mode.
Shifts input data at rise from "L" to "H".
Inputs character code or command data needed to display from MSB.
Sets oscillation frquency by connecting external resistor and capacitor (maximum
oscillation frequency fosc (max)=1MHz). Also feasible to apply external clock. In this case,
inject external clock to Xin terminal and open Xout terminal.
Connect to digit terminal of VFD. DIG00~DIG15 correspond to the 1st figure to 16th figure
respectively.
Connect to segment terminal of VFD. For corresponding SEG00~SEG35 to segment
terminal of VFD, refer to the figure right.
Output port (static operation).
Positive power supply terminal for internal logic.
Positive power supply terminal for high tension output port.
GND terminal.
Negative power supply terminal for VFD drive.
in the right figure indicates 1 dot of segment, the figure in shows the segment output
terminal number (00~35) to be connected.
2 1
1 4
1 6
1 5
2 0
1 3
1 8
1 7
5 9
3 3
3 1
2 3
6 4
1 2
1
6 1
D i s p l a y C o n t r o l
R e g i s t e r
C h i p S e l e c t I n p u t
S h i t C l o c k I n p u t
S e r i a l D a t a I n p u t
C S
S C K
S D A T A
D i s p l a y C o d e R e g i s t e r
( 8 - b i t x 1 6 )
S e r i a l
R e c e p t i o n
C i r c u i t
c o d e
w r i t e
C o d e /
C o m m a n d
C o n t r o l C i r c u i t
R A M
w r i t e
D e c o d e rD e c o d e r
C G R O M
( 3 5 - b i t x 1 6 0 )
C G R O M
( 3 5 - b i t x 1 6 )
S e g m e n t
O u t p u t
C i r c u i t
S E G
S E G
S E G
S E G
0 0
2 6
2 7
3 5
S e g m e n t
O u t p u t
O u t p u t P o r t
( 2 - b i t )
P 0
P 1 O u t p u t P o r t
R e s e t I n p u t R E S E T
C l o c k I n p u t X I N
C l o c k O u t p u t X O U T
C l o c k
G e n e r a t i o n
C i r c u i t
c o d e s e l e c t
D i s p l a y C o n t r o l l e r
D i g i t O u t p u t
C i r c u i t
D I G
D I G
D I G
D I G
0 0
1 1
1 2
1 5
D i g i t O u t p u t
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
2 1
2 2
2 3
2 4
2 5
2 6
2 7
2 8
2 9
3 0
3 1
3 2
6 4
6 3
6 2
6 1
6 0
5 9
5 8
5 7
5 6
5 5
5 4
5 3
5 2
5 1
5 0
4 9
4 8
4 7
4 6
4 5
4 4
4 3
4 2
4 1
4 0
3 9
3 8
3 7
3 6
3 5
3 4
3 3
D I G
1 1
D I G
1 0
D I G
0 9
D I G
0 8
D I G
0 7
D I G
0 6
D I G
0 5
D I G
0 4
D I G
0 3
D I G
0 2
D I G
0 1
D I G
0 0
R E S E T
C S
S C K
S D A T A
P I
P O
V c c 1
X
o u t
X
i n
V s s
S E G
3 5
S E G
3 4
S E G
3 3
S E G
3 2
S E G
3 1
S E G
3 0
S E G
2 9
S E G
2 8
S E G
2 7
V p S E G
2 6
S E G
2 5
S E G
2 4
S E G
2 3
S E G
2 2
S E G
2 1
S E G
2 0
S E G
1 9
S E G
1 8
S E G
1 7
S E G
1 6
S E G
1 5
S E G
1 4
S E G
1 3
S E G
1 2
S E G
1 1
S E G
1 0
S E G
0 9
S E G
0 8
S E G
0 7
S E G
0 6
S E G
0 5
S E G
0 4
S E G
0 3
S E G
0 2
S E G
0 1
S E G
0 0
V c c 2
D I G
1 5
D I G
1 4
D I G
1 3
D I G
1 2
00 01 02 03 04
05 06 07 08 09
10 11 12 13 14
15 16 17 18 19
20 21 22 23 24
25 26 27 28 29
30 31 32 33 34
35

20
20
DN-X1500
GP1S094HCZ (IC401,402,403,404)
A OUTPUT
A –INPUT
A +INPUT
V
B OUTPUT
V
B –INPUT
B +INPUT
1
2
3
45
7
8
6
1
2
1A
1B
2Y
2A
2B
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
Vcc
4Y
4B
4A
3Y
3B
3A
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1A
1B
1Y
2A
2B
2Y
GND
Vcc
4B
4Y
4A
3B
3A
3Y
NJM7915FA (IC907)
Output
Input
GND
Output
GND
Input
FRONT
VIEW
1234
1. V
IN
2. VO
3. GND
4. V
C
BA4510F(IC302~316)
NJM2068MD(IC317~320)
NJM4556AD(IC708)
SN74LV02APW(DSP:IC114)SN74LV08APW(IC104,DSP:IC115)
SN74AHCT08PW (IC107)
NJM7815FA(S)(IC906)
PQ018EF01SZ
(IC106)
8
7
6
5
1
2
3
4
5
7
8
6
Vcc
1Y
3A
2Y
1
2
3
4
1A
3Y
2A
GND
FRONT
VIEW
BA05T (IC901,902,905)
TC7WU04F (IC403,503)
+
+
1
2
A Output
A-Input
A+ Input
V-B+ Input
B-Input
B Output
V+
UPC4570C (IC601,602)
1
2
3
12
3 4
4
Anode
Collector
Emitter
Cathode