Denon AVR-2801/981 User manual
Hi-Fi Component
SERVICE MANUAL
MODEL
AVR-2801/981
AV SURROUND RECEIVER
Some illustrations using in this service manual are slightly different from the actual set.
TUNING
BAND TITLE
MENU/GUIDE
MODE
MEMORY
USE/LEARN T.TONE MULTI OUTPUT SET UP
RETURN
STATUS
DISPLAY
ON SCREEN
SYSTEM
SETUP
SURROUND
PARAMETER
CH SELECT
SELECT
ENTER
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TEL 13942296513 QQ 376315150 892498299
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2
AVR-2801/981
SPECIFICATIONS
AUDIO SECTION
(Power Amplifier)
Rated output: Front: 90 W + 90 W (8 Ω/ohms, 20 Hz ~ 20 kHz with 0.05 % T.H.D.)
135 W + 135 W (6 Ω/ohms, 1 kHz with 0.7 % T.H.D.)
Center: 90 W (8 Ω/ohms, 20 Hz ~ 20 kHz with 0.05 % T.H.D.)
135 W (6 Ω/ohms, 1 kHz with 0.7 % T.H.D.)
Surround: 90 W + 90 W (8 Ω/ohms, 20 Hz ~ 20 kHz with 0.05 % T.H.D.)
135 W + 135 W (6 Ω/ohms, 1 kHz with 0.7 % T.H.D.)
Dynamic power: 120 W ×2 ch (8 Ω/ohms)
170 W ×2 ch (4 Ω/ohms)
200 W ×2 ch (2 Ω/ohms)
Output terminals: Front: A or B 6 ∼16 Ω/ohms
A+B 8∼16 Ω/ohms
Surround/Center: 6 ∼16 Ω/ohms
(Analog)
Input sensitivity/input impedance: 200 mV/47 kΩ/kohms
Frequency response: 10 Hz ~ 100 kHz: +0, −3 dB (DIRECT mode)
S/N: 102 dB (DIRECT mode)
Distortion: 0.008 % (20 Hz ~ 20 kHz) (DIRECT mode)
Rated output: 1.2 V
(Digital)
D/A output: Rated output −2 V (at 0 dB playback)
Total harmonic distortion - 0.008% (1 kHz, at 0 dB)
S/N ratio −102 dB
Dynamic range - 96 dB
Digital input: Format −Digital audio interface
(Phono equalizer (PHONO input-REC OUT))
Input sensitivity: 2.5 mV
RIAA deviation: ±1 dB (20 Hz to 20 kHz)
Signal-to-noise ratio: 74 dB (A weighting, with 5 mV input)
Rated output/Maximum output: 150 mV/7 V
Distortion factor: 0.03% (1 kHz, 3 V)
VIDEO SECTION
(Standard Video Jacks)
Input/output level and impedance: 1 Vp-p, 75 Ω/ohms
Frequency response: 5 Hz ~ 10 MHz −+0, −3 dB
(S-video jacks)
Input/output level and impedance: Y (brightness) signal −1 Vp-p, 75Ω/ohms
C (color) signal −0.286 Vp-p, 75Ω/ohms
Frequency response: 5 Hz ~ 10 MHz − +0, −3 dB
TUNER SECTION [FM] (Note: µV at 75 Ω/ohms, 0 dBf = 1 ×10-15 W) [AM]
Receiving range: 87.50 MHz ~ 107.90 MHz 520 kHz ~ 1710 kHz
(for North America model) (for North America model)
87.50 MHz ~ 108.00 MHz 522 kHz ~ 1611 kHz
(for Europe, China, Hong Kong, (for Europe, China, Hong Kong,
Taiwan R.O.C. and Multiple voltage models
)
Taiwan R.O.C. and Multiple voltage models
)
Usable sensitivity: 1.0 µV (11.2 dBf) 18 µV
50 dB quieting sensitivity: MONO 1.6 µV (15.3 dBf)
STEREO 23 µV (38.5 dBf)
S/N ratio: MONO 80 dB
STEREO 75 dB
Total harmonic distortion: MONO 0.15 %
STEREO 0.3 %
GENERAL
Power supply: AC120 V, 60 Hz (for North America and Taiwan R.O.C. models)
AC230 V, 50 Hz (Europe model)
AC220 V, 50 Hz (for China model)
AC115/230 V, 50/60 Hz (for Hong Kong and Multiple voltage)
Power consumption: 5.0 A (for North America model)
270 W (for Europe, China, Hong Kong, Taiwan R.O.C. and Multiple voltage models
)
Maximum external dimensions: 434 (W) ×171 (H) ×416 (D) mm (17-3/32″×6-11/32″×16-3/8″)
Weight: 11.5 kg (25 lbs. 6 oz.)
REMOTE CONTROL UNIT (RC-881: for North America, China, Hong Kong,Taiwan R.O.C. and Multiple voltage models)
(RC-882: for Europe model)
Batteries: R6P/AA Type (two batteries)
External dimensions: 70 (W) ×215 (H) ×24 (D) mm (2-3/4″× 8-15/32″×15/16″)
Weight: 200 g (Approx. 7 oz.) (including batteries)
SAFETY PRECAUTIONS
The following check should be performed for the continued protection of the customer and service technician.
LEAKAGE CURRENT CHECK
Before returning the unit to the customer, make sure you make either (1) a leakage current check or (2) a line to chassis
resistance check. If the leakage current exceeds 0.5 milliamps, or if the resistance from chassis to either side of the
power cord is less than 460 kohms, the unit is defective.
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3
AVR-2801/981
WIRE ARRANGEMENT
If wire bundles are untied or moved to perform adjustment or parts replacement etc.,be sure to rearrange them neatly as they
were originally bundled or placed afterward.
Otherwise, incorrect arrangement can be a cause of noise generation.
Wire arrangement viewed from the top
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TEL 13942296513 QQ 376315150 892498299
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4
AVR-2801/981
DISASSEMBLY
(Follow the procedure below in reverse order when reassembling)
1. Top Cover
Remove 3 screws on the rear and 6 screws on both
sides to detach the Top Cover as shown in the arrow
direction.
2. Front Panel
(1) Remove 7 screws from the top and bottom edges of
the Front Panel.
(2) Release 4 top and bottom hooks, then detach the Front
Panel as shown in the arrow direction.
Top Cover
Front panel
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3
3. Inner Panel
Pull out the Inner Panel in the arrow direction after removing
3 screws .
4
Inner panel
Hook
Hook
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2
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4
4
Hook
Hook
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5
AVR-2801/981
4. Inner Panel Ass'y
(1) Remove 3 round and 1 square knobs, and unscrew 4
nuts.
(2) Remove 19 screws fixing each P.W.B.
5. Amp Unit
(1) Remove 2 screw to detach Pre-out Unit .
(2) Take off the Amp Unit as shown in the arrow direction
after removing 1 screw .
Nut
5
6 7
8
9
10
6. Regulator Unit
Take off the Regulator Unit as shown in the arrow
direction after removing 8 screws .
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5
Round knob
Square knob
Round knob
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Nut
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TEL 13942296513 QQ 376315150 892498299
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6
AVR-2801/981
7. S-Video / C-video / Audio-in & DSP /
Ext-in & VR / Digital-in / Tuner Unit
(1) Remove 38 screws to detach the Rear Panel.
(2) Take off the objective P.W.B. upward.
13
8. How to Check Power Amp / µµ
µµ
µ-com Unit
with Power-on
(1) Remove 12 screws , 1 screw , and 4 screws
fixing to the Chassis.
(2) Pull up the Unit to separate from the Chassis.
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Rear Panel
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TEL 13942296513 QQ 376315150 892498299
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+
−+−+
−+
−
+
−
+
−
+
+
ADC DSP DAC
LPF
RIAA
BUFF. A/D IN AMP
D/A OUT AMP
TO
H.P.F.
VR
ADDER.
FROM.
(S.W.ch.)
EQ.AMP
PRE AMP
CINEMA EQ
TONE
POWER AMP
SP-OUT
SP-OUT
H/P-OUT
PRE-OUT
PRE-OUT
D/A OUT AMP
VR POWER AMP
SP-OUT
SP-OUT
PRE-OUT
PHONO-IN
LINE-IN
EXT.-IN
EXT.-IN
10kHz: −4dB
+
−
LPF
PRE AMP
CINEMA EQ
CENTER CH ONLY
10kHz: −4dB
(dBV) (dB)
30
20
10
0
−10
40
30
20
10
0dB
−30
−14
−20
−50
EXT.IN 200mV
D/A OUT(DOLBYDIGITAL: DIALNORM−27dB)
D/A OUT(DOLBYDIGITAL: DIALNORM−27dB)
200mV/EXT.IN
LINE-IN 200mV
PHONO 2.5mV (−52dBV)
−9dB
A/D IN
0dBfs
−10dBfs
−20dBfs
−30dBfs
A/D
0dBfs
−10dBfs
−20dBfs
−30dBfs
D/A
15.5dB 16.5dB
(TONE)
1.2V (1.58dBV) (DIRECT)
42.6dB→27V, 28.6dBV
−
38dB
FROM
DSP
(dBV) (dB)
30
20
10
0
−10
40
30
20
10
0dB
−14
−20
0dBfs
−10dBfs
−20dBfs
−30dBfs
D/A
1.2V (1.58dBV)
15.5dB
LEVEL: Same as Front ch
PRE-OUT
~
~
~
~
+
−
+
−
DAC
+
−
LEVEL DIAGRAM
7
D
C
B
A
876
E
1 4
32 5
AVR-2801/981
FRONT
CENTER
SURROUND
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TEL 13942296513 QQ 376315150 892498299
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8
8765
14
32
B
C
D
A
E
AVR-2801/981
SUBWOOFER
− − +
+−
(FRONT CH)
FRONT L/R ADD.
LPF
D/A OUT AMP
ADDER INV
(FRONT CH)
TO
ATTN. PRE AMP
PRE-OUT
EXT.-IN
PRE-OUT
0dBfs
−10dBfs
−20dBfs
−30dBfs
−40dBfs
D/A
1.2V (1.58dBV)
2.15V (6.65dBV)
20.5dB
2.5dB
1.5dB
1.5dB
11dB
11dB
3dB
TO FRONT CH
20.5dB
(dBV)
30
20
10
0
−10
10
0dB
−14
−20
(dB)
40
30
20
200mV/EXT.IN
FROM
R ch FROM
L ch
+
−
DAC+
−
D/A OUT(DOLBYDIGITAL: DIALNORM
−27dB)
Config2
Config1
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CH1: DATA
CH2: fs
CH3: 64fs
CH4: 256fs
CLOCK FLOW & WAVE FORM IN DIGITAL BLOCK
Wave Form
CH1: D-DATA
(IC705 (5) )
CH1: DATA
CH2: fs
CH3: 64fs
12
9
AVR-2801/981
4
CH1: DATA
CH2: fs
CH3: 64fs
3
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A/D SELECTOR
IC804
SN74AHC157PW
*fs is a sampling frequency of input digital signal.
e.g.:sampling frequency 48kHz →fs=48kHz
*64fs and 256fs are 64 or 256 times the sampling
frequency respectively.
e.g.: sampling frequency 48kHz
64fs: 48kHzX64=3.072MHz
256fs: 48kHzX256=12.288MHz
*The samoling frequency for analog input is fixed
to 48kHz internally.
*(No.) indicates the pin unmber of individual
*The arrow indicates the direction of signal
as the input terminal pointed by the arrow
and the output terminal by the opposite.
D/A CONVERTER
IC701
AD1854
(2)256fs
(26)64fs Fch
(25)fs
(27)DATA
IC702
AD1854
(2)256fs
(26)64fs C&SWch
(25)fs
(27)DATA
IC703
AD1854
(2)256fs
(26)64fs Sch
(25)fs
(27)DATA
INPUT
SELECTOR1
IC705
TC74HC
151AF
COAX1 (13)
OPT1 (15) (5)
OPT2 (3)
OPT3 (2)
IC800
LC89055W
CKOUT(13)
(5)DIN2 BCK(14)
LRCK(15)
DATAD(16)
XIN(22)
12.287MHz
IC802
SG-8002
(3)
A/D CONVERTER
IC604
AK5353
MCLK(11)
AIN SCLK(12)
LRCK(10)
SDATA(9)
MCLK
(44) (22) (25) (26)
SCLKN1LRCKN1SDATAN1
AUDATA0(41)
AUDATA1(40)
AUDATA2(39)
(30)CLKIN
IC814
CS492604
DSP1
21
3
(27) (43) (42)
SCLK LRCLKCMPDAT
9624 SELECTOR
IC805
TC74HCT157AF
4
MCLK
DA SCK
DA LRCK
SD IN
256fs
64fs
fs
FRONT
CENTER/SW
SURROUND
256fs
64fs fs
DATA
IC606 (7)
(13)
(10)
SN74LV4040APW
DIR
12 3 4567 8
A
B
C
D
E
10
AVR-2801/981
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TEL 13942296513 QQ 376315150 892498299
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ADJUSTMENTADJUSTMENT
Tuner SectionTuner Section
CONNECTION DIAGRAM OF MEASURING INSTRUMENTSCONNECTION DIAGRAM OF MEASURING INSTRUMENTS
''
FMFM
''
AMAM
1111
AVR-2801/981AVR-2801/981
T503
IC502
1
12 Pin
GND
AM
AM IF
OUT
OSCILLOSCOPE
1U-3235-5 TUNER UNIT
STEREO
MODULATOR
FMSSG
DIGITAL
VOLTMETER
TP102
T502 VR501
VR502
IC502
75Ω
1
1U-3235-5 TUNER UNIT
FM/MPX ALIGNMENT
Input Output Adjust
Step
Alignment
Item
Tuning
Frequency
Setting Type
Frequency
Input Level
Modulation
Coupling Type
Connect to
Points Adjust to Remarks
1
Tuning Center
98.1 MHz FM SSG 98.1 MHz 60 dBµNone Antenna
Terminal
Digital
Voltmeter TP102 T502 ±50mV
Function : FM
Mode : Auto
2
Separation
98.1 MHz FM SSG 98.1MHz 60 dBµ
Stereo (L)
1KHz 100%
Antenna
Terminal
AC
Voltmeter
AUDIO
OUT
Terminal (R)
VR502 Maximum
Separation
3
Signal Level
98.1MHz FM SSG 98.1MHz 20 dBµOff Antenna
Terminal VR501
Light
“TUNED”
FLD
Character
AM ALIGNMENT
Output Adjustment
Step
Alignment
Item Frequency Input Type
Connect to
Points Adjust to Remarks
1
IF IF SWEEP
(Input level is not over to work A.G.C.)
Oscilloscope
IC502 12Pin
T503
Maximum height and best
symmetry curve
1kHz1kHz
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TEL 13942296513 QQ 376315150 892498299
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Audio Section
Idling Current (1U-3232-1)
Required measurement equipment : DC Voltmeter
Preparation
(1) Avoid direct blow from an air conditioner or an electric fan, and adjust the unit at normal room tempereture 15 °C ~ 30 °C
(59 °F ~ 86 °F).
(2) Presetting
lPOWER (Power sourse switch) →OFF
lSPEAKER (Speaker terminal) →No load (Do not connect speaker, dummy resistor, etc.)
Adjustment
(1) Remove top cover and set VR501, VR502, VR503, VR504, VR505, on 1U-3232-1 (Power Unit) at counterclockwise
( ) fully.
(2) Connect DC Voltmeter to test points (FRONT-Lch: TP501, FRONT-Rch: TP502, CENTER ch: TP505, SURROUND-Lch:
TP503, SURROUND-Rch: TP504).
(3) Connect power cord to AC Line, and turn power switch "ON".
(4) Presetting. MASTER VOLUME : "---" counterclockwise ( min.)
MODE : 5CH STEREO
FUNCTION : CD
(5) Allow 2 minutes, and turn VR501 clockwise ( ) and adjust the TEST POINT voltage to 1.5 mV ±0.5 mV DC.
(6) After 10 minutes from preset, turn VR501 to set the voltage to 3 mV ±0.5 mV DC.
(7) Adjust the Variable Resistors of other channels in the same way.
(8) After 5 minutes from (6), turn VR501 to set the voltage to 3 mV ±0.5 mV DC.
(9) Adjust the Variable Resistors of other channels in the same way.
12
AVR-2801/981
VR504
TP504
VR502
TP502
VR505
TP505
VR501
TP501
VR503
TP503
S Rch
F Rch
Cch
F Lch
S Lch
DC Voltmeter
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TEL 13942296513 QQ 376315150 892498299
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NameName FunctionFunction
TMP88CU74F Terminal FunctionTMP88CU74F Terminal Function
PinPin
No.No.
11 P02/S01P02/S01 RDS RESETRDS RESET OO CC ZZ LL RDS reset output (LC7074)RDS reset output (LC7074)
22 P03P03 OSD RSTOSD RST OO CC ZZ HH OSD control output (M35015)OSD control output (M35015)
33 P04P04 ST/MONOST/MONO OO CC ZZ LL STEREO/MONO control signal, L: STEREOSTEREO/MONO control signal, L: STEREO
44 P05P05 PLFL DATAPLFLDATA OO CC ZZ LL PLL, FL control terminal (LC72131 & LC75721NE)PLL, FL control terminal (LC72131 & LC75721NE)
55 P06P06 PLL STBPLL STB OO CC ZZ LL PLL control terminal (LC72131)PLL control terminal (LC72131)
66 P07P07 PLFL CLKPLFL CLK OO CC ZZ LL PLL, FL control terminal (LC72131 & LC75721NE)PLL, FL control terminal (LC72131 & LC75721NE)
77 VssVss VssVss II GNDGND LL GNDGND
88 XoutXout XoutXout OO XTALXTAL
99 XinXin XinXin II XTALXTAL
1010 RESET_RESET_ RESET_RESET_ II EuEu LvLv LL Reset inputReset input
1111 P22/XTOUTP22/XTOUT TUNED_TUNED_ II EuEu LvLv ZZ Tuning detect, L: TunedTuning detect, L: Tuned
1212 P21/XTINP21/XTIN STEREO_STEREO_ II EuEu LvLv ZZ L: At stereo receiveL: At stereo receive
1313 TESTTEST TESTTEST II GNDGND SS Connect to GNDConnect to GND
1414 P20/INT5_P20/INT5_ B.DOWN_B.DOWN_ II EuEu LvLv ZZ Power down detect, L: Power downPower down detect, L: Power down
1515 P10/INT0_P10/INT0_ PROTECT_PROTECT_ II EdEd E&LE&L ZZ PROTECTION detect input, H: DetectPROTECTION detect input, H: Detect
1616 P11/INT1P11/INT1 RDS STARTRDS START II ZZ LL RDS data input (LC7074)RDS data input (LC7074)
1717 P12P12 OSD CLKOSD CLK OO CC ZZ HH OSD control output (M35015)OSD control output (M35015)
1818 P13P13 OSD CSOSD CS OO CC ZZ HH OSD control output (M35015)OSD control output (M35015)
1919 P14P14 OSDDATAOSDDATA OO CC ZZ LL OSD control output (M35015)OSD control output (M35015)
2020 P15/INT3P15/INT3 REMOCONREMOCON II EdEd E&LE&L ZZ Remote control signal inputRemote control signal input
2121 P16/INT2P16/INT2 ACKACK OO CC ZZ LL MAIN-SUB CPU comm. control terminalMAIN-SUB CPU comm. control terminal
2222 P17/INT4P17/INT4 REQREQ II EuEu ZZ LL MAIN-SUB CPU comm. control terminalMAIN-SUB CPU comm. control terminal
2323 P30/SCLP30/SCL SISI II MAIN-SUB CPU comm. control terminalMAIN-SUB CPU comm. control terminal
2424 P31/SDAP31/SDA SOSO OO CC MAIN-SUB CPU comm. control terminalMAIN-SUB CPU comm. control terminal
2525 P32/SCK0_P32/SCK0_ CLKCLK OO CC MAIN-SUB CPU comm. control terminalMAIN-SUB CPU comm. control terminal
2626 P40/AIN0P40/AIN0 MODEMODE II EuEu LvLv ZZ Destination switching inputDestination switching input
2727 P41/AIN1P41/AIN1 KEY1KEY1 II EuEu LvLv ZZ Button input 1Button input 1
2828 P42/AIN2P42/AIN2 KEY2KEY2 II EuEu LvLv ZZ Button input 2Button input 2
2929 P43/AIN3P43/AIN3 KEY3KEY3 II EuEu LvLv ZZ Button input 3Button input 3
3030 P44/AIN4P44/AIN4 FUNC STB1FUNC STB1 OO CC ZZ Function control output (TC9274N), INPUTFunction control output (TC9274N), INPUT
3131 P45/AIN5P45/AIN5 FUNC/T. CON CLKFUNC/T. CON CLK OO CC ZZ LL
Function control output (TC9274N, TC9273), TONE control output (TC9184P)Function control output (TC9274N, TC9273), TONE control output (TC9184P)
3232 P46/AIN6P46/AIN6 FUNC/T. CON DATAFUNC/T. CON DATA OO CC ZZ LL
Function control output (TC9274N, TC9273), TONE control output (TC9184P)Function control output (TC9274N, TC9273), TONE control output (TC9184P)
3333 P47/AIN7P47/AIN7 FUNC STB2FUNC STB2 OO CC ZZ LL Function control output (NJU7313), 6CH EXT. INFunction control output (NJU7313), 6CH EXT. IN
3434 P50/AIN8P50/AIN8 E.VOL STBE.VOL STB OO CC LL LL Elect. volume control output (TC9459)Elect. volume control output (TC9459)
3535 P51/AIN9P51/AIN9 TONE STBTONE STB OO CC LL LL TONE control output (TC9184P)TONE control output (TC9184P)
3636 P52/AIN10P52/AIN10 E.VOLDATAE.VOLDATA OO CC LL HH Elect. volume control output (TC9459)Elect. volume control output (TC9459)
3737 P53/AIN11P53/AIN11 E.VOL CLKE.VOL CLK OO CC LL HH Elect. volume control output (TC9459)Elect. volume control output (TC9459)
SymbolSymbol I/OI/O TypeType OpOp DetDet ResRes InitInit
SEMICONDUCTORSSEMICONDUCTORS
&&
IC’sIC’s
Note:Note: Abbreviation ahead of IC No. indicates the name of P.W.B.Abbreviation ahead of IC No. indicates the name of P.W.B.
PO:PO: Power P.W.B.Power P.W.B. RE:RE: Requlator P.W.B.Requlator P.W.B.
EX:EX: Exit in P.W.B.Exit in P.W.B. AU:AU: Audio/DSP P.W.B.Audio/DSP P.W.B.
CO:CO: Control P.W.B.Control P.W.B.
TMP88CU74FTMP88CU74F
(CO: IC303)(CO: IC303)
FunctionFunction
3838 VASSVASS VASSVASS II Ref. volt (GND)Ref. volt (GND)
3939 VAREFVAREF VAREFVAREF II Ref. volt (VDD)Ref. volt (VDD)
4040 VDDVDD VDDVDD II Power supplyPower supply
4141 P60P60 FL CEFL CE OO PP EdEd SS LL HH FL display control output (LC75712NE)FL display control output (LC75712NE)
4242 P61P61 FL RESFL RES OO PP EdEd SS LL HH FL display control output (LC75712NE)FL display control output (LC75712NE)
4343 P62P62 FUNC STB3FUNC STB3 OO PP EdEd ZZ LL Function control output (TC9273), REC OUTFunction control output (TC9273), REC OUT
4444 P63P63 FA-RELAYFA-RELAY OO PP IdId LL LL Front SP relay A control terminal, L: MuteFront SP relay A control terminal, L: Mute
4545 P64P64 FB-RELAYFB-RELAY OO PP IdId LL LL Front SP relay B control terminal, L: MuteFront SP relay B control terminal, L: Mute
4646 P65P65 C-RELAYC-RELAY OO PP IdId LL LL Center SP relay control terminal, L: MuteCenter SP relay control terminal, L: Mute
4747 P66P66 S-RELAYS-RELAY OO PP IdId LL HH Surround SP relay control terminal, L: MuteSurround SP relay control terminal, L: Mute
4848 P67P67 PRE F MUTEPRE F MUTE OO PP EdEd LL HH Front PRE OUT mute control terminal, L: MuteFront PRE OUT mute control terminal, L: Mute
4949 P70P70 PRE C MUTEPRE C MUTE OO PP EdEd LL LL Center PRE OUT mute control terminal, L: MuteCenter PRE OUT mute control terminal, L: Mute
5050 P71P71 PRE S MUTEPRE S MUTE OO PP EdEd LL LL Surround PRE OUT mute control terminal, L: MuteSurround PRE OUT mute control terminal, L: Mute
5151 P72P72
SUB WOOFER MUTESUB WOOFER MUTE
OO PP EdEd LL HH Sub-woofer PRE OUT mute control terminal, L: MuteSub-woofer PRE OUT mute control terminal, L: Mute
5252 P73P73 H/P RELAYH/P RELAY OO PP IdId LL HH H/P OUT relay control terminal, L: MuteH/P OUT relay control terminal, L: Mute
5353 P74P74 EXP OEEXP OE OO PP EdEd LL HH Port expander control terminal (BU4094B)Port expander control terminal (BU4094B)
5454 P75P75 EXP CLKEXP CLK OO PP EdEd LL LL Port expander control terminal (BU4094B)Port expander control terminal (BU4094B)
5555 P76P76 EXP DATAEXP DATA OO PP EdEd LL LL Port expander control terminal (BU4094B)Port expander control terminal (BU4094B)
5656 P77P77 EXP STBEXP STB OO PP EdEd LL LL Port expander control terminal (BU4094B)Port expander control terminal (BU4094B)
5757 P80P80 POWERPOWER OO PP IdId LL HH Power relay control output, H: ONPower relay control output, H: ON
5858 P81P81 RESET2RESET2 OO PP IdId LL LL Reset signal output to sub-CPU, H: ResetReset signal output to sub-CPU, H: Reset
5959 P82P82 SUB-CPU-B-DOWNSUB-CPU-B-DOWN OO PP IdId LL LL B-DOWN signal output to sub-CPUB-DOWN signal output to sub-CPU
6060 P83P83 TAPE MON. LEDTAPE MON. LED OO PP IdId LL LL TAPE MONITOR LED indicator control, H: MONITORTAPE MONITOR LED indicator control, H: MONITOR
6161 P84P84 STANDBYSTANDBY OO PP IdId LL HH Standby LED drive output H: LightStandby LED drive output H: Light
6262 P85P85 DIRECTDIRECT OO PP IdId LL LL DIRECT relay control, H: DIRECTDIRECT relay control, H: DIRECT
6363 P86P86 S1S1 OO PP IdId LL Video signal switching control outputVideo signal switching control output
6464 P87P87 S2S2 OO PP IdId LL Video signal switching control outputVideo signal switching control output
6565 P90P90 TUNER MUTETUNER MUTE OO PP EdEd LL HH TUNER mute control terminal, H: MuteTUNER mute control terminal, H: Mute
6666 P91P91 OO PP IdId LL HH Not UsedNot Used
6767 P92P92 S MONI DETS MONI DET II EuEu LvLv ZZ S monitor connection detect input, L: ConnectedS monitor connection detect input, L: Connected
6868 P93P93 S SIG DETS SIG DET II EuEu LvLv ZZ S signal detect input, H: DetectedS signal detect input, H: Detected
6969 P94P94 SYNC DET.SYNC DET. II EuEu LvLv ZZ Sync detect input, H: Ext. syncSync detect input, H: Ext. sync
7070 P95P95 SEL A (M)SEL A (M) II EuEu LvLv ZZ Master volume rotation detect input (rotary encoder)Master volume rotation detect input (rotary encoder)
7171 P96P96 SEL B (M)SEL B (M) II EuEu LvLv ZZ Master volume rotation detect input (rotary encoder)Master volume rotation detect input (rotary encoder)
7272 P97P97 CINEMA EQCINEMA EQ OO PP EuEu LvLv ZZ LL CINEMA EQ control output, H: ONCINEMA EQ control output, H: ON
7373 PD0PD0 VOL MUTEVOL MUTE OO PP EdEd LL LL Master volume minimum control, L: Min.Master volume minimum control, L: Min.
7474 PD1PD1 SEL C (S)SEL C (S) II EuEu LvLv ZZ Surround mode rotation detect input (rotary encoder)Surround mode rotation detect input (rotary encoder)
7575 PD2PD2 SEL D (S)SEL D (S) II EuEu LvLv ZZ Surround mode rotation detect input (rotary encoder)Surround mode rotation detect input (rotary encoder)
7676 PD3PD3 SEL E (F)SEL E (F) II EuEu LvLv ZZ Input selector switch rotation detect input (rotary encoder)Input selector switch rotation detect input (rotary encoder)
7777 PD4PD4 SEL F (F)SEL F (F) II EuEu LvLv ZZ Input selector switch rotation detect input (rotary encoder)Input selector switch rotation detect input (rotary encoder)
7878 VkkVkk VkkVkk GND fixedGND fixed
7979 P00/SCK1_P00/SCK1_ RDS CLKRDS CLK II SS ZZ RDS clock input (LC7074)RDS clock input (LC7074)
8080 P01/SI1P01/SI1 RDSDATARDSDATA II SS ZZ RDS data input (LC7074)RDS data input (LC7074)
I/OI/O TypeType OpOp DetDet ResRes InitInit
NameName
PinPin
No.No. SymbolSymbol
NOTE:
Pin No. : Terminal number of microcomputer.
Port Name : The name entered in the data sheet of microcomputer.
Symbol : Symbolized interface function.
I/O : Input or out of part.
“I” = Input port
“O” = Output port
Type : Composition of port in case of output port.
“C” = CMOS output
“N” = NMOS open drain output
“P” = PMOS open drain output
Op : Pull up/Pull down selection information.
“Iu” = Inner microcomputer pull up
“Id” = Inner microcomputer pull down
“Eu”= External microcomputer pull up
“Ed”= External microcomputer pull down
Det : Indicates judging state of input port. Level detection is “LV”; Edge detection is “Ed”; Detection by both shifting is “E&L”;
Serial data detection is “S” (Serial data output is also “S”).
Res : State at reset.
“H” = Outputs High Level at reset
“L” = Outputs Low Level at reset
“Z” = Becomes High impedance mode at reset
Ini : Initial output state.
Function : Function and logical level explanation of signals to be interface.
124
25
40
41
64
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AVR-2801/981AVR-2801/981
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TEL 13942296513 QQ 376315150 892498299
TEL 13942296513 QQ 376315150 892498299
http://www.xiaoyu163.com
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TMP93CS41F (AU: IC301)TMP93CS41F (AU: IC301)
NameName FunctionFunction
TMP93CS41F Terminal FunctionTMP93CS41F Terminal Function
PinPin
No.No.
11 V REFLV REFL A/D ref. GNDA/D ref. GND
22 A VssA Vss ←← A/D GNDA/D GND
33 A VccA Vcc ←← AD +5VAD +5V
44 _NMI_NMI II Not used (fixed to H)Not used (fixed to H)
55 P70/TI0P70/TI0 C15C15 OO CC LL LL Fixed to L (DSP ROM address cont. out bit 15, not used)Fixed to L (DSP ROM address cont. out bit 15, not used)
66 P71/TO1P71/TO1 C16C16 OO CC LL LL DSP program ROM address cont. output bit 16DSP program ROM address cont. output bit 16
77 P72/TO2P72/TO2 C17C17 OO CC LL LL DSP program ROM address cont. output bit 17DSP program ROM address cont. output bit 17
88 P73/TO3P73/TO3 OO CC LL LL
99 P80/INT4/TI4P80/INT4/TI4 _INTREQ_INTREQ I/OI/O CC EuEu EE↓↓&L&L ZZ DSP request input and cont. output (L: Rq & cont.)DSP request input and cont. output (L: Rq & cont.)
1010 P81/INT5/TI5P81/INT5/TI5 B. DOWN_B. DOWN_ II EuEu EE↑↑&L&L ZZ Power down detect (H: Detected)Power down detect (H: Detected)
1111 P82/TO4P82/TO4 DSP SSDSP SS OO CC ZZ LL
1212 P83/TO5P83/TO5 _REQ_REQ OO CC EuEu HH LL MAIN-SUB CPU comm. control output (L: Comm. request fromMAIN-SUB CPU comm. control output (L: Comm. request from
sub)sub)
1313 P84/INT6/TI6P84/INT6/TI6 _ACK_ACK II EuEu EE↓↓&L&L MAIN-SUB CPU comm. control input (L: Ack. return from main)MAIN-SUB CPU comm. control input (L: Ack. return from main)
1414 P85/INT7/TI7P85/INT7/TI7 ERRERR II EE↑↑&L&L DIR control input terminal (LC89055Q)( H: ERR)DIR control input terminal (LC89055Q)( H: ERR)
1515 P86/TO6P86/TO6 _DSP RESET_DSP RESET OO CC LL LL DSP reset output terminal (L: Reset)DSP reset output terminal (L: Reset)
1616 P87/INT0P87/INT0 _CS_CS II EE↑↑&L&L DIR control input terminal (LC89055Q), when CH status changeDIR control input terminal (LC89055Q), when CH status change
LL→→HH
1717 P90/TXD0P90/TXD0 SISI OO CC MAIN-SUB CPU comm. control terminal (data output)MAIN-SUB CPU comm. control terminal (data output)
1818 P91/RXD0P91/RXD0 SOSO II MAIN-SUB CPU comm. control terminal (data input)MAIN-SUB CPU comm. control terminal (data input)
1919
P92/_CTS0/SCLK0P92/_CTS0/SCLK0
CLKCLK II CC MAIN-SUB CPU comm. control terminalMAIN-SUB CPU comm. control terminal (I2C clock in/output)(I2C clock in/output)
2020 P93/TXD1P93/TXD1 DSPDATADSPDATA OO CC ZZ LL
2121 P94/RXD1P94/RXD1 DSP SODSP SO OO CC LvLv ZZ LL
2222 P95/SCLK1P95/SCLK1 DSP CLKDSP CLK OO CC ZZ LL
2323 AM8/_16AM8/_16 ←← Fixed to +5VFixed to +5V
2424 CLKCLK OO CC EuEu
2525 VccVcc ←← +5V+5V
2626 VssVss I/O1I/O1 GNDGND
2727 X1X1 XinXin II XX′′tal connectiontal connection
2828 X2X2 XoutXout OO XX′′tal connectiontal connection
2929 _EA_EA ←← Fixed to GNDFixed to GND
3030 _RESET_RESET RESET2_RESET2_ II EuEu LvLv LL Reset input (controlled by main CPU)Reset input (controlled by main CPU)
3131 P96/XT1P96/XT1 A/D RESETA/D RESET OO NN EuEu HH HH A/D control terminal (L: Reset)A/D control terminal (L: Reset)
3232 P97/XT2P97/XT2 OO CC EdEd LL LL
3333 TEST1TEST1 ←← ΙΙ Connected to TEST2Connected to TEST2
3434 TEST2TEST2 ←← ΙΙ Connected to TEST1Connected to TEST1
3535 PA0PA0 DINADINA OO CC EdEd LL LL Digital input switching control outputDigital input switching control output
3636 PA1PA1 DINBDINB OO CC EdEd LL LL Digital input switching control outputDigital input switching control output
3737 PA2PA2 DINCDINC OO CC EdEd LL LL Digital input switching control outputDigital input switching control output
3838 PA3PA3 OO CC EdEd LL LL
3939 PA4PA4 DIRECTDIRECT OO CC EdEd LL LL Digital direct data switch cont. terminal (H: Direct)Digital direct data switch cont. terminal (H: Direct)
4040 PA5PA5 OO CC EdEd LL LL
SymbolSymbol I/OI/O TypeType OpOp DetDet ResRes InitInit
NameName FunctionFunction
PinPin
No.No.
4141 PA6PA6 DEEMPDEEMP OO CC EdEd LL LL DAC de-emphasis filter cont. out terminal (H: ON)DAC de-emphasis filter cont. out terminal (H: ON)
4242 PA7/SCOUTPA7/SCOUT 96k-DAC96k-DAC OO CC ZZ LL DAC control terminal (H: Sample frequency 96kHz)DAC control terminal (H: Sample frequency 96kHz)
4343 ALEALE ←← OO CC LL LL Address latch enableAddress latch enable
4444 VccVcc +5V+5V
4545 P00/AD0P00/AD0 AD0AD0 II
4646 P01/AD1P01/AD1 AD1AD1 II
4747 P02/AD2P02/AD2 AD2AD2 II
4848 P03/AD3P03/AD3 AD3AD3 II
4949 P04/AD4P04/AD4 AD4AD4 II
5050 P05/AD5P05/AD5 AD5AD5 II
5151 P06/AD6P06/AD6 AD6AD6 II
5252 P07/AD7P07/AD7 AD7AD7 II
5353 P10/AD8/A8P10/AD8/A8 A8A8 II
5454 P11/AD9/A9P11/AD9/A9 A9A9 II
5555 P12/AD10/A10P12/AD10/A10 A10A10 II
5656 P13/AD11/A11P13/AD11/A11 A11A11 II
5757 P14/AD12/A12P14/AD12/A12 A12A12 II
5858 P15/AD13/A13P15/AD13/A13 A13A13 II
5959 P16/AD14/A14P16/AD14/A14 A14A14 II
6060 P17/AD15/A15P17/AD15/A15 A15A15 II
6161 _WDTOUT_WDTOUT ←← OO CC ZZ HH
6262 VssVss ←← GNDGND
6363 VccVcc ←← +5V+5V
6464 P20/A0/A16P20/A0/A16 A16A16 II
6565 P21/A1/A17P21/A1/A17 DIR CLKDIR CLK OO CC ZZ LL DIR control terminal (LC89055Q) control clock outputDIR control terminal (LC89055Q) control clock output
6666 P22/A2/A18P22/A2/A18 DIR CEDIR CE OO CC ZZ LL DIR control terminal (LC89055Q) control chip enable outputDIR control terminal (LC89055Q) control chip enable output
6767 P23/A3/A19P23/A3/A19 DIR MOSIDIR MOSI OO CC ZZ LL DIR control terminal (LC89055Q) control data outputDIR control terminal (LC89055Q) control data output
6868 P24/A4/A20P24/A4/A20 DIR MISODIR MISO II LvLv DIR control terminal (LC89055Q) control data inputDIR control terminal (LC89055Q) control data input
6969 P25/A5/A21P25/A5/A21 SW-SUMSW-SUM OO CC LL LL Subwoofer output summation cont. outputSubwoofer output summation cont. output
7070 P26/A6/A22P26/A6/A22 DAC-RESETDAC-RESET OO CC LL HH
DACcontrolterminal(L:Powerdownmode,DACcontrolterminal(L:Powerdownmode,
→→
(risingedge)Reset)(risingedge)Reset)
7171 P27/A7/A23P27/A7/A23 SEL CKSEL CK OO CC ZZ LL ADC/DIR data clock switching control terminal (L: ADC)ADC/DIR data clock switching control terminal (L: ADC)
7272 P30/_RDP30/_RD _RD_RDOO CC ZZ LL
7373 P31/_WRP31/_WR _WR_WROO CC ZZ LL
7474 P32/_HWRP32/_HWR CSICSI II LvLv DIR control input terminal (L: PCM)DIR control input terminal (L: PCM)
7575 P33/_WAITP33/_WAIT ERR MUTE_ERR MUTE_ OO CC LL LL Pop noise preventive mute control output (L: Mute)Pop noise preventive mute control output (L: Mute)
7676 P34/_BUSRQP34/_BUSRQ II
7777 P35/_BUSRQP35/_BUSRQ DIG. (AC3) MUTEDIG. (AC3) MUTE OO CC ZZ LL Digital mute control output (L: AC-3 or DTS decode enable)Digital mute control output (L: AC-3 or DTS decode enable)
7878 P36/_R/WP36/_R/W II
7979 P37/_RASP37/_RAS DIR RESETDIR RESET OO CC ZZ LL DIR control output (LC89055Q) (L: Reset)DIR control output (LC89055Q) (L: Reset)
8080 P40/_CS0/_CAS0P40/_CS0/_CAS0 OO CC ZZ LL
8181
P41/_CS1/_CAS1P41/_CS1/_CAS1
OO CC ZZ LL
8282
P42/_CS2/_CAS2P42/_CS2/_CAS2
_CS0_CS0 OO CC ZZ LL Flash memory control terminalFlash memory control terminal
8383 P60/PG00P60/PG00 DSP C. RESETDSP C. RESET OO CC ZZ LL DSP reset output terminal (L: Reset)DSP reset output terminal (L: Reset)
8484 P61/PG01P61/PG01 SCDOUTSCDOUT II LvLv DSP status data input terminalDSP status data input terminal
8585 P62/PG02P62/PG02 DSP_C. CSDSP_C. CS OO CC ZZ LL DSP chip select cont. output (L: Data out)DSP chip select cont. output (L: Data out)
8686 P63/PG03P63/PG03 DSP C. CLKDSP C. CLK OO CC ZZ LL DSP data clock output terminalDSP data clock output terminal
8787 P64/PG10P64/PG10 SCDINSCDIN OO CC ZZ LL DSP data output terminalDSP data output terminal
8888 P65/PG11P65/PG11 OO CC ZZ LL
8989 P66/PG12P66/PG12 OO CC ZZ LL
9090 P67/PG13P67/PG13 OO CC ZZ LL
9191 VssVss ←← GNDGND
9292 P50/AN0P50/AN0 II
9393 P51/AN1P51/AN1 II
9494 P52/AN2P52/AN2 EMPEMP II LvLv H: EMP onH: EMP on
9595 P53/AN3P53/AN3 96K DET96K DET II LvLv 96k signal detect input, H: 96k96k signal detect input, H: 96k
9696 P54/AN4P54/AN4 II
9797 P55/AN5P55/AN5 II
9898 P56/AN6P56/AN6 II
9999 P57/AN7P57/AN7 II
100100 V REFHV REFH ←← AD ref. +5VAD ref. +5V
SymbolSymbol I/OI/O TypeType OpOp DetDet ResRes InitInit
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76
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51
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TEL 13942296513 QQ 376315150 892498299
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15
AVR-2801/981
LC89055W (AU: IC800)
Pin Name Function
LC89055W Terminal Function
Pin
No.
1 DISEL I Data input terminal (select input pin of DIN0, DIN1)
2 DOUT O Input bi-phase data through output terminal
3 DIN0 I Amp built-in coaxial/optical input correspond data input terminal
4 DIN1 I Amp built-in coaxial/optical input correspond data input terminal
5 DIN2 I Optical input correspond data input terminal
6 DGND Digital GND
7 DVDD Digital power supply
8 R I VCO gain control input terminal
9 VIN I VCO free-run frequency setting input terminal
10 LPF O PLL loop filter setting terminal
11 AVDD Analog power supply
12 AGND Analog GND
13 CKOUT O Clock output terminal (256fs, 384fs, 512fs, X′tal osc., VCO free-run osc.)
14 BCK O 64fs clock output terminal
15 LRCK O fs clock output terminal (L: Rch, H: Lch, I2S: Reverse)
16 DATAO O Data output terminal
17 XSTATE O Input data detecting result output terminal
18 DGND Digital GND
19 DVDD Digital power supply
20 XMCK O X′tal osc. clock output terminal (24.576MHz or 12.288MHz)
21 XOUT O X′tal osc. connection output terminal
22 XIN I X′tal osc. connection output terminal
23 EMPHA O Emphasis information output terminal of channel status
24 AUDIO O Bit1 output terminal of channel status
25 CSFLAG O Top 40bit revise flag output terminal of channel status
26 F0/P0/C0 O Input fs cal. sig. out / data type out / input word inf. output terminal
27 F1/P1/C1 O Input fs cal. sig. out / data type out / input word inf. output terminal
28 F2/P2/C2 O Input fs cal. sig. out / data type out / input word inf. output terminal
29 VF/P3/C3 O Validity flag out / data type out / input word inf. output terminal
30 DVDD Digital power supply
31 DGND Digital GND
32 AUTO O Non PCM burst data transfer detect sig. output terminal
33 BPSYNC O Non PCM burst data preamble Pa, Pb, Pc, Pd sync sig. output terminal
34 ERROR O PLL lock error, data error flag output terminal
35 DO O CPU I/F read data output terminal
36 DI I CPU I/F write data input terminal
37 CE I CPU I/F chip enable input terminal
38 CL I CPU I/F clock input terminal
39 XSEL I Frequency select input pin of XIN X′tal osc. (24.576MHz or 12.288MHz)
40 MODE0 I Mode setting input terminal
41 MODE1 I Mode setting input terminal
42 DGND Digital GND
43 DVDD Digital power supply
44 DOSEL0 I Data output format select input terminal
45 DOSEL1 I Data output format select input terminal
46 CKSEL0 I Output clock select input terminal
47 CKSEL1 I Output clock select input terminal
48 XMODE I Reset input terminal
I/O
* For latch-up countermeasure, set digital (DVDD) and analog (AVDD) power on/off in the same timing.
DISEL
DOUT
DIN0
DIN1
DIN2
DGND
DVDD
R
VIN
LPF
AVDD
AGND
AUDIO
EMPHA
XIN
XOUT
XMCK
DVDD
DGND
XSTATE
DATA0
LRCK
BCK
CKOUT
CE
CL
XSEL
MODE0
MODE1
DGND
DVDD
DOSEL0
DOSEL1
CKSEL0
CKSEL1
XMODE
DI
DO
ERROR
BPSYNC
AUTO
DGND
DVDD
VF/P3/C3
F2/P2/C2
F1/P1/C1
F0/P0/C0
CSFLAG
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16
AVR-2801/981
M35015-204SP Terminal Function
Pin No. Symbol Name I/O Function
1 OSC1 Osc. circuit ext. I External terminal for indication oscillator circuit. Standard OSC. freq. is approx. 7MHz.
2 OSC2 terminal. O With this OSC. freq., decides horizontal indicatin and character width.
3 CS Chip select input I Chip select terminal and turns to “L” when transfer serial data.
Hysteresis input. Pull up resistor is built-in.
4 SCK Serial clock input I Takes in serial data of SIN at SCK rise when CS terminal is in “L”.
Hysteresis input. Pull up rersist is built-in.
5 SIN Serial data input I Serial input of register for indication control and data, and address for indication data
memory. Hysteresis input. Pull up rersistor is built-in.
6 AC Auto-clear input I Resets internal circuit of IC at “L” mode.
Hysteresi input. Pull up resistor is built-in.
7V
DD2 Power supply Power supply terminal of analog system. Connect to +5V.
8CVIDEO
Combined
video output OOutput terminal of combined video signal. Outputs 2Vp-p combined signal. Character
output, etc. Overlap CVIN signal and outputs at superimpose.
9 LECHA Character level
input IInput terminal deciding character output level in combined video signal. color of character
is white.
10 CVIN Combined video
input IInput terminal of external combined video signal.
Character output etc. overlap this external combined video signal.
11 Vss Ground Ground terminal. Connect to GND.
12 P0 Output port p0 O General output or character background signal BL NK1* output is switchable.
Polarity can be selected at ROM mask.
13 P1 Output port P1 O General output or character background signal CO1* output is switchable.
Polarity can be selected at ROM mask.
14 P2 Output port P2 O General output or character background signal BLNK2* output is switchable.
Polarity can be selected at ROM mask.
15 P3 Output port P3 O General output or character background signal CO2* output is switchable.
Polarity can be selected at ROM mask.
16 OSCOUT O Terminal for external use of sync signal OSC. circuit. Use the freq.: 14.32MHz at NTSC
17 OSCIN I system, 17.73MHz at PAL. system, 14.30MHz at MPAL system.
18 HOR* Horizontal sync
signal IInputs horizontal sync signal.
Hysteresis input.
19 VERT* Vertical sync
signal Input vertical sync signal. Hysteresis input. Polarity can be selected at ROM mask.
20 VDD1 Power supply I Power supply terminal of digital system. Connect to +5V.
Ext. terminal
for sync sig.
OSC. Circuit
M35015-204SP (RE: IC308)
1
20
10
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15
16
17
18
19
20
OSC1
OSC2
CS
SCK
SIN
AC
V
DD2
CVIDEO
LECHA
CVIN
V
DD1
VERT*
HOR*
OSCIN
OSCOUT
P3
P2
P1
P0
Vss
CS
SCK
SIN
V
DD1
20
AC
Vss
V
DD2
P1
P0
CVIN
LECHA
CVIDEO
OSCOUT
OSCIN
HOR*VERT*OSC2OSC1
INPUT
CONTROL
CIRCUIT
INDICATION
OSCILLATOR
DATA
CONTROL
CIRCUIT
ADDRESS
CONTROL
CIRCUIT TIMING
GENERATOR
INDICATION
CONTROL
REGISTER
INDICATION RAM
INDICATION CHARACTER ROM
BLINKING CIRCUIT
SHIFT REGISTER
INDICATION
CONTROL CIRCUIT
READ OUT ADDRESS
CONTROL CIRCUIT
IINDICATION LOCATION
DETECTION CIRCUIT
H COUNTER
SYNC SIGNAL
SWITCHING CIRCUIT
SYNC SIGNAL DIS-
CRIMINATING CIRCUIT
OSC CIRCUIT
FOR SYNC SIGNAL
GENERATION
TIMING
GENERATOR
NTSC
VIDEO OUTPUT
CIRCUIT
6
11
5
4
3
7
1 2 19 18
17
16
8
9
10
12
13
P2
14
P3
15
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0
9
9
2
8
9
4
2
9
8
T
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1
3
9
4
2
2
9
6
5
1
3
9
9
2
8
9
4
2
9
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0
5
1
5
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17
AVR-2801/981
1
2
34
56
7
8
9
10
11
33
32
31
30
29
282726252423
34
35
36
37
38
39
40
41
42
43
44
17
16
15
14
13
12
18 19 20 21 22
A1,SCDIN
RD,R/W,EMOE,GPIO11
WR,DS,EMWR,GPIO10
XMT958
DGND1
VD1
MCLK
SCLK
LRCLK
AUDATA0
AUDATA1
AUDATA2
DC
DD
RESET
AGND
VA
FILT1
FILT2
CLKSEL
CLKIN
CMPREQ,LRCLKN2
CS
SCDIO,SCDOUT,PSEL,GPIO9
ABOOT,INTREQ
EXTMEM,GPIO8
SDATAN1
VD3
DGND3
SCLKN1,STCCLK2
LRCLKN1
CMPDAT,SDATAN2
CMPCLK,SCLKN2
A0,SCCLK
DATA7,EMAD7,GPIO7
DATA6,EMAD6,GPIO6
DATA5,EMAD5,GPIO5
DATA4,EMAD4,GPIO4
VD2
DGND2
DATA3,EMAD3,GPIO3
DATA2,EMAD2,GPIO2
DATA1,EMAD1,GPIO1
DATA0,EMAD0,GPIO0
1 VD1 Digital positive supply
2 DGND1 Digital supply ground
3 XMT958 SPDIF transmitter output
4 WR, DS, EMWR, GPIO10
Host write strobe or host data strobe or external memory write enable or general purpose input & output number10
5 RD, R/W, EMOE, GPIO11 Host parallel output enable or host parallel R/W or external memory outout enable or general
purpose input & output number11
6 A1, SCDIN Host adddress bit one or SPI serial control data input
7 A0, SCCLK Host parallel address bit zero or serial control port clock
8 DATA7, EMAD7, GPIO7
9 DATA6, EMAD6, GPIO6
10 DATA5, EMAD5, GPIO5
11 DATA4, EMAD4, GPIO4
12 VD2 Digital positive supply
13 DGND2 Digital supply ground
14 DATA3, EMAD3, GPIO3
15 DATA2, EMAD2, GPIO2
16 DATA1, EMAD1, GPIO1
17 DATA0, EMAD0, GPIO0
18 CS Host parallel chip select, host serial SPI chip select
19
SCDIO, SCDOUT, PSEL, GPIO9
Serial control port data input and output, parallel port type select
20 INTREQ, ABOOT Control port interrupt request, automatic boot enable
21 EXTMEM, GPIO8 External memory chip select or general purpose input & output number 8
22 SDATAN1 PCM audio data input number one
23 VD3 Digital positive supply
24 DGND3 Digital supply ground
25 SCLKN1, STCCLK2 PCM audio input bit clock
26 LRCLKN1 PCM audio input sample rate clock
27 CMPDAT,SDATAN2 PCM audio data input number two
28 CMPCLK, SCLKN2 PCM audio input bit clock
29 CMPREQ, LRCLKN2 PCM audio input sample rate clock
30 CLKIN Master clock input
31 CLKSEL DSP clock select
32 FILT2 Phase locked loop filter
33 FILT1 Phase-locked loop filter
34 VA Analog positive supply
35 AGND Analog supply ground
36 RESET Master reset input
37 DD Reserved
38 DC Reserved
39 AUDATA2 Digital audio output 2
40 AUDATA1 Digital audio output 1
41 AUDATA0 Digital audio output 0
42 LRCLK Audio output sample rate clock
43 SCLK Audio output bit clock
44 MCLK Audio master clock
CS492604-CLR
(AU: IC814)
Pin Name Function
CS492604-CLR Terminal Function
Pin
No.
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2
8
9
4
2
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8
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3
9
4
2
2
9
6
5
1
3
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9
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8
9
4
2
9
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5
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18
AVR-2801/981
Symbol
V
DD
Vss
Power terminal +5V
Power terminal GND
V
FL
Power terminal FL drive
DI
CL
CE
Serial data transfer terminal
DI: Data
CL: Clock
CE: Chip enable
OSCI
OSCO External CR connecting terminal
RES System reset terminal
AM1~AM35
AA1~AA3 Anode output terminal
AA4/G16
AA5/G15
AA6/G14
AA7/G13
AA8/G12
Anode/Grid output terminal
G1~G11 Grid output terminal
TEST LSI test terminal
Function
64
49
48 33
32
17
161
AM 1
AM 2
AM 3
AM 4
AM 5
AM 6
AM 7
AM 8
AM 9
AM 10
AM 11
AM 12
AM 13
AM 14
AM 15
AM 16
AM 17
AM 18
AM 19
AM 20
AM 21
AM 22
AM 23
AM 24
AM 25
AM 26
AM 27
AM 28
AM 29
AM 30
AM 31
AM 32
G7
G8
G9
G10
G11
AA8/G12
AA7/G13
AA6/G14
AA5/G15
AA4/G16
AA3
AA2
AA1
AM35
AM34
AM33
DI
CL
CE
RES
V
DD
OSCI
OSCO
Vss
TEST
V
FL
G1
G2
G3
G4
G5
G6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DGND
MCLK
CLATCH
CCLK
CDATA
384/256
X2MCLK
ZEROR
DEEMP
96/48
AGND
OUTR+
OUTR-
FILTR
DVDD
SDATA
BCLK
L/RCLK
PD/RST
MUTE
ZEROL
IDPM0
IDPM1
FILTB
AVDD
OUTL+
OUTL-
AGND
AD1854
LC75721E (EX: IC101)
AD1854 (AU: IC701, 702, 703)
Pin
2 MCLK Master Clock Input.
3 CLATCH Latch input for control data.
4 CCLK Control clock input for control data.
5 CDATA Serial control input.
6 384/256 Selects the master clock mode.
7 X2MCLK Selects internal clock doubler (LO) or internal clock=MCLK (HI).
8 ZEROR Right Channel Zero Flag Output.
9 DEEMP De-Emphasis.
10 96/48 Selects 48 kHz (LO) or 96 kHz Sample Frequency Control.
11,15 AGND Analog Ground.
12 OUTR+ Right Channel Positive line level analog output.
13 OUTR- Right Channel Negative line level analog output.
14 FILTR Voltage Reference Filter Capacitor Connection.
16 OUTL- Left Channel Negative line level analog output.
17 OUTL+ Left Channel Positive line level analog output.
18 AVDD Analog Power supply.
19 FILTB Filter Capacitor connection.
20 IDPM1 Input serial data port mode control one.
21 IDPM0 Input serial data port mode control zero.
22 ZEROL Left Channel Zero Flag output.
23 MUTE Mute. Assert HI to mute both stereo analog outputs.
24 PD/RST Power-Down/Reset.
25 L/RCLK Left/Right clock input for input data.
26 BCLK Bit clock input for input data.
27 SDATA Serial input.
28 DVDD Digital Power Supply.
No. Name I/O Description
1 DGND Digital Ground.
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
O
O
O
O
O
I
O
O
I
I
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1
5
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9
2
8
9
4
2
9
8
T
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3
9
4
2
2
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6
5
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9
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19
AVR-2801/981
Terminal Function
No. Name I/O Function
1 AINR I Rch analog input pin
2 AINL I Lch analog input pin
3 VREF O Ref. V out pin
4 VCOM O Common V out pin
5 AGND Analog GND pin
6VA Analog power pin, +2.7~+5.5
7VD Digital power pin, +2.7~+5.5V
8 DGND Digital GND pin
9 SDTO O Serial data out pin, 2’s complement, MSB first out, at power down: L
10 LRCK I L/Rch clock pin
11 MCLK I Master clock input pin
12 SCLK I Serial data clock input pin, A/D data out at SCLK falling edge
13 PDN I Power down pin, L: Power down mode
14 DIF I Serial interface format pin (L: Firward, H: I2S)
15 TTL I Digital input level select pin, L: CMOS level, H: TTL level
16 TST I Test pin (internal pull-down)
TC9274N-011 (AU: IC107)
42
1
21
1
23456789
10 11 12 13 14 15 16 17 18 19
20
21
22
23
24
25
26
27
28
29
3031
32
33
34
35
36
37
3839
40
41
42
V
DD
V
SS
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
S17
S18
GND
CK
DATA
STB
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
S17
S18
18 bit Latch Circuit (Rch)
(Lch) Same as Rch
Level Shift + Shift Register Circuit
AK5353 (AU: IC813)
AINR
AINL
VREF
VCOM
AGND
VA
VD
DGND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
TST
TTL
DIF
PDN
SCLK
MCLK
LRCK
SDTO
16
1
8
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
QUAL
RDDA
V
REF
MUX
V
SS A
CIN
SCOUT
RDCL
T57
OSCO
OSCI
V
DD D
TEST
MODE
V
DD A
V
SS D
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
QUAL
RDDA
V
REF
MUX
V
DD A
V
SS A
CIN
SCOUT
MODE
TEST
V
SS D
V
DD D
OSCI
OSCO
T57
RDCL
Quality indication output.
RDS data output.
Multiplex signal input.
+5V power supply for analog part.
Ground for analog part (0V).
Subcarrier input to comparator.
Subcarrier ouput of reconstruction filter.
Oscillation mode/test control input.
Test enable input.
Ground for digital part (0V).
+5V power supply for digital part.
Oscillator input.
Oscillator output.
57kHz clock signal output.
RDS clock output.
Pin No. Symbol Function
SAA6579T Terminal Function
SAA6579T (CO: IC301)
Europe model only
Reference voltage output (0.5 V
DD A
).
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9
2
8
9
4
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9
8
T
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1
3
9
4
2
2
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6
5
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20
AVR-2801/981
16
1
8
STROBE 1
2
3
4
5
6
7
89
10
11
16
15
14
13
12
DATA
CLOCK
Q1
Q2
Q3
Q4
V
SS
VDD
OE
Q5
Q6
Q7
Q8
Q'
S
Q
S
1
2
3
4
5
6
7
8
9
10
11
13
14
12
15
16
28
27
26
25
24
23
22
21
20
19
18
17
V
DD
STB
DATA
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
GND
CK
Vss
1
28
14
TC9273N-004 (AU: IC108)
BU4094BF (CO: IC304, EX: IC103)
CO: IC304
Port Symbol Function
Port Symbol Function
EX: IC103
TC9273N Terminal Function
Pin No. Symbol Name Function Note
1Vss
-Power Terminal
13 GND Digital Ground
28 VDD +Power Terminal
Dual Power Use: VDD = 8.0~17 V Single Power Use: VDD = 8.0~18V
GND = 0V Vss = GND = 0V
Vss = -8.0~17V
¾
2~12
17~27 S1~11 I/O Terminal Input terminal of analog switch. ¾
14 CK Clock Input Clock input for data transfer.
15 DATA Data Input Serial input for switch setting.
16 STB Strobe Input Strobe input for data writing.
Low level
Border Input
Terminal
Q7 FRONT SP-A LED
Q8
Q6
Q5
Q4
Q3
Q2
Q1 LOCK LED
DOLBY DIGITAL LED
dts LED
AUTO LED
DTS LED
PCM LED
FRONT SP-B LED
"FRONT SPEAKER A" LED drive output
"LOCK" LED drive output (H: Lock)
"DOLBY DIGITAL" LED drive output (H: D.Digital)
"dts" LED drive output (H: dts)
"AUTO" LED drive output (H: input mode "AUTO")
"DTS" LED drive output (H: input mode "DTS")
"PCM" LED drive output (H: input mode "PCM")
"FRONT SPEAKER B" LED drive output
Q7
Q8
Q6
Q5
Q4
Q3
Q2
Q1
G
A
B
C
D
E
F
Not Used
Video output switching (DVD/TV)
Video input switching
Video input switching
Video input switching
Video output switching
Video output switching
Video output switching (DVD/TV)
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8
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3
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4
2
2
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9
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Table of contents
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