Dialog DA14680 User manual

User Manual
DA1468x Range Extender
Daughterboard
UM-B-074
Abstract
This document describes the hardware system setup of a range extender daughterboard based on
the Dialog DA14680/681 Bluetooth® low energy SoC and the Skyworks SKY66112-11 Front End
Module. Target hardware: DA1468x/DA1510x_db_aQFN60 –Board Number: 224-23-D. Target
silicon: DA14680/681.

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Contents
Abstract................................................................................................................................................ 1
Contents............................................................................................................................................... 2
Figures.................................................................................................................................................. 3
Tables ................................................................................................................................................... 4
1Terms and Definitions................................................................................................................... 5
2References..................................................................................................................................... 5
3Introduction.................................................................................................................................... 6
4System Overview........................................................................................................................... 7
4.1 Features................................................................................................................................ 7
4.2 System Description............................................................................................................... 8
4.3 System Interface................................................................................................................... 8
5Power............................................................................................................................................ 11
6Bluetooth Low Energy SoC........................................................................................................ 12
7RF Front End................................................................................................................................ 14
7.1.1 Control Signals .................................................................................................... 14
7.1.2 GPIO Setup ......................................................................................................... 16
7.1.3 Power Amplifier.................................................................................................... 17
7.1.3.1 Power Modes................................................................................... 19
7.1.3.2 Power Supply................................................................................... 20
7.1.4 Transmit (TX) Path .............................................................................................. 20
7.1.5 Receive (RX) Path............................................................................................... 21
7.1.6 Filtering (Optional) ............................................................................................... 21
7.1.7 Antenna................................................................................................................ 22
7.1.8 Resistive Attenuator (Optional)............................................................................ 23
8Crystals ........................................................................................................................................ 24
9QSPI Flash Memory..................................................................................................................... 24
10 TX Output Power Control Circuit............................................................................................... 24
11 Reference Design Pin Assignment............................................................................................ 25
12 Development Mode - Peripheral Pin Mapping.......................................................................... 27
13 PCB Assembly............................................................................................................................. 28
13.1 DA14681 Range Extender Schematic ................................................................................ 29
13.2 SKY66112-11 Front End Module Schematic...................................................................... 30
13.3 Bill of Materials.................................................................................................................... 31
14 Application Software Guide: ble_external_host ...................................................................... 33
15 BLE Measurements..................................................................................................................... 37
15.1 Basic Performance Measurements..................................................................................... 37
15.1.1 Receiver Sensitivity ............................................................................................. 38
15.1.1.1 Test Description............................................................................... 38
15.1.1.2 Test Setup ....................................................................................... 38
15.1.1.3 Test Results..................................................................................... 38
15.1.2 Transmitter Output Power.................................................................................... 40
15.1.2.1 Test Description............................................................................... 40

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15.1.2.2 Test Setup ....................................................................................... 40
15.1.2.3 Test Results..................................................................................... 40
15.1.3 Current Consumption........................................................................................... 41
15.1.3.1 Test Setup ....................................................................................... 41
15.1.3.2 Advertising Mode............................................................................. 41
15.1.3.3 Connection Mode............................................................................. 42
15.1.3.4 Extended Sleep Mode ..................................................................... 43
15.2 BLE FCC Measurements.................................................................................................... 44
15.2.1 Maximum Output Power and Antenna Gain (Transmitter).................................. 45
15.2.1.1 Test Specification ............................................................................ 45
15.2.1.2 Test Setup ....................................................................................... 45
15.2.1.3 Test Results..................................................................................... 45
15.2.2 Emission Limitations Conducted (Transmitter).................................................... 47
15.2.2.1 Test Specification ............................................................................ 47
15.2.2.2 Test Setup ....................................................................................... 47
15.2.2.3 Test Results..................................................................................... 47
15.2.3 Band Edge Emissions Compliance (Transmitter)................................................ 50
15.2.3.1 Test Specification ............................................................................ 50
15.2.3.2 Test Setup ....................................................................................... 50
15.2.3.3 Test Results..................................................................................... 50
15.2.4 Emission Limitations Radiated (Transmitter)....................................................... 52
15.2.4.1 Test Specification ............................................................................ 52
15.2.4.2 Test Setup ....................................................................................... 52
15.2.4.3 Test Results..................................................................................... 52
Appendix A Application Software Guide: ble_adv_demo............................................................. 55
Revision History ................................................................................................................................ 59
Figures
Figure 1: PCB of the DA14680/681 Range Extender (224-23-D)......................................................... 6
Figure 2: Block Diagram of Range Extender (224-23-D)...................................................................... 8
Figure 3: Range Extender (224-23-D) on a DA1468x Dev.Kit PRO Motherboard................................ 9
Figure 4: Layout of the Range Extender Daughterboard ...................................................................... 9
Figure 5: DA14680/681 Range Extender Connected to a Communication Interface Board (CIB) ..... 10
Figure 6: SW1 Position for Each Power Scheme................................................................................ 11
Figure 7: DA14681 Basic System with External QSPI Flash Memory - overview............................... 13
Figure 8: RF Front End Signal Paths .................................................................................................. 14
Figure 9: SKY66112-11 Control Signal Timing ................................................................................... 15
Figure 10: DCF Signal Programming .................................................................................................. 16
Figure 11: SKY66112-11 Front End Module - overview...................................................................... 18
Figure 12: SKY66112-11 Gain vs. POUT, LPM2................................................................................... 19
Figure 13: Antenna Selection Using P4_0 or a R53 Pull-Down Resistor............................................ 22
Figure 14: SKY66112-11 Antenna Ports............................................................................................. 22
Figure 15: ANT1, Printed IFA Antenna and Matching Network (Z4 = 1.8 pF) .................................... 23
Figure 16: Resistive Attenuator Between DA14681 and SKY66112-11............................................. 23
Figure 17: Top View of PCBA.............................................................................................................. 28
Figure 18: Bottom View of PCBA ........................................................................................................ 28
Figure 19: Enable FEM Driver in custom_config_qspi.h..................................................................... 33
Figure 20: Flash Connection to V18P Power Rail in custom_config_qspi.h....................................... 33
Figure 21: Configure DA14681 Power Output Level at -2 dBm.......................................................... 34
Figure 22: Include hw_rf.h in main.c ................................................................................................... 34

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Figure 23: Set Build Configuration ...................................................................................................... 35
Figure 24: Building Project ble_external_host..................................................................................... 35
Figure 25: Configuration of correct product id DA14680/1-01............................................................. 36
Figure 26: Programming External Flash Using ble_external_host.bin................................................ 36
Figure 27: RX Sensitivity, Dirty Transmitter, Payload = 255, VCC2 = 1.2 V, PIN = -2 dBm................. 39
Figure 28: Nominal Average TX Power, VCC2_FEM = 1.2 V............................................................. 40
Figure 29: Peak Current During a BLE Advertising Event .................................................................. 41
Figure 30: Peak Current During a BLE Connection Event.................................................................. 42
Figure 31: Average Current During Extended Sleep Mode................................................................. 43
Figure 32: Maximum Output Power, CH00, VCC2 = 1.2 V................................................................. 45
Figure 33: Maximum Output Power, CH19, VCC2 = 1.2 V................................................................. 46
Figure 34: Maximum Output Power, CH39, VCC2 = 1.2 V................................................................. 46
Figure 35: Harmonics Level, Lowest Frequency, CH00...................................................................... 48
Figure 36: Harmonics Level, Middle Frequency, CH19 ...................................................................... 48
Figure 37: Harmonics Level, Highest Frequency, CH39..................................................................... 49
Figure 38: Lower Band Edge, CH00 ................................................................................................... 50
Figure 39: Upper Band Edge, CH39 ................................................................................................... 51
Figure 40: FCC Radiated Emission Limits .......................................................................................... 52
Figure 41: Emissions in Restricted Band RA 2.31 GHz to 2.39 GHz, CH00 ...................................... 53
Figure 42: Emissions in Restricted Band RB 2.4835 GHz to 2.5 GHz, CH39 .................................... 54
Figure 43: Enable FEM Driver in custom_config_qspi.h..................................................................... 55
Figure 44: Flash Connection to V18P Power Rail in custom_config_qspi.h....................................... 55
Figure 45: Configure DA14681 Power Output Level at -2 dBm.......................................................... 56
Figure 46: Include hw_rf.h in main.c ................................................................................................... 56
Figure 47: Set Build Configuration ...................................................................................................... 57
Figure 48: Building Project ble_adv..................................................................................................... 57
Figure 49: Programming External Flash Using ble_adv.bin................................................................ 58
Tables
Table 1: Electrical Characteristics......................................................................................................... 7
Table 2: Jumper/Switch Settings for Power Schemes of DA1468x Dev.Kit PRO Motherboard ......... 11
Table 3: Jumper/Switch Settings for Power Schemes of CIB Board .................................................. 11
Table 4: SKY66112-11 Control Signal Description ............................................................................. 15
Table 5: Truth Table for SKY66112-11 ............................................................................................... 15
Table 6: DCF Signal Configuration...................................................................................................... 16
Table 7: SKY66112-11 Control Signal and DCF Timer Configuration ................................................ 16
Table 8: SKY66112-11 TX Output Characteristics.............................................................................. 20
Table 9: SKY66112-11 TX RF Power Output (Note 1) ....................................................................... 21
Table 10: Default Configuration........................................................................................................... 21
Table 11: LNA Modes (Note 1)............................................................................................................ 21
Table 12: SKY66112-11 Antenna Select Logic................................................................................... 22
Table 13: Y1 16 MHz Crystal Characteristics...................................................................................... 24
Table 14: Y2 32 kHz Crystal Characteristics....................................................................................... 24
Table 15: DA14680/681 aQFN60 Pin Assignment.............................................................................. 25
Table 16: DA1468x Development/Test Mode Pin Mapping................................................................ 27
Table 17: BOM of DA14681 Range Extender ..................................................................................... 31
Table 18: RX Sensitivity for VCC2 = 1.2 V (Note 1)............................................................................ 38
Table 19: Nominal Average TX Power, VCC2 = 1.2 V (Note 1).......................................................... 40
Table 20 Typical Peak Current During Advertising Mode (Note 1) ..................................................... 41
Table 21: Typical Peak Current during Connection Mode (Note 1) .................................................... 42
Table 22: Typical Average Current in Extended Sleep Mode (Note 1)............................................... 43
Table 23: FCC 15.247 Compliance Pre-Tests Performed .................................................................. 44
Table 24: Maximum (Peak) Output Power (dBm), VCC2 = 1.2 V, CH00, CH19, CH39 ..................... 45
Table 25: Measured Reference Level................................................................................................. 47
Table 26: Conducted TX Harmonics at CH00, CH19, CH39 .............................................................. 47
Table 27: Emissions Levels in Restricted Areas RA and RB for CH00, CH19 and CH39.................. 53

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1 Terms and Definitions
BLE Bluetooth low energy
BOM Bill of Materials
CIB Communication Interface Board
CLI Command Line Interface
CSA5 (Bluetooth) Core Specification Addendum 5
DCF Dynamic Control Function
DCR Direct Current Resistance
DCXO Digitally Controlled Crystal Oscillator
DUT Device Under Test
EIRP Effective Isotropic Radiated Power
FEM Front End Module
FSM Finite State Machine
FW Firmware
HW Hardware
IFA Inverted-F Antenna
LNA Low Noise Amplifier
LPM Low Power Mode
LPF Low Pass Filter
PA Power Amplifier
PCBA Printed Circuit Board Assembled
PCB Printed Circuit Board
RF Radio Frequency
RFCU RF Control Unit
RMS Root Mean Square
RX receive(r)
SoC System on Chip
SWD Serial Wire Debug (interface)
TX transmit(ter)
n.a. not available
2 References
[1] Bluetooth Core Specification Addendum 5, 15 December 2015, Bluetooth SIG.
[2] UM-B-060, DA1468x/DA1510x Pro-Development Kit, User Manual, Dialog Semiconductor.
[3] DA14681 Low Power Bluetooth Smart 4.2 SoC, Datasheet, Dialog Semiconductor.
[4] UM-B-065, Bluetooth Smart Communication Interface Board, User Manual, Dialog
Semiconductor.
[5] SKY66112-11, Datasheet, Skyworks Inc.
[6] AN-B-061, DA1468x Application hardware design guidelines, Application Note, Dialog
Semiconductor.

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3 Introduction
The DA1468x/DA1510x_db_aqfn60_FEM_vD (224-23-D) is a reference design for extending the
range of a Bluetooth®low energy system based on the Dialog Semiconductor DA14681 SoC, where
enhanced RF transmitted power is presented. The DA14680/681 Range Extender daughterboard
serves as a reference design to potential customers requesting enhanced BLE RF Output Power up
to +13.5 dBm. Physically, the daughterboard consists of a 4-layer PCBA where the digital and power
interfaces of the DA14680/681 are accessible to the user.
This document presents the system, technical specifications, physical dimensions and test results.
Figure 1: PCB of the DA14680/681 Range Extender (224-23-D)

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4 System Overview
4.1 Features
■Highly integrated DA14680 or DA14681 Bluetooth low energy 4.2 SoC
■Can be used stand-alone or as a data pump on a system with an external processor
■Complies to Bluetooth v4.2, ETSI EN 300 328 and EN 300 440 Class 2 ( Europe), FCC CFR47
Part 15 ( US) and ARIB STD-T66 ( Japan)
■BLE transmit output power > +10 dBm, compliant with BLE v4.2 + CSA5 (see Ref. [1])
■Includes two crystal oscillators: 16 MHz (XTAL16M) and 32.738 kHz (XTAL32K)
■Access to processor via JTAG, SPI, UART or I2C interface
■18 general purpose I/Os with programmable voltage levels
■Operating voltage: 1.7 V to 4.75 V.
■On-board printed inverted F-type antenna (Figure 4)
■uFL connector for external antennas (Figure 4)
■RF connector for conducted measurements (Figure 4)
■BLE Radio transceiver
1
:
○+13.5 dBm transmit output power
○-95.5 dBm receiver sensitivity
■Supply current
2
:
○TX: max. current < 59 mA
○RX: max. current < 10 mA
○Extended - Sleep current: 4.5 A
■43 mm x 43 mm, 4 layer PCBA
■Operating temperature: –40 ºC to +85 ºC
■Test FW based on SDK 1.0.8
Table 1: Electrical Characteristics
Parameter3
Value
Average TX power
+13.5 dBm
RX sensitivity4
-95.5 dBm
Max. current consumption in TX mode
59 mA
Max. current consumption in RX mode
10 mA
Average current consumption during sleep mode
4.5 A
1
FCC part 15.247,15.209 compliance.
2
Normal operation using SDK ble_adv_demo application, TX output power +13.5 dBm.
3
Current measured using SDK 1.0.8 ble_adv_demo, configuration CHL = 0, LPM2 (FEM_VCC2 = 1.2 V),
RF_TX_PWR_REG = 2.
4
Dirty transmitter: ON, 1500 packets, payload PRBS9 length 255 bytes.

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4.2 System Description
The system consists of:
●DA14680 or DA14681 SoC in aQFN60 package (the main implementation and testing was done
with DA14681)
●Sky66112-11 RF Front End Module (SKY66112-11_203225G)
●QSPI Data Flash memory (dual package wlcsp-w25q80ew, soic8-W25Q80EWSNIG-default)
●Crystals 16 MHz (or 32 MHz) and 32.768 kHz
●Can be supplied from a Li-Poly battery
●Mating headers for connecting to a DA1468x PRO Motherboard
A system overview is shown in Figure 2.
Sky66112-11
16 MHz CRYSTAL 32.768 kHz CRYSTAL
DA1468x/1510x SoC
Matching
circuit
TX/RX path
Matching
circuit
CSD
CPS
CTX
CRX
CHL
ANT_SEL
1V8 1V8P
Qspi flash
V33
Resistive
attenuator (1) Low pass
filter (2)
Debug
interface
DA1468x/ 1510x
PMU
FEM control signals 6
VCC1
VCC2
VDD
V33_FEM (4)
Sky66112-11
TX Power control
circuit (3)
1V8
1V8P
VCC2_PA
1V8P VCC1_PA V33 VDD_PA
FEM_VCC2
FEM_VCC2
VCC1_PA
VDD_PA
VCC2_PA
Legend:
(1) Resistive attenuator application is possible.
(2) Low pass filter application is possible.
(3) RF TX Output Control Circuit.
(4) Only for DA1510x. Figure 2: Block Diagram of Range Extender (224-23-D)
4.3 System Interface
DA14680/681 Range Extender daughterboard is plugged on headers J1, J2 of DA1468x PRO
motherboard, as shown in Figure 3.
The PRO motherboard provides UART and JTAG (SWD) interfaces to the DA14680/681, current
measurement circuitry, as well as breakout headers (J3, J4) for the available GPIOs and general
purpose user peripherals. For more details on the functionality and specifications of the motherboard,
refer to user manual UM-B-060 (Ref. [2]).
The system is powered via the Debug USB port (USB2). The daughterboard can also be
independently programmed using an external battery connected to the on board Li-Poly battery
connector (see section 5for more details). The layout and main features of the daughterboard are
shown in Figure 4.

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Figure 3: Range Extender (224-23-D) on a DA1468x Dev.Kit PRO Motherboard
Figure 4: Layout of the Range Extender Daughterboard
Another option for programming the DA14680/681 Range Extender is to connect the daughterboard
to a CIB (Communication Interface Board) using a 2x10 cable as shown in Figure 5. The CIB

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provides UART and JTAG (SWD) interfaces to the DA14680/681 as well as power supply. If an
external Li-Poly battery is used to supply the daughterboard, jumper J16 on the CIB must be
removed. For more details on the Communication Interface Board, please refer to user manual UM-
B-065 (Ref. [4]).
Figure 5: DA14680/681 Range Extender Connected to a Communication Interface Board (CIB)

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5 Power
There are three options for powering the system when using DA1468x Dev.Kit PRO Motherboard:
●The PRO motherboard’s voltage regulator (VLDO, see Ref. [2]) –total current capability approx.
300 mA.
●A Li-Poly rechargeable battery on the PRO motherboard.
●A Li-Poly rechargeable battery on the daughterboard of DA14680/681 range extender.
The power source to the daughterboard is selectable with SW1 as shown in Figure 6.
Figure 6: SW1 Position for Each Power Scheme
The different configurations for each of the power schemes using the DA1468x Dev.Kit PRO
Motherboard are described in Table 2.
Table 2: Jumper/Switch Settings for Power Schemes of DA1468x Dev.Kit PRO Motherboard
Power Scheme
Indication
SW1
J9
USB1
USB2
Motherboard LDO
VBAT
Left
2-3
-
Power + debug
Li-Poly Battery mounted
on motherboard
External
battery
Left
1-2
Power + charge
debug
Li-Poly Battery mounted
on daughterboard
External
battery
Right
-
Power + charge
debug
When using the CIB board, there are two options for powering the system:
●Power supply coming from the USB of CIB.
●A Li-Poly rechargeable battery on the daughterboard of DA14680/681 range extender.
The different configurations for the power schemes using the CIB board are described in Table 3.
Table 3: Jumper/Switch Settings for Power Schemes of CIB Board
Power Scheme
Indication
SW1
J16
Power supply from CIB
VBAT or External Battery
Left or Right
connected
Li-Poly Battery mounted on
daughterboard
External battery
Right
not connected

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6 Bluetooth Low Energy SoC
The DA14680/681 is a flexible System-on-Chip for Bluetooth®low energy applications, combining an
application processor, memories, cryptography engine, power management unit, digital and analog
peripherals and a Bluetooth low energy MAC engine and radio transceiver. An overview of the basic
system is shown in Figure 7.
The DA14680/681 is based on an ARM®Cortex®-M0 CPU delivering up to 84 DMIPS and provides a
flexible memory architecture, enabling code execution from embedded memory (RAM, ROM) or non-
volatile memory (OTP or external Quad-SPI Flash). The DA14680 incorporates a QSPI Data Flash
memory in the package, whereas the DA14681 requires an external QSPI Data Flash.
The advanced power management unit of the DA14681 enables it to run from primary and secondary
batteries, as well as provide power to external devices. The on-chip charger and state-of-charge fuel
gauge allow the DA14680/681 to natively charge rechargeable batteries over USB.
An on-chip PLL enables on-the-fly tuning of the system clock between 16 MHz and 96 MHz to meet
high processing requirements. The system runs at 32 kHz LP clock during low power sleep modes or
it goes to clock less deep sleep mode to save power.
The DA14680/681 SoC power management subsystem consists of:
●VBUS: Is the battery charger input as well as the USB bus voltage. A decoupling capacitor equal
or less than 4.7 F is placed close to VBUS pin.
●VBAT1: An external battery is connected on this pin. A 1 F decoupling capacitor (C10) is
required close to the pin (0402 package, 6.3 V). Voltage range for VBAT1 is 1.7 V to 4.75 V.
●VBAT2: Is the input of the SIMO DC-DC converter. It is shorted externally with VBAT1. A 1 F
decoupling capacitor (C8) is required next to the pin (0402 package, 6.3 V).
●V33: Output voltage rail, 3.3 V. A decoupling ceramic capacitor of 4.7 F (C3), (0402 package,
6.3 V) is placed. V33 cannot be turned off.
●SIMO DC-DC converter outputs are: V18, V18P, V12, V14. The inductor needed for DC-DC
operation is placed externally. A low DCR inductor (L1) of 470 nH, 0805 is connected on pins
LX/LY.
●V18 and V18P: These voltage rails can deliver power to external devices, even when the system
is in sleep mode. Decoupling ceramic capacitors (C4, C5) of 10 F (0603 package, 16 V), are
placed as close as possible to the V18 and V18P pins. The current delivery capability of the V18
and V18P power rails is 75 mA in active mode, while it is 2 mA in sleep mode.
●V12: Power rail supplies the digital core of the DA14680/681 and delivers up to 50 mA at 1.2 V
when in active mode. A 4.7 F decoupling capacitor (C6) is used (0402 package, 6.3 V).
●V14: Power rail delivers up to 20 mA at 1.4 V and should not be used to supply external devices.
A 4.7 F decoupling capacitor (C7) is placed close to the V14 pin (0402 package, 6.3 V).
●V14_RF: Input pin. It is shorted to V14 on the PCB layout. V14_RF powers the RF circuits via a
number of dedicated internal LDOs. A 4.7 F decoupling capacitor (C9) is placed as close to the
V14_RF pin as possible.
●VDDIO: Flash interface supply voltage. It is connected to the same power rail as the Flash
memory. A 1 F decoupling capacitor (C1), is added (0402 package, 6.3 V).
The DA14680/681 radio transceiver characteristics are:
●2.4 GHz CMOS transceiver with integrated balun
●50 matched single wire antenna interface
●Transmit output power in the range of 0 dBm to -4 dBm
●-93 dBm BLE receiver sensitivity
●Supply current at VBAT1 (3 V) for the RF part:
○TX: 3.4 mA
○RX: 3.7 mA

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Figure 7: DA14681 Basic System with External QSPI Flash Memory - overview

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7 RF Front End
This part of the design implements the amplification of the RF transmitted signal while the transmitted
harmonics as well as the TX spurious emissions remain within the FCC/ETSI specification. The RF
Front End Module (FEM) used is SKY66112-11 of Skyworks (Ref. [5]).
The operation of RF front end is controlled by the DA14680/681 SoC using control signals. During
the operation of the FEM there are three available RF paths:
●TX path through the amplifier
●RX path through the LNA of the PA
●TX/RX bypass path, where both PA/LNA are bypassed during transmission and reception.
The amplifier path is enabled during transmission. The RF signal passes through the PA and the RF
matching network and is transmitted through one of the two available antenna ports. A resistive
attenuator and a low pass filter can also be included in the amplifier path if needed. In the bypass
path, the RF signal received at the antenna is driven directly to the BLE transceiver. In the RX LNA
path the received signal passes through SKY66112-11 LNA, which has a receive gain of 11 dB.
ANT1
2.4 GHz printed antenna
Matching
circuit
TX amplifier path
BLE 2402..2480 MHz
CSD
CPS
CTX
CRX
CHL
ANT_SEL
Resistive
attenuator (1)
Low pass
filter (2)
Matching
circuit
ANT2
uFL connector
DA14681
aQFN60
BLE SoC
TX/RX bypass path
RX LNA path
SKY66112-11
Legend:
(1) Resistive attenuator application is possible.
(2) Low pass filter application is possible.
Figure 8: RF Front End Signal Paths
The amplifier has three different voltage rails (VCC1, VCC2 and VDD). The TX power output is tuned
by modifying the VCC2 supply rail voltage as well as the power level at its input. The basic power
levels for the PA are:
●TX POUT = +21 dBm @ VCC2 = 3.0 V, PIN = -1 dBm
●TX POUT = +16 dBm @ VCC2 = 1.8 V, PIN = -3 dBm
●TX POUT = +13 dBm @ VCC2 = 1.2 V, PIN = -3 dBm
7.1.1 Control Signals
The SKY66112-11 has a number of digital control signals that need to be set/reset by the
DA14680/681. They are currently being controlled by Dynamic Control Function (DCF) signals of the
DA14680/681 RF control unit. The DCF signals are normal GPIOs controlled by timers within the
radio. Their functionality is explained in Table 4, while their timing is shown in Figure 9.
The digital control signals are compatible with 1.6 V to 3.6 V CMOS levels and are supplied from the
VDD voltage rail.

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Table 4: SKY66112-11 Control Signal Description
Control Signal
Function
Mode of Operation
CSD
FEM Enable signal
0: all off (sleep mode)
1: FEM enabled
CRX
RX enable
0: RX off
1: RX on with LNA
CPS
Bypass mode
0: Bypass disabled
1: Bypass mode for TX or RX
CTX
TX Enable
0: TX off
1: TX on (Low or High power)
CHL
TX Power level
0: TX Low power level
1: TX High power level
ANT_SEL
Antenna select signal
0: ANT1
1: ANT2
Table 5: Truth Table for SKY66112-11
Mode
Description
CSD
CPS
CRX
CTX
CHL
0
All off (sleep mode) (Note 1)
0
X
X
X
X
1
Receive LNA mode
1
0
1
0
X
2
Transmit high power mode
1
0
X
1
1
3
Transmit low power mode
1
0
X
1
0
4
Receive Bypass mode
1
1
1
0
X
5
Transmit Bypass mode
1
1
X
1
X
6
All off (sleep mode)
1
X
0
0
X
Note 1 All controls must be at logic 0 to achieve the specified sleep current.
TX/RX_EN RF
CTX 47 us
CRX
CSD
CPS
CHL
20 us1 us
20 us
20 us
20 us
47 us
47 us
47 us
Figure 9: SKY66112-11 Control Signal Timing

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The control signal timing aims to keep the signals at logic 0 as long as possible to achieve better
power results. This can be achieved by assigning the control signals to DCF timers (see Table 7)
Decoding of the signals results in the following signal description:
●CTX: Enable any TX related operation
●CRX: Enable any RX related operation
●CHL: Define TX High (1) or Low (0) power mode
●CPS: Enable bypass TX/RX mode
●CSD: Enable FEM
7.1.2 GPIO Setup
The RF Control Unit (RFCU) of DA14680/681 provides the capability of controlling five signals which
can be used for controlling the SKY66112-11. The DCFs can be output on any GPIO by using PID
numbers 55 to 59. The five DCF signals can be extracted from the RFCU to any pin by programming
the PID values in the Pxx_MODE_REG registers, as follows:
Table 6: DCF Signal Configuration
Function
PORT0_DCF
PORT1_DCF
PORT2_DCF
PORT3_DCF
PORT4_DCF
PID
55
56
57
58
59
Figure 10: DCF Signal Programming
Table 7: SKY66112-11 Control Signal and DCF Timer Configuration
Mode
DA1468x GPIO
SKY66112-11
Comments
FEM enable
P4_3
CSD
GPIO or DCF timer 29 (PORT2_DCF)
TX enable
P4_5
CTX
DCF timer 27 (PORT0_DCF)
PA High Gain
P4_4
CHL
GPIO or DCF timer 31 (PORT4_DCF)
RX enable
P4_2
CRX
DCF timer 28 (PORT1_DCF)

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Mode
DA1468x GPIO
SKY66112-11
Comments
PA or LNA Bypass
P4_6
CPS
GPIO or DCF timer 30 (PORT3_DCF)
This signal can be fixed at logic 0 or 1 through
a pull-down or pull-up resistor.
ANT_SEL
P4_0
ANT_SEL
GPIO
This signal can be fixed at logic 0 through a
pull-down resistor.
7.1.3 Power Amplifier
The SKY66112-11 is a fully integrated RF Front End Module (FEM) designed for Smart Energy
applications. The device provides PA, LNA, an integrated inter-stage matching and harmonic filter,
and digital controls compatible with 1.6 V to 3.6 V CMOS levels.
The RF blocks operate over a wide supply voltage range from 1.2 V to 3.6 V that allows the
SKY66112-11 to be used in battery powered applications over a wide spectrum of the battery
discharge curve. The basic characteristics for the SKY66112-11 are:
●Three voltage rails (VCC1, VCC2 and VDD)
●TX power output tuning thru power rail voltage modification
○TX POUT = +21 dBm @ VCC2 = 3.0 V / 115 mA, Pin = -1 dBm
○TX POUT = +16 dBm @ VCC2 = 1.8 V / 60 mA, Pin = -3 dBm
○TX POUT = +13 dBm @ VCC2 = 1.2 V / 45 mA, Pin = -3 dBm
●LNA with gain 11 dB
●Receive Noise Figure = 2 dB
●Bypass mode of operation (-2 dB)
●Two Antennas Ports
An overview of the SKY66112-11 Front End Module is shown in Figure 11.

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Figure 11: SKY66112-11 Front End Module - overview

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7.1.3.1 Power Modes
The SKY66112-11 FEM supports three different power modes:
●HPM1: High Power Mode 1, where VCC2 = 3.0 V, VCC1 = 1.8 V and VDD = 3.0 V @
POUT = +21 dBm, PIN = -1 dBm.
●LPM1: Low Power Mode 1, where VCC2 = 1.8 V, VCC1 = 1.8 V and VDD = 3.0 V @
POUT = +16 dBm, PIN = -3 dBm.
●LPM2: Low Power Mode 2, where VCC2 = 1.2 V, VCC1 = 1.8 V and VDD = 3.0 V @
POUT = +13 dBm, PIN = -3 dBm (see Figure 12).
In the current design due to FCC compliance
5
reasons, Low Power Mode 2 is used. VCC2 voltage
level is connected to V18 and it is configured to 1200 mV using a series resistor R73=16.5 . The
DA14680/681 TX output power is set to -2 dBm and it is programmed using RF_TX_PWR_REG
(0x500020C0).
Figure 12: SKY66112-11 Gain vs. POUT, LPM2
The use of a hardware resistive attenuator between DA14680/681 and SKY66112-11 may be
considered to provide an extra low RF input power range to SKY66112-11 when a lower TX output
power is needed (see Figure 8). Of course, addition of the resistive attenuator leads to a current
consumption increment for the same RF power output.
Given the lowest power level that DA14680/681 can provide at the input of the PA which is -4 dBm
and that the PA gain in bypass mode is -2 dB, the Range Extender can deliver a minimum output
power of -6 dBm and a maximum of +13.5 dBm.
5
Emission limitations in restricted area of 2483.5 MHz to 2500 MHz.

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7.1.3.2 Power Supply
The SKY66112-11 requires three different supply voltages:
●VCC1: Supplies the first stage of the PA as well as the LNA.
●VCC2: Supplies the second stage of the PA.
●VDD: Supplies the logic (switches, bias enable, etc.).
Table 8: SKY66112-11 TX Output Characteristics
Voltage
Rail
FEM
Pin
FEM Specification (V)
Comments
Min
Typ
Max
VCC1
16
1.7
1.8
3.3
VCC1 = 1.8 V, VCC2 = 3.0 V, ICC = 115 mA,
POUT = +21 dBm, PIN = -1 dBm
VCC1 = 1.8 V, VCC2 = 3.0 V , ICC = 90 mA,
POUT = +20 dBm, PIN = -2 dBm
VCC1 = 1.8 V, VCC2 = 1.8 V , ICC = 60 mA,
POUT = +16 dBm, PIN = -3 dBm
VCC1 = 1.8 V, VCC2 = 1.2 V, ICC = 45 mA,
POUT = +13 dBm, PIN = -3 dBm
VCC2
14
0.6
3.0
3.3
VDD
11
1.8
3.0
3.3
VDD is supplied by V33 of the DA14680/681.
VCC1 is connected to the V18P voltage rail of DA14680/681. Current consumption and voltage
regulation requirements must be taken under consideration. VCC1 supplies the LNA or the first stage
of the PA with a power consumption of 6 mA or 25 mA (max.) respectively. The V18P output must
present very low ripple and low noise. The V18P power rail has a driving current capability of 75 mA.
The VCC2 voltage level is critical, as it affects the RF PA output level. VCC2 supplies the second
stage of the PA and draws most of the TX current. VCC2 is connected to the V18 power rail
6
. The
VCC2 voltage can be changed using a series resistor R73. The V18 power rail has a current driving
capability of 75 mA.
7.1.4 Transmit (TX) Path
The RF PA TX Power output level is defined primarily by the VCC2 voltage level and secondly by the
control signal settings.
The CPS signal is used to enable the bypass operating mode of the FEM. Enabling CPS provides a
direct path between antenna and DA14680/681 chip.
The CHL functionality is intended to be used to increase efficiency at the lower output power levels
by reducing the PA bias. It is not intended for power control. However at constant VCC2, toggling
CHL will increase/decrease POUT by 0.5 dB to 0.75 dB.
The TX power output is determined based on:
●VCC2 level which is connected to V18 via a series resistor R73.
●DA14680/681 TX power set using RF_TX_PWR_REG (0x500020C0). This register can be
programmed from 0 to 4 (0 dBm to -4 dBm).
●Resistive attenuator populated before or after the PA (optional).
6
This configuration differs from the DA1468x development kit. GPIOs configured to operate at 1.8 V are supplied from the
V18P rail while the ones configured to operate at 3.3 V are supplied from the V33 rail. This means that V18P could only be
used for VCC2 if there are no GPIOs configured to operate at 1.8 V. Therefore, instead of V18P the V18 power rail is used to
supply VCC2.