Dwin T5L ASIC Series User manual

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T5L_ASIC Development Guide
Version 2.0
2022/4/13

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Contents
1 Summary...........................................................................................................................................3
2 Hardware Description........................................................................................................................5
2.1 PIN Definition.................................................................................................................................5
2.2 Packaging Dimension ..................................................................................................................10
2.3 Basic Performance Parameters ...................................................................................................11
2.4 Notices for Hardware Design .......................................................................................................12
3 OS CPU..........................................................................................................................................13
3.1 Initial Configuration ......................................................................................................................14
3.2 Memory........................................................................................................................................15
3.2.1 Code Memory(64KBytes)..........................................................................................................15
3.2.2 Variable Memory(256KBytes)....................................................................................................16
3.2.3 Data Memory(32KBytes)...........................................................................................................18
3.2.4 Extended SFR Register ............................................................................................................19
3.3 Mathematical Operating Unit(MDU).............................................................................................20
3.4 Timer............................................................................................................................................22
3.5 Watchdog Timer(WDT)................................................................................................................24
3.6 IO.................................................................................................................................................25
3.7 UART............................................................................................................................................27
3.7.1 UART2......................................................................................................................................27
3.7.2 UART3......................................................................................................................................28
3.7.3 UART4......................................................................................................................................29
3.7.4 UART5.......................................................................................................................................30
3.8 CAN .............................................................................................................................................31
3.9 Interrupt System...........................................................................................................................33
3.9.1Interrupt Control SFR.................................................................................................................33
3.9.2 Interrupt Priority.........................................................................................................................34
3.10 T5L ASIC 8051 Instruction Set...................................................................................................30
4 Simulation Debug............................................................................................................................32
5 EK043 Evaluation Board.................................................................................................................34

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1 Summary
The T5L series ASIC is a single-chip and dual-core ASIC designed by DWIN technology co., ltd for
AIOT applications with low power consumption, high cost performance, GUI and highly integrated
application, including T5L1(low resolution) and T5L2(high resolution). Its main features are as follow:
(1) Mature and stable 8051 core which is the most widely used with the maximum operating
frequency of T5L is up to 250MHz, 1T(single instruction cycle)high speed operation.
(2) Separated GUI CPU core running DGUS II System:
➢ High-speed display memory, 2.4GB/S bandwidth, 24bit color display resolution supporting to
800*600(T5L1) or 1366*768(T5L2).
➢ 2D hardware acceleration, the decompression speed of JPEG is up to 200fps@1280*800, the
UI with animation and icons as its main feature is extremely cool and smooth.
➢ Images and icons stored in JPEG format. Adopt Low-cost 16Mbytes SPI Flash.
➢ Support CTP or RTP with adjustable sensitivity and maximum 400Hz touch frequency.
➢ High-quality speech compression storage and playback.
➢ 128Kbytes variable storage space for exchanging data with OS CPU core and memory
➢ 1-way 15bit 32Ksps PWM digital power amplifier driver loudspeaker to save power amplifier
cost and achieve high signal-to-noise ratio and sound quality restoration.
➢ Support DGUS development and simulation on PC. Support background remote upgrade.
(3) Separated CPU (OS CPU) core runs user 8051 code or DWIN OS system, user CPU omitted in
practical application.

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➢ Standard 8051 architecture and instruction set, 64Kbytes code space, 32Kbytes on-chip RAM.
➢ 64 bit integer mathematical operation unit(MDU), including 64bit MAC and 64 bit divider.
➢ Built-in software WDT, three 16bit Timers, 12 interrupt signals with the highest four interrupt
embedding.
➢ 28 IOs, 4-channel UARTs, 1-channel CAN, up to 8-channel 12-bit A/Ds and 2-channle 16-bit
PWM of adjustable resolution.
➢ Support IAP online simulation and debugging with unlimited number of breakpoints.
➢ Upgrade code online through DGUS system.
(4) 1Mbytes on-chip Flash with DWIN patent encryption technology ensure code and datasecurity.
(5) Reduces crystal requirements and PCB design challenges for a variety of inexpensive wide-
range tuned impedance crystal oscillators and PLLs.
(6) 3.3V IO voltage, adaptable to 1.8/2.5/3.3 various levels
(7) Support SD interface or UART1 download and configuration. Support SD card file reading and
rewriting.
(8) Support DWIN WiFi module to access to DWIN cloud directly, and easily development for
various cloud platform applications.
(9) Working temperature ranges from - 40℃to +85℃(Customizable IC for -55℃to 105℃
operating temperature range )
(10) With low power consumption and strong anti-interference ability, it can work steadily on the
double-sided PCB design, and easy to pass EMC/EMI test.
(11) 0.4mm ELQFP128 packaging with low processing difficulty and low cost.
(12) T5L ASIC + LCD + TP + UI design support for industry customers with cost-effective matching
program sales and comprehensive technical service support.

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2 Hardware Description
2.1 PIN Definition
T5L ASIC is packaged in ELQFP128 (16*16*1.5mm), and pins arrangement are shown below.
T5Lpin
CPU
PIN#
Definition
Function 1
Instructions
Function 2
Instructions
Function 3
Instructions
OS
119
TX4
UART4 data
sending
OS
120
RX4
UART4 data
receiving
OS
121
TX5
UART5 data
sending
OS
122
RX5
UART5 data
receiving
OS
123
P0.0
I/O port
OS
124
P0.1
I/O port
OS
125
P0.2
I/O port
CAN_TX
CAN data sending
OS
126
P0.3
I/O port
CAN_RX
CAN data receiving
OS
127
P0.4
I/O port
TX2
UART2 data sending
OS
128
P0.5
I/O port
RX2
UART2 data receiving
OS
1
P0.6
I/O port
TX3
UART3 data sending
OS
2
P0.7
I/O port
RX3
UART3 data receiving
OS
3
VDD
T5L1=1.25V
T5L2=1.2V
OS
4
VIO
3.3V

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OS
5
P1.0
I/O port
OS
6
P1.1
I/O port
OS
7
P1.2
I/O port
OS
8
P1.3
I/O port
OS
9
P1.4
I/O port
OS
10
P1.5
I/O port
OS
11
P1.6
I/O port
OS
12
P1.7
I/O port
OS
13
VDD
T5L1=1.25V
T5L2=1.2V
OS
14
VIO
3.3V
OS
15
P2.0
I/O port
OS
16
P2.1
I/O port
OS
17
P2.2
I/O port
OS
18
P2.3
I/O port
OS
19
P2.4
I/O port
OS
20
P2.5
I/O port
OS
21
P2.6
I/O port
OS
22
P2.7
I/O port
OS
23
VDD
T5L1=1.25V
T5L2=1.2V
OS
24
VIO
3.3V
OS
25
P3.0
I/O port
EX0
External interrupt 0 input
OS
26
P3.1
I/O port
EX1
External interrupt 1 input
OS
27
P3.2
I/O port
OS
28
P3.3
I/O port
29
GND
30
GND
31
GND
32
OS/GUI
0:GUI JMARK,
1=OS JMARK
33
/RST
System reset
input
34
JMARKS
PIN35#-PIN38# Select: 0=JMARK, 1=I/O port
GUI
35
P0.0
I/O port
TMS
JMARK interface
TCON_CS
LCD screen
TCON interface
GUI
36
P0.1
I/O port
TCK
JMARK interface
TCON_CLK
LCD screen
TCON interface
GUI
37
P0.2
I/O port
TDI
JMARK interface
TCON_DATA
LCD screen
TCON interface
GUI
38
P0.3
I/O port
TDO
JMARK interface
TCON_RST
LCD screen TCON
interface
GUI
39
P0.4
I/O port
TX1
UART1 data sending
GUI
40
P0.5
I/O port
RX1
UART1 data receiving
GUI
41
P0.6
I/O port
FSK_TX
FSK transceiver data sending

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GUI
42
P0.7
I/O port
FSK_RX
FSK transceiver data receiving
GUI
43
ADC0
AD input
RTP_X0
4-wire resistance touch screen
interface
GUI
44
ADC1
AD input
RTP_Y0
4-wire resistance touch screen
interface
GUI
45
ADC2
AD input
RTP_X1
4-wire resistance touch screen
interface
GUI
46
ADC3
AD input
RTP_Y1
4-wire resistance touch screen
interface
GUI
47
ADC4
AD input
IF_0.4
DC/DC 0.4V voltage feedback
GUI
48
ADC5
AD input
VF_1.25
DC/DC 1.25V voltage feedback
GUI
49
ADC6
AD input
IF_0.4
GUI
50
ADC7
AD input
VF_1.25
GUI
51
AGND
AD GND
GUI
52
AVDD
AD power supply, 3.3V, close to 470pJ (C0G material) in parallel with 105 filter capacitor
GUI
53
VREF
AD reference power supply, up to AVDD+0.3V, close to 470pJ (C0G material) in parallel with 105 filter
capacitor
GUI
54
VDDPLL
T5L1=1.25V T5L2=1.2V, close to 470pJ (C0G material) in parallel with 105 filter capacitor
GUI
55
XIN
Crystal,10MHz-
12MHZ
CLK_IN
3.3V clock input
GUI
56
XOUT
Crystal
GUI
57
VDD
1.1V
GUI
58
VIO
3.3V
GUI
59
P1.0
I/O port
PWM0
16bit PWM output
GUI
60
P1.1
I/O port
PWM1
16bit PWM output
PWM_V
LCD screen
AVDD DC/DC
GUI
61
P1.2
I/O port
PWM2
16bit PWM output
PWM_I
LCD backlight
DC/DC
GUI
62
P1.3
I/O port
PWM3
16bit PWM output
BUZZ&SPK
Buzzer/speaker
drive
GUI
63
P1.4
I/O port
SDD0
SD card interface: data
SPI_D0
SPI Flash
interface: data
GUI
64
P1.5
I/O port
SDD1
SD card interface: data
SPI_D1
SPI Flash
interface: data
GUI
65
P1.6
I/O port
SDD2
SD card interface: data
SPI_D2
SPI Flash
interface: data
GUI
66
P1.7
I/O port
SDD3
SD card interface: data
SPI_D3
SPI Flash
interface: data
GUI
67
VDD
T5L1=1.25V
T5L2=1.2V
GUI
68
VIO
3.3V
GUI
69
P2.0
I/O port
SDCK
SD card interface: clock
PA_EN
Amplifier power
switch for speech
playback
GUI
70
P2.1
I/O port
SDCK
SD card interface: instructions

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GUI
71
P2.2
I/O port
SPI_CS
SPI Flash interface: chip selection
GUI
72
P2.3
I/O port
SPI_CLK
SPI Flash interface: clock
GUI
73
P2.4
I/O port
RTP_Y1
4-wire resistance touch screen
interface
CTP_SDA
Capacitance
touch screen
interface
GUI
74
P2.5
I/O port
RTP_X1
4-wire resistance touch screen
interface
CTP_INT
Capacitance
touch screen
interface
GUI
75
P2.6
I/O port
RTP_Y0
4-wire resistance touch screen
interface
CTP_SCL
Capacitance
touch screen
interface
GUI
76
P2.7
I/O port
RTP_X0
4-wire resistance touch screen
interface
CTP_RST
Capacitance
touch screen
interface
GUI
77
VDD
T5L1=1.25V
T5L2=1.2V
GUI
78
VIO
3.3V
GUI
79
P3.0
I/O port
CLK_OUT
System clock frequency division
output
GUI
80
P3.1
I/O port
FSK_TR
T/R switching signal for half-
duplex use of SFK transceiver
GUI
81
P3.2
I/O port
GUI
82
P3.3
I/O port
GUI
83
P3.4
I/O port
LCD_PCLK
LCD interface
GUI
84
P3.5
I/O port
LCD_DE
LCD interface
GUI
85
P3.6
I/O port
LCD_HS
LCD interface
GUI
86
P3.7
I/O port
LCD_VS
LCD interface
GUI
87
VDD
T5L1=1.25V
T5L2=1.2V
GUI
88
VIO
3.3V
GUI
89
P4.0
I/O port
LCD_B0
LCD interface
GUI
90
P4.1
I/O port
LCD_B1
LCD interface
GUI
91
P4.2
I/O port
LCD_B2
LCD interface
GUI
92
P4.3
I/O port
LCD_B3
LCD interface
GUI
93
P4.4
I/O port
LCD_B4
LCD interface
GUI
94
P4.5
I/O port
LCD_B5
LCD interface
GUI
95
P4.6
I/O port
LCD_B6
LCD interface
GUI
96
P4.7
I/O port
LCD_B7
LCD interface
GUI
97
VDD
T5L1=1.25V
T5L2=1.2V
GUI
98
VIO
3.3V
GUI
99
P5.0
I/O port
LCD_G0
LCD interface
GUI
100
P5.1
I/O port
LCD_G1
LCD interface
GUI
101
P5.2
I/O port
LCD_G2
LCD interface

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GUI
102
P5.3
I/O port
LCD_G3
LCD interface
GUI
103
P5.4
I/O port
LCD_G4
LCD interface
GUI
104
P5.5
I/O port
LCD_G5
LCD interface
GUI
105
P5.6
I/O port
LCD_G6
LCD interface
GUI
106
P5.7
I/O port
LCD_G7
LCD interface
GUI
107
VDD
T5L1=1.25V
T5L2=1.2V
GUI
108
VIO
3.3V
GUI
109
P6.0
I/O port
LCD_R0
LCD interface
GUI
110
P6.1
I/O port
LCD_R1
LCD interface
GUI
111
P6.2
I/O port
LCD_R2
LCD interface
GUI
112
P6.3
I/O port
LCD_R3
LCD interface
GUI
113
P6.4
I/O port
LCD_R4
LCD interface
GUI
114
P6.5
I/O port
LCD_R5
LCD interface
GUI
115
P6.6
I/O port
LCD_R6
LCD interface
GUI
116
P6.7
I/O port
LCD_R7
LCD interface
GUI
117
VDD
T5L1=1.25V
T5L2=1.2V
GUI
118
VIO
3.3V
Note that the pads on the bottom of the IC must be reliably grounded, otherwise the performance of the
IC will be affected.

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2.2 Packaging Dimension
For PCB design, please refer to the DWIN official device packaging and reference design.

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2.3 Basic Performance Parameters
Parameter
Unit
Minimum
Typical value
Maximum
Instructions
CPU core voltage
V
1.10
1.20
1.30
T5L2
V
1.20
1.25
1.35
T5L1
CPU core current
mA
100
Dual-core 200MHz full speed
operation
IO voltage (VIO)
V
1.8
3.3
3.6
5V TTL/CMOS level input
requires voltage division or
clamp protection
AD operating voltage(VADD)
V
1.8
3.3
3.6
AD reference voltage (Vref)
V
VADD+0.3
AD input voltage
V
Vref+0.3
IO high level output
amplitude(VOH)
V
3.0
VIO=3.3V,IO load current 8mA
IO low level 1utput
amplitude(Vol)
V
0.3
VIO=3.3V,IO load current 8mA
IO high level output current
mA
-10
VIO=3.3V, VOH=3V
IO low level output current
mA
10
VIO=3.3V, VOL=0.3V
IO port turnover speed
MHz
100
IO high level recognition
voltage(VIH)
V
1.6
IO low level recognition
voltage(VIL)
V
0.6
External crystal frequency
MHz
10.0
11.0592
12.0
CPU main frequency (CPU_CLK)
MHz
206.4384
Corresponding to 11.0592MHz
crystal, CPU main frequency =
crystal frequency* 56/3.
350MHz version code can be
customized.
Working temperature
℃
-40
+85
Storage temperature
℃
-55
+105
ESD protection capability
KV
2
HBM

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2.4 Notices for Hardware Design
(1) The core power voltage must be stable, otherwise it will lead to abnormal CPU operation.
(2) Reset is recommended to be handled by a low-level reset IC like SGM809S, instead of a simple
RC reset circuit. The T5L has a built-in watchdog (WDT) for each CPU core, so there is no need for
an external WDT IC.
(3) When designing for dual panel applications, connect a 470pF in parallel with 104 (or 105) filter
capacitors as close as possible to the IC supply pins to reduce noise emission.
(4) When IO input signal is over 0.3V of VIO voltage, IO must be protected by voltage divider or
clamp, otherwise it may cause abnormal signal or damage IC.
(5) All IO ports are floating input when they are configured as input mode, without internal pull-up or
pull-down.
All IO ports are in the input mode during the reset. If they are output, they can be pulled down or
pulled up externally to ensure that the reset has a definite level.
(6) The 4-bit bus speed of T5L and external SPI Flash is 100MHz, and thus The wiring should be as
close as possible and 470pF must be arranged on the power pins of the SPI Flash in parallel with
105 filter capacitor.

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3 OS CPU
The T5L OS CPU adopt the 8051 kernel, which is the most widely used in industry and has longest
history in mass production.
On the basis of the good real-time performance, fast IO rate and stable reliability of 8051, DWIN has
significantly improved the 8051 memory by optimizing the code processing, expanding the SFR bus
and enhancing the hardware math processor.
For applications mainly for computing and data processing, users can also run the OS CPU and
conduct secondary application development on the DWIN OS platform.
Refer to "DWIN OS Development Guide" for specific development methods.

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3.1 Initial Configuration
When the 8051 kernel is powered on, the special function register (SFR) in the following table must
be initializedcorrectly.
SFR name
Address
Initial values
Instructions
CKON
0X8E
0X00
CPU runs in 1T mode
T2CON
0XC8
0X70
Configure extended interrupt system;
configure timer T2 to run inautoload mode
DPC
0X93
0X00 or 0x01
The change mode of DPTR after MOVX instruction operation must
be configured to 0x00 if developed with C51.
0x00: No change. 0x01: DPTR=DPTR+1. 0x03: DPTR=DPTR-1.
PAGESEL
0X94
0X01
64KB code space
D_PAGESEL
0X95
0X02
32KB RAM space accessed by MOVX: 0x8000-0xFFFF
MUX_SEL
0XC9
0x60 orconfiguration
according to
application needs
Peripheral multiplexing selection:
.7 1 = CAN interface leads to P0.2, P0.3, 0 = CAN interface does
notlead out, and it works as an IO interface;
.6 1 = UART2 interface leads to P0.4, P0.5, 0 = UART2 interface
doesnot lead out, and it works as an IO interface;
.5 1 = UART3 interface leads to P 0.6, P 0.7, 0 = UART3 interface
doesnot lead out, and it works as an IO interface;
.4-.2 Reserved;
.1 WDT control 1=open 0=close;
.0 WDT feed dog, 1=feed the dog one time(The WDT count
becomes zero, and the watchdog's overflowing time is one
second. );
PORTDRV
0XF9
0x01
Driver capability configuration of IO port output mode.
0x00=4mA
0X01=8mA
0X02=16mA
0X03=32mA
RAMMODE
0XF8
0X00
DGUS variable memory access interface control

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3.2 Memory
The 8051 kernel of OS can access seven different kinds of memory, which are shown as below.
Memory type
Size
Address space
Access mode
Code memory
64KBytes
0x0000-0xFFFF
It can only be read by MOVC instruction, same as standard
8051.
Data register
256Bytes
0x00-0xFF
The same as standard 8051
SFR register
128Bytes
0X80-0XFF
The same as standard 8051. DWIN can provide user SFR
definition files( .INC or .H header file).
Extended SFR register
64Bytes
0x00-0x3F
Accessible using the SFR register interface defined by EXADR,
EXDATA.
Data memory
32KBytes
0x8000-0xFFFF
Accessible using MOVX instruction. When DPC is configured as
0x00, same as standard 8051.
DGUS variable memory
256KBytes
0x00:0000-0x00:FFFF
Accessible using DGUS variable memoryinterface.
CANCommunication
interface
48Bytes
0xFF:0060-0xFF:006B
Accessible using DGUS variable memoryinterface.
3.2.1 Code Memory(64KBytes)
Functional partitioning and definition of the code memory space are shown in the followingtable.
Address
Definition
Instructions
0x00
Reset_PC
After reset, the program starts running address.
0x00
EX0_ISR_PC
External interrupt 0 program interface
0x00
T0_ISR_PC
Timer0 interrupt program interface
0x00
EX1_ISR_PC
External interrupt 1 program interface
0x00
T1_ISR_PC
Timer1 interrupt program interface
0x00
UART2_ISR_PC
UART2 TX/RX interrupt programinterface
0x00
T2_ISR_PC
Timer2 interrupt program interface
0x00
CAN_ISR_PC
CAN interface interrupt programinterface
0x00
UART4_TX_ISR_PC
UART4 TX interrupt program interface
0x006B
UART5_RX_ISR_PC
UART5 RX interrupt program interface
0x0083
UART3_ISR_PC
UART3 TX/RX interrupt program interface
0x00F8
JMARK interface enabled
0xFFFF will allow connection to JMARK interface for simulation debugging, and
other values will be prohibited.
0x00FA
"DWINT5"
Code identification, illegal values will cause OS 8051 to stop running.
0x0100
Application code start
Maximum 63.75KB
The OS 8051 code is stored in the 0x01:0000-0x01:FFFF position of the 1Mbytes on chip Flash.
After power-on reset, the system loads and runs in RAM.
Code can only be written to on-chip Flash through SD interface or UART1 interface (or WIFI
network interface, etc).

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3.2.2 Variable Memory(256KBytes)
(1) 0x00:0000-0x00:7FFF addresses correspond to the 128Kbytes variable memory space currently
used by the DGUS II system.
For example, the two DGUS II variable memories, 0x1000 and 0x1001, correspond to the 0x0800
address of the OS 8051 DGUS variable memory, where D3 corresponds to the 0x1000 variable high
byte and D2 corresponds to the 0x1000 variable low byte; D1 corresponds to 0x1001 variable high
byte and D0 corresponds to 0x1001 variable low byte.
(2) 0x00:8000-0x00:FFFF addresses are not used by DGUS II system at present, and can be defined
by users as variable memory.
(3) 0xFF:0060-0xFF:006B address, the configuration and transceiver buffer of CAN interface.
Access to the DGUS variable memory uses the SFR register interface in the following table.
SFR name
Address
Instruction
RAMMODE
0xF8
DGUS variable memory access interface control, which can be bit addressed.
.7 Write 1=request occupation of DGUS variable memory to read/write. Must be cleared when not
occupied.
.6 APP_EN Write 1=initiate read/write once. It is cleared after hardware execution.
.5 APP_RW 1=Read variable memory 0=Write variable memory
.4 APP_ACK Hardware answer to 8051 request to occupy variable memory, 1=OK, 0=BUSY.
.3-.0 Corresponding to DATA3:DATA0 Write enable 1=corresponding bytes written, 0=corresponding
byte not written.
ADR_H
0XF1
DGUS variable memory high 8-bit address,A23:A16.
ADR_M
0XF2
DGUS variable memory middle 8-bitaddress,A15:A8.
ADR_L
0XF3
DGUS variable memory low 8-bit address,A7:A0.
ADR_INC
0xF4
The automatic increment of address after reading and writing of DGUS variable memory.
That is, ADR_H:M:L after reading and writing = ADR_H:M:L+ADR_INC before.
DATA3
0xFA
DGUS variable data interface, write selection corresponds to RAMMODE.3.
DATA2
0XFB
DGUS variable data interface, write selection corresponds to RAMMODE.2.
DATA1
0XFC
DGUS variable data interface, write selection corresponds to RAMMODE.1.
DATA0
0XFD
DGUS variable data interface, write selection corresponds to RAMMODE.0.
DGUS variable memory must be read and written according to the steps below.(If you want to use
interrupt in the application, the interrupt must be closed when the main application reads and writes
DGUS variable data, not embedded.)
(1) Configured address and address increment;
(2) Set RAMMODE as 0x8F (write) or 0xAF (read), check if RAMMODE. 4=1 to confirm access to
read and write control.
(3) Read and write data, set RAMMODE as 0X00 after reading and writing.

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Example
Read and write two double words in 0x0800 address (corresponding to DGUSII variable memory
address 0x1000).
MOV ADR_H,#00H ;Configure DGUS variable memory address
MOV ADR_M,#08H
MOV ADR_L,#00H
MOV ADR_INC,#01H ;Configuration address increment
MOV RAMMODE,#0AFH ;Start read mode
JNB APP_ACK,$ ;Waiting for confirmation
MOV R0,#TEST_BUF ;Reading demo
MOV R1,#2
RDVP: SETB APP_EN ;Start reading data once
JBAPP_EN,$
MOV @R0,DATA3
INC R0
MOV @R0,DATA2
INC R0
MOV @R0,DATA1
INC R0
MOV @R0,DATA0
INC R0
DJNZ R1,RDVP
CLR APP_RW ;Writing mode; writing demo
MOV ADR_L,#00H ;Adjust the address to 0x08:0000
MOV R0,#TEST_BUF
MOV R1,#2
WRVP: MOV DATA3,@R0
INC R0
MOV DATA2,@R0
INC R0
MOV DATA1,@R0
INC R0
MOV DATA0,@R0
SETB APP_EN ;Start writing data once
JNB APP_EN,$
INC R0
DJNZ R1,WRVP
MOV RAMMODE, #00H ;Variable memory read and write ends

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3.2.3 Data Memory(32KBytes)
The OS 8051 CPU of T5L has 32KBytes RAM as data memory, corresponding to addresses 0x8000-
0xFFFF, and the related interface SFRs are listed below.
SFR name
Address
Instructions
DPC
0x93
DPTR change mode after MOVX instruction operation.
DPC=0X00:DPTR remains unchanged after MOVX instruction operation. If developed using
C51, DPTR must be configured as 0x00
DPC=0X01 After MOVX instruction operation, DPTR=DPTR+1
DPC=0X03 After MOVX instruction operation, DPTR=DPTR-1
DPH
0X83
DPTR data pointer
DPL
0X82
The address space from 0x0000 to 0x7FFF prohibit using MOVX instructions to read and write,
which may cause code to runabnormally.
The T5L's MOVX instruction is 3 instruction cycles (3T, 14.5nS at 11.0592MHz crystal), and the DPC
can be configured with DPTR auto increment (or decrement) mode, making the T5L much faster than
the standard 8051 for reading and writing data memory, especially for inverse order memory read
and write applications.
Example
MOV
DPC,#01H
;DPTR++
MOV
DPTR,#8000H
MOVX
A,@DPTR
;A=@8000
MOVX
A,@DPTR
;A=@8001, DPTR=8002 after reading

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3.2.4 Extended SFR Register
Extended SFR registers use EXADR, EXDDATA register to read andwrite.
SFR name
Address
Instruction
EXADR
0xFE
Extend the SFR address and automatically add 1 to the next SFR after each reading andwriting.
EXDATA
0xFF
Expanding SFR data interface
The extended SFR register defines the register interface of the Mathematical Operating Unit (MDU)
and provides 48 additional data storage for users. The following table is defined:
EXADR
Definition
Instruction
0x00
MDU_A7
Maximum bit of MDU Aregister(64bit)
......
0x07
MDU_A0
Minimum bit of MDU A register(64bit)
0x08
MDU_B7
Maximum bit of MDU B register(64bit)
......
0x0F
MDU_B0
Minimum bit of MDU B register(64bit)
0x10
MDU_C7
Maximum bit of MDU C register(64bit)
......
0x17
MDU_C0
Minimum bit of MDU C register(64bit)
0x18
EXR0
First extended data register.
0x19
EXR1
Second extended data register
0x3F
EXR39
Fortieth extended data register
If you need to read or write the extended SFR in the interrupt application, the main program must
turn off the interrupt when reading or writing the extended SFR and cannot be embedded.

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3.3 Mathematical Operating Unit(MDU)
Due to the limited computing power of 8051, the hardware mathematic unit (MDU) is extended in T5L
to improve computing power. OS 8051 applications can access hardware MAC and hardware divider.
The related SFR definitions are as follows:
SFR name
Address
Instruction
MAC_CN
0xE5
The MAC hardware multiplier-adder control register is defined asfollows.
.7 MAC enable. Write 1 to perform a calculation, and clear after hardwareexecution;
.6 MAC mode. 1 for multiplier-adder mode: C=A*B+C; 0 for multipliermode: C=A*B;
.5 Write 0;
.4 1=64bit MAC 0=32bit MAC(A3:0/B3:0/C7:0;note that C is still 64bit);
.3 1 = Signed number; 0 = Unsigned number;
.2-.0 Write 0;
The A, B, Cregister group is the MDU_A, MDU_B, MDU_C register group of extendedSFR registers.
DIV_CN
0XE6
DIV hardware divider control register (division C/A, quotient A, remainder B) is defined asfollows:
.7 DIV enable. Write 1 to perform a calculation, and clear after hardwareexecution;
.6 DIV mode 1: Rounded 0: Not rounded;
.5-.4 Undefined, write 0;
.3 1 = Signed number 0 = unsigned number;
.2-.0 Write 0;
The A, B, C register group is the MDU_A, MDU_B, MDU_C register group of extendedSFR registers.
Example: 32bit MAC calculate 0x1234*0x5678-0x2000
MOV
EXADR,#04H
;write A3:A0=0x 00 00 1234
MOV
EXDATA,#00H
MOV
EXDATA,#00H
MOV
EXDATA,#12H
MOV
EXADR,#34H
;write B3:B0=0x 00 00 56 78
MOV
EXDATA,#00H
MOV
EXDATA,#00H
MOV
EXDATA,#56H
MOV
EXDATA,#78H
MOV
EXADR,#10H
;write C7:C0=0xFF FF FF FF FF FF
E0 00 (-0x2000)
MOV
EXDATA,#0FFH
MOV
EXDATA,#0FFH
MOV
EXDATA,#0FFH
MOV
EXDATA,#0FFH
MOV
EXDATA,#0FFH
MOV
EXDATA,#0FFH
MOV
EXDATA,#0E0H
MOV
EXDATA,#00H
MOV
MAC_CN,#0C8H
;32bit integer MAC
MOV
A,MAC_CN
MOV
ACC,7,WTMAC
MOV
EXADR,#10H
;read results00 00 00 00 06 25 E0 60
MOV
R7,EXDATA