Dynamic Engineering PCI5IP User manual

DYNAMIC ENGINEERING
150 DuBois St. Suite C, Calif. 95060
831-457-8891 Fax [phone]
http://www.dyneng.com
[email protected]
Est. 1988
PCI5IP
User Manual
Integrated PCI óIP Module Carrier
Key Features
Fast Access with integrated PCI óIP Bridge
5 IP Positions with IO
8/32 MHz IP operation
8/16/32 bit accesses supported
16/32 bit IP module support
Data Alignment – Byte and Word Swapping
Watch Dog Timer
LED’s - Power, IP Access, User
Multi-board support
Manual Revision G1
Corresponding Hardware: Revision G
Fab Number 10-2002-0307
FLASH revision G1

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PCI5IP
Dynamic Engineering
150 DuBois St Suite C
Santa Cruz, CA 95060
This document contains information of proprietary interest to Dynamic
Engineering. It has been supplied in confidence and the recipient, by accepting
this material, agrees that the subject matter will not be copied or reproduced, in
whole or in part, nor its contents revealed in any manner or to any person except
to meet the purpose for which it was delivered.
Dynamic Engineering has made every effort to ensure that this manual is
accurate and complete. Still, the company reserves the right to make
improvements or changes in the product described in this document at any time
and without notice. Furthermore, Dynamic Engineering assumes no liability
arising out of the application or use of the device described herein.
The electronic equipment described herein generates, uses, and can radiate
radio frequency energy. Operation of this equipment in a residential area is likely
to cause radio interference, in which case the user, at his own expense, will be
required to take whatever measures may be required to correct the interference.
Dynamic Engineering’s products are not authorized for use as critical
components in life support devices or systems without the express written
approval of the president of Dynamic Engineering.
This product has been designed to operate with IP Modules and compatible user-
provided equipment. Connection of incompatible hardware is likely to cause
serious damage.
©2002-2016 by Dynamic Engineering.
Other trademarks and registered trademarks are
owned by their respective manufactures.
Revised July 21, 2016

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PRODUCT DESCRIPTION 5!
Theory of Operation 11!
INSTALLATION 12!
ADDRESS MAP 13!
PROGRAMMING 14!
pci5ip_intreg_base 17!
pci5ip_intreg_(a-e) 20!
pci5ip_intreg_int 23!
pci5ip_intreg_dswitch 25!
APPLICATIONS GUIDE 26!
Interfacing 26!
Engineering Kit 26!
IP Module Logic Interface Pin Assignment 27!
Construction and Reliability 28!
MTBF 28!
Thermal Considerations 28!
WARRANTY AND REPAIR 29!
Service Policy 29!
Out of Warranty Repairs 29!
For Service Contact: 29!
SPECIFICATIONS 30!
ORDER INFORMATION 31!
Table of Contents

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FIGURE 1!PCI5IP POWER FILTERING 8!
FIGURE 2!PCI5IP RESET CIRCUIT 9!
FIGURE 3!PCI5IP STROBE CONNECTION TABLE 10!
FIGURE 4!PCI5IP ADDRESS MAP 13!
FIGURE 5!PCI5IP CONTROL PORT 17!
FIGURE 6!PCI5IP SLOT CONTROL PORT 20!
FIGURE 7!PCI5IP 16 BIT BYTE SWAPPING 21!
FIGURE 8!PCI5IP 32 BIT BYTE SWAPPING 21!
FIGURE 9!PCI5IP INTERRUPT STATUS PORT 23!
FIGURE 10!PCI5IP USER SWITCH PORT 25!
FIGURE 11!PCI5IP LOGIC INTERFACE 27!
FIGURE 12!PCI5IP LOCATION REFERENCE 32!
FIGURE 13!PCI5IP CONNECTOR REFERENCE 32!
List of Figures

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Product Description
IndustryPack® Modules are an important part of solutions for Embedded situations.
Rugged, Small, light .. just right for many applications. IndustryPack® Modules require
a “carrier” to adapt them to the system. Dynamic Engineering has carrier solutions for a
variety of formats. PCI5IP is designed to support PC computer based solutions. Other
supported formats include PCIe, cPCI, PC104p, VPX.
PCI5IP is part of the Dynamic Engineering IP Compatible family of modular I/O
components. PCI5IP provides five IndustryPack® Compatible sites in one PCI slot. Two
of the slot pairs can be used for double wide IP Modules with either 16 or 32 bit IP
Module bus.
PCI5IP is supported with Windows® compliant [WDM32] drivers for XP and 2000
[WFM] for Win7 and Linux [Ubuntu]. VxWorks is in development. The drivers come
with a generic IP driver to allow use with “unknown” IP’s – IP’s that do not have a driver
designed yet. For example, third party IP’s
ID, IO, INT, and MEM access types are supported for read and write cycles. The full 8
Mbytes of address space is allocated to each of the MEM spaces.
The PCI bus is 32 bits wide and most industry packs are 16 bit devices. Byte, word,
and long word accesses are supported. Bytes can be to any address. Word accesses
need to be word aligned. Long word accesses need to be long word aligned. Each of
the access types has a one-to-one correspondence to the hardware. There are no
"extra" accesses with the PCI5IP design.
The Data bus is designed as a 32-bit bus with slots A,C,E on the D15-0 segment. B
and D are on the D31-16 half of the bus. The current hardware compensates and
allows for standard accesses to all slots – software transparent. The BC and DE slots
can be accessed as a 32 bit wide data path. The BC and DE slots are mechanically
aligned for double wide card installation as well as pairs of single wide cards.
A long word access to a 16 bit port will automatically be converted into two back-to-back
IP accesses with the address incrementing between cycles unless the increment
disable function is selected (see Slot control register description). In the increment
disable case the hi or low address can be specified for the double access.
For a read, one 32 bit data word will be returned. For example a long word read to the
ID space would yield $xx50xx49 for many boards as the "0" location has $49 and the
next address has $50. The long word mode happens automatically when all 4 of the
byte lane enables are detected asserted. The overall throughput is greatly enhanced

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with this mode of operation. Please note the non-data bytes should be masked, as
many IPs do not drive the “off byte”.
For a long word access to a long word port the 32 bit IP data bus is utilized. Slots B/C
and D/E form 32 bit slots when 32 bit IPs are installed. The access type is automatic
based on the address space used to access the slots. You can use 16 and 32 bit
accesses intermixed without changing your control registers if the IP supports both.
Slot C and E control registers define the access when in 32 bit mode. It may be
necessary to match Slot B clock to slot C and Slot D clock to slot E if your IP uses both.
The address is shifted from long [32] to short [16] by hardware and the byte strobes
used to access the individual bytes or words. If your card has mixed addressing
requirements you may need dual defines to account for the 32 bit and 16 bit addressing.
The PCI bus is defined as little endian and many IPs have their register sets defined to
operate efficiently with a little endian interface. The default settings on the PCI5IP are
“straight through” byte for byte and D15-0 written to address 0x00 before D31-D16
written to address 0x02 when long words are written to 16 bit ports. Please note that
any long word address can be used. The lower data is written to the lower address first,
then the upper data to the upper address. Each slot has a BS and WS control bit to
allow Byte and Word Swapping to be performed to accommodate alternate IP and OS
requirements.
Byte Swapping
16 bit ports
D15-8 óD7-0
D31-24 óD23-16
32 bit ports
D31-24 => D7-0
D23-16 => D15-8
D15-8 => D23-16
D7-0 => D31-24
Word Swapping will swap D31-16 with D15-0
If byte swapping is enabled and 0x1234 is written to an IP slot, then the IP will see
0x3412. If 0x12345678 is written to a 32-bit port then the IP will see 0x78563412. The
“is written” is defined by the data on the PCI bus. Your software/OS may do its own
conversion before the data gets to the PCI bus.
The byte and word swap controls are separated to allow the conversion to be used for
big-little endian and for register mapping purposes. Each slot has separate controls for

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access to that slot.
PCI5IP has a watch-dog timer function which completes the IP access if the IP does not
respond within 7.6 uS. The watch-dog timer has a master status bit and an optional
interrupt output. In addition to the master status each slot control register reports status
for the bus error. Multi-threaded programs can tell if their hardware access caused the
Bus Error even if other threads have accessed other hardware since the bus error was
caused.
The design of PCI5IP tags all accesses from the PCI bus. IP Modules can take longer
than the PCI response specification leading to the use of retry cycles on the PCI bus.
In a single CPU system the retry accesses are done serially. The current IP access will
be the correct one to respond to the retry access. In a multi-CPU system it is possible
to get out of sequence accesses, and potentially have the IP response sent to the
wrong retry access. By storing the PCI parameters for the IP access and only
responding to the correct retry cycle; multiprocessor cross contamination is avoided.
This feature is incorporated beginning with the revision F.
Each slot is programmable for 8 or 32 MHz. operation. The control register has
separate bits for slot A, B, C, D and E. The clocks are locked together and can be
switched at any time. Hardware insures that the clocks switch basis on a clock period
boundary to provide seamless operation.
PCI5IP supports interrupts from each slot with separate mask bits. Two interrupts from
each of the five slots. An interrupt “force” bit is supplied to aide in software
development. The bus error [watch dog timer] can also be an interrupt condition. The
masked interrupts are tied together and connected to INTA on the PCI bus.
PCI5IP has LED's for power, access, and user functions. The supplied voltages are
monitored and an LED illuminated when in tolerance. +12, -12, +5, 3.3. An additional 8
LED's are supplied which are controlled via the control register for user defined
purposes. Five LED’s are controlled by a timer circuit which is activated by the
acknowledge from each of the IP slots.
The power to each of the IP slots is individually filtered and fused for +5 and ±12. The
fuses are rated at 2A on the 5V rail and 1.1A on the ±12V rails. PCI5IP is designed to
route maximum power to each slot in parallel. The power supply capabilities for your
chassis may provide additional constraints. Each slot filter has a separate RF filter, bulk
capacitor, “self healing” fuse, and bipass capacitors. A bipass capacitor is located at
each of the power pins on the PCI5IP with the bulk capacitor near the filter pin for
optimum noise rejection, voltage hold-up and local filtering. For power hungry IP’s the
fuses can be replaced with a strap to allow for more than the specified current.

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FIGURE 1 PCI5IP POWER FILTERING
With the filter pin on each slot and bulk capacitor each IP is effectively isolated from the
other IP’s mounted to the PCI5IP. Additional work was done in layout to minimize the
amount of cross-slot electronic noise. Each of the IP slots is also isolated from the PCI
interface by the power conditioning. The FPGA uses 3.3 and 2.5V power which is
derived from the 5V supply and bussed on mini-planes to the FPGA. The FPGA is
effectively isolated from the IP slots by the regulators and additional filtering.
PCI5IP is well behaved with low noise power provided to each of the slots. PCI5IP is
designed for analog and digital IP applications including data acquisition,
instrumentation, measurement, command and control, telemetry and other industrial
applications.
An 8 bit "dip switch" is provided on the PCI5IP. The switch configuration is readable via
a register. The switch is for user defined purposes. We envision the switch being used
for software configuration control, PCI board identification or test purposes.
P C I P ow e r
IP P o w e r
F1
L1

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The reset switch provided can be used to reset the IP devices without affecting the PCI
bus. Power, PCI reset, and a control register bit also cause the IP Reset to be
activated. The reset is controlled to be synchronous to the 8 MHz. clock. Alternatively,
the IP-Debug-Bus card can be used for individual slot resets.
FIGURE 2 PCI5IP RESET CIRCUIT
The IO are brought to 50 pin headers. The headers are installed without ejectors to be
PCI compliant [height]. The ejectors can be installed by special request. Routing is
matched length, impedance controlled, and differential on a per IP basis. The
differential pairs are 1-2,3-4,..23-24, 25-50, 26-27…48-49. With this pattern the
differential pairs can be properly routed for both the IP and Header connectors with
adjacent pin pairs used except for the single 25-50 pair. Frequently 25 and 50 are
grounds. Routing is still 1:1 as well making signal tracing through the carrier easier to
deal with. Dynamic Engineering IP modules take advantage of the differential definition
just outlined.
PCI5IP conforms to the VITA standard for IndustryPack Carriers. This guarantees
compatibility with multiple IndustryPack compatible modules.
PCI5IP conforms to the PCI 2.3 specification and supports both 3.3V and 5V signaling
levels. PCI5IP is accessible in the memory space on the PCI bus. This guarantees
compatibility with other PCI compliant hardware – most PC’s.
The PCI interface is integrated with the IP interface providing superior performance over
designs relying on a separate PCI interface device. In addition to access speed the
higher level of integration results in fewer initialization steps and requirements, more
flexibility in operation, a higher MTBF, and less complex software with only one Base
Address [BAR] to deal with.
If your project can benefit from a "non-standard" implementation, or features that we
have not thought of, or implemented yet please let us know. The Xilinx has room. For
example; if your project will use IP's that can operate at 33 MHz instead of 32, then we
could synchronize the IP and PCI clocks and save several synchronization steps.
C
D Q
C
D Q
IP REFERENCE CLK
IP RESET
VCC DETECT TIMER
RESET REG BIT
PUSH BUTTON

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Wired but not yet implemented. (1) All of the DMA control signals are available for a
future revision to implement.
Wired and User implemented. The IP Strobe signal is connected from each IP slot to a
5 pin header to allow for inter-slot user defined communications. The IP specification
does not define what the strobe can be used for. The header is rarely used. If you
need it please add “–STB” to your order number and we will install the 5 pin header for
you. Standard .025” sq. posts suitable for wire-wrap inter-connection.
On each IP Slot the Strobe signal is connected to pin 46.
FLASH memory is used to program the FPGA. Future updates can be added to your
card with the Xilinx Impact tool should you want to make use of a new feature. For
example with the Revision G FLASH, the PCI Core is now a Dynamic Engineering
design. This is important because we have corrected a defect in the core previously
used which interfered with use in external chassis.
FLASH Revisions:
Initial Release A 4/2002, ported from PCI3IP and added 2 positions plus independent
controls
Rev B 6/03 Add independent bus error status bits
Rev C 6/03 Add 32 bit addressing and dual slot operation capability
Rev D 7/03 Add byte and word swap capability
Rev E 6/09 Add protection for multi-processor operation
Rev F 8/09 minor update for 32 bit addressing with multi-processor protection
Rev G 4/16 Update to use DE designed PCI core, add Readable Revision field
Rev G.1 7/16 Update to add Bus Error status bits to base status register and master
bus error clear control. Modification to Bus Error capture logic. Addition
of readable FLASH major and minor revision.
Strobe Pinout on Header
TP1
1 STB A
2 STB B
3 STB C
4 STB D
5 STB E
FIGURE 3 PCI5IP STROBE CONNECTION TABLE

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Theory of Operation
PCI5IP is used to bridge from PCI to IP bus specifications. The PCI bus will be the
master in most cases with the IP's being accessed for read or write cycles. The PCI
accesses are handled at the lowest level by the PCI core.
The PCI bus provides multiplexed address and data plus control lines. The data is
separated from the address, and the control lines are decoded to provide the inputs to
the IP Interface state machines. The address is tested to determine which slot the
access belongs to and which type of access to implement. The IP control strobes are
generated. When acknowledge is received the cycle is terminated back to the host.
The PCI bus will see a retry mode while the access is taking place and "disconnect with
data" when the cycle is completed.
Feature List
• PCI Universal Voltage [3.3 or 5V signaling]
• Integrated PCI óIP conversion for faster access
• 5 IP compatible positions
• Full ID, IO, INT, and Memory space allocated for each IP
• 8 or 32 MHz operation in each slot independently
• byte, word, long word access. 32 bit access to 16 bit slots with static or incrementing
address. 32 bit access to 32 bit slots.
• byte and word swapping for little endian – big endian conversion
• Bus error abort response with slot status
• 1:1 50 pin headers with matched length, impedance controlled differentially routed
traces between IO and header
• IP Reset Switch
• 8 position "DIP Switch" – slot identification when multiple PCI5IP’s are in your system
or for user defined purpose(s)
• 8 User LED’s, 4 Power LED’s, 5 Access LED’s
• Fused Filtered Power with resettable “self healing” fuses in each slot.
• Windows®XP, Win7, Linux Drivers available. Generic IP interface included with driver
to support your IP. Dynamic Engineering driver development available for customized
IP support. [please download the separate Driver manual] VxWorks coming soon.
If you develop a driver for one of our products and are willing to allow others to use it;
we will add it to the web site as a free of charge download and, if desired, give credit to
the author.

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Installation
PCI5IP and the IP’s to be mounted should be treated as static sensitive hardware.
The technician should be properly grounded; the mounting and installation process
performed at a static free workstation.
PCI5IP can be installed into any PCI slot with full-length capability. The bezel and PCI
extension bracket securely retain the PCI5IP within the chassis. The PCI5IP with type1
IP Modules installed is PCI legal for height, length and width. Adjacent slots can be
filled with multiple PCI5IP cards.
Ordering options include a right angle connector for position A that protrudes through
the bezel. This is the standard option and helps with cabling. When this option is
ordered a special trimmed rear support is mounted to allow PCI5IP to be rotated
through the chassis rear bezel port while engaging at the rear support. When the –BB
option is ordered a vertical connector is installed, a blank bezel is provided in place of
the cable bezel [designed to allow cables to come through the bezel], and a traditional
offset rear support bracket is provided.
Each of the 5 IP positions can have an IP installed. IndustryPack®s are installed by
pushing the mezzanine card onto the connector pair on the PCI5IP. Each position is
clearly marked. The IO connector is located near the top of the PCI5IP and the IP Bus
connector near the PCI backplane edge. The IP connectors are keyed making
orientation error proof. Please refer to Figure 12 for the position and IO connector
placement.
The IP mounting kit can be utilized to secure the IP to the PCI5IP. Each Dynamic
Engineering IP sold comes with a mounting kit. If you need a replacement or your IP
comes from another manufacturer please order IP-MTG-HW. 1 kit per IP. The kit
includes stainless steel hardware – screws and standoffs.
http://www.dyneng.com/IPHardware.html
If more than one PCI5IP is to be installed into the same system – visible on the PCI bus
the dipswitch can be set to different positions on each card. Software can use the
dipswitch setting to identify which PCI5IP is allocated which address space and
associate specific IP/cables with that PCI5IP so there is positive automatic control of
your system configuration. The Dynamic Engineering Driver makes use of this feature
to allow multiple PCI5IP’s to be used in the same system without identification
challenges.

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Address Map
pci5ip_intreg_base 0x00000000 // base control register
pci5ip_intreg_a 0x00001000 // slot A specific clock and interrupt
pci5ip_intreg_b 0x00002000 // slot B
pci5ip_intreg_c 0x00003000 // slot C
pci5ip_intreg_d 0x00004000 // slot D
pci5ip_intreg_e 0x00005000 // Slot E
pci5ip_intreg_dswitch 0x00006000 // User Switch read back port
pci5ip_intreg_int 0x00007000 // Interrupt status read-back
pci5ip_ida_st 0x00110000 // starting address of slot A ID space
pci5ip_idb_st 0x00140000 // starting address of slot B ID space
pci5ip_idc_st 0x00120000 // starting address of slot C ID space
pci5ip_idd_st 0x00150000 // starting address of slot D ID space
pci5ip_ide_st 0x00130000 // starting address of slot E ID space
pci5ip_idbc_st 0x00160000 // starting address of slot B/C ID
pci5ip_idde_st 0x00170000 // starting address of slot D/E ID
pci5ip_ioa_st 0x00210000 // starting address of slot A IO space
pci5ip_iob_st 0x00240000 // starting address of slot B IO space
pci5ip_ioc_st 0x00220000 // starting address of slot C IO space
pci5ip_iod_st 0x00250000 // starting address of slot D IO space
pci5ip_ioe_st 0x00230000 // starting address of slot E IO space
pci5ip_iobc_st 0x00260000 // starting address of slot B/C IO
pci5ip_iode_st 0x00270000 // starting address of slot D/E IO
pci5ip_inta_st 0x00310000 // starting addr of slot A INT space
pci5ip_intb_st 0x00340000 // starting addr of slot B INT space
pci5ip_intc_st 0x00320000 // starting addr of slot C INT space
pci5ip_intd_st 0x00350000 // starting addr of slot D INT space
pci5ip_inte_st 0x00330000 // starting addr of slot E INT space
pci5ip_intbc_st 0x00360000 // starting address of slot B/C INT
pci5ip_intde_st 0x00370000 // starting address of slot D/E INT
pci5ip_mema_st 0x00800000 // starting addr of slot A MEM space
pci5ip_mema_en 0x00FFFFFF // end address of slot A MEM space
pci5ip_memb_st 0x02000000 // starting addr of slot B MEM space
pci5ip_memb_en 0x027FFFFF // end address of slot B MEM space
pci5ip_memc_st 0x01000000 // starting addr of slot C MEM space
pci5ip_memc_en 0x017FFFFF // end address of slot C MEM space
pci5ip_memd_st 0x02800000 // starting addr of slot D MEM space
pci5ip_memd_en 0x02FFFFFF // end address of slot D MEM space
pci5ip_meme_st 0x01800000 // starting addr of slot E MEM space
pci5ip_meme_en 0x01FFFFFF // end address of slot E MEM space
pci5ip_membc_st 0x03000000 // starting address of slot B/C MEM
pci5ip_membc_en 0x037FFFFF // end address of slot B/C MEM
pci5ip_memde_st 0x03800000 // starting address of slot D/E MEM
pci5ip_memde_en 0x03FFFFFF // end address of slot D/E MEM
FIGURE 4 PCI5IP ADDRESS MAP

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The address map provided is for the local decoding performed within PCI5IP.
The addresses are all offsets from a base address. The host the PCI5IP is
installed into provides the base address and interrupt level. Your software will
need to concatenate the base address + PCI5IP address + IP Local address to
create a pointer to each programmable feature on your IP.
Programming
The address map will connect to the IP module. The IP board description will
provide the local addresses. If you are in a Windows or Linux environment you
can use a Dynamic Engineering Driver for the carrier and potentially the IP.
Complete information is provided within this manual to allow customers who use
another OS or want to write their own interface to do so.
Dynamic Engineering can write a driver for your IP to interface with our carrier(s)
even if it is not “one of ours”. Please contact [email protected] with your
requirements if you are interested in this service.
The host system will search the PCI bus to find the assets installed during power-
on initialization. The VendorId = 0x10EE and the CardId = 0x000B for the
PCI5IP. Interrupts are requested by the configuration space. The VendorId and
CardId parameters are used by the OS to identify the card and in some cases
launch the plug and play installation process. The interrupt level expected and
style is also set in the registry.
Once the initialization process has occurred and the system has assigned an
address range to the PCI5IP card, the software will need to determine what the
address space is. We refer to this address as base0 in our software.
The next step is to initialize the PCI5IP. The default of no interrupts enabled and
8 MHz. operation will be valid in many cases. The base register for the PCI5IP
and specific slot registers A-E can be initialized to change the default parameters
to suite your requirements. Please refer to the register map definitions for more
information.
Access to your installed IP is done by accessing base0 + slot address + IP offset.
The slot address is defined in the memory map. For example to read your IP in
slot D IO space: *(base0 + pci5ip_iod + ip offset) = data. Each slot and memory
type [IO, ID, INT, Mem] has a unique address space for 20 defined address
spaces [non-32 bit] plus the PCI5IP internal address space. The internal
registers are defined in the following pages.

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Please note the Dynamic Engineering Windows® and Linux drivers for PCI5IP
take care of communicating with the system, discovering the address ranges and
interrupt levels and supporting the IP Module level drivers. The SW is included
with your purchase of PCI5IP. Additional HW support tools are available in the
form of an engineering kit.
Dynamic Engineering IP Module drivers are automatically launched as the
Carrier level driver detects the IP Module during initialization. Multiple Modules
of the same type and mixed modules are supported. Third party modules are
supported with a Generic Driver included with the carrier level driver. IP Module
drivers can work with any of the Dynamic Engineering IP Module Carriers for
PCI.
The IP Module Driver communicates with the Carrier level driver to discover the
carrier it is mounted to and the slot. With the carrier and slot information
deterministic control of hardware is possible in a PCI system along with flexibility.
The Carrier DIPSWITCH is used to differentiate one from another in a multiple
carrier system, and the slot number is used to further differentiate between
multiple cards of the same type.
The IP module positions are labeled A-E in the silk for identification.
PCI5IP has an integrated PCI interface with IP bridge. The integrated approach
simplifies programming with only one base address and fewer parameters to
have to initialize. The integrated approach is also a faster access approach
leading to higher performance in your system.
Higher performance for your system can be achieved by matching the IP register
model to the OS and user software model that you are using, selecting the
optimal IP reference clock rate and access types.
PCI5IP has individual clock selection for each of the IP modules. Access time is
reduced when the IP clock rate is set to 32 MHz. PCI5IP can handle any mixture
of clock requirements. Make sure that the IP can handle the higher rate. All
Dynamic Engineering IP Modules are rated for both 8 and 32 MHz operation.
PCI5IP can handle byte, word and long word accesses from the PCI bus. The
state machine within the bridge will automatically select 16 or 32 bit IP width
based on the address space utilized. 32 bit accesses to 16 bit ports will be
converted to double accesses. 32 bit accesses to 32 bit ports will be handled in
a single access. The Byte Swap [BS], Word Swap [WS], Address Increment, and

Page 16 of 32 Embedded Solutions
Word High allow the accesses to be customized for the IP installed for optimum
performance. 32 bit accesses to 16 bit ports are faster than individual 16 bit
accesses and frequently easier to write software for. For example if your IP has
a 24 bit port with 16 bits in one register and 8 in the next you can write all 24
with one 32 bit access. With word and byte swapping you can account for the
organization of the registers on the IP. Some IP’s convert 16 bit accesses to
double 8 bit accesses – IP-QuadUART for example. If your IP has 16:8
conversion then you can write 32 bits and get 4 – 8 bit writes to your IP in one
access.
Read the IP manual and see what strategy is best to communicate with that card
then adapt the settings on the PCI5IP to optimize your accesses to that IP. With
separate control registers for each installed IP you can run different strategies for
each installed IP as appropriate.

Page 17 of 32 Embedded Solutions
Register Definitions
pci5ip_intreg_base
[$00 Main Control Register Port read/write]
CONTROL REGISTER 0
DATA BIT DESCRIPTION
31 Reset 1 = reset IPs 0 = normal
30-14 spare
13 INT FORCE 1 = FORCE 0 = NORMAL
12 Master INT EN 1 = ENABLED 0 = DISABLED
11 spare
10 Bus Error Status Master Clear
9 Bus Error Int/Status Clear
8 Bus Error Int En
7 LED7 1 = ON 0 = OFF
6 LED6
5 LED5
4 LED4
3 LED3
2 LED2
1 LED1
0 LED0
FIGURE 5 PCI5IP CONTROL PORT
Reset when set causes a reset to the IP slots. Reset is active as long as the
Reset signal is asserted. Reset is synchronized to the IP clock per the IP
interface specification. The duration is controlled by the user software. 200 mS
is a suggested minimum time to enable for resetting purposes. In addition there
is a device on board which causes an IP reset of 200+ mS when a power
transition to the powered on state is detected.
LED7-0 are the user LED's situated at the right side of the card near Slot E.
Each LED can be activated by setting the corresponding data bit and deactivated
by clearing the same bit. The LED’s are aligned: 0x12 would be
off off off on off off on off [7ó0]
Spare means undefined, and is suggested to be written as ‘0’ to allow for
commonality with future enhancements.
INT FORCE will, when set, cause INTA on the PCI bus to be asserted. This bit

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can be useful for software debugging. Set this to simulate an IP interrupt when
the hardware is not available. The master interrupt must be enabled to have an
effect.
Master Interrupt Enable must be set to allow the IP or other interrupt conditions
to become an interrupt on the PCI bus. 1 = enabled. 0 = disabled or masked.
Bus Error Int En when ‘1’ allows the bus error detection circuit to cause an
interrupt to the host when a Bus Error is detected. The status is available on the
Interrupt status register. When ‘0’ the status is still valid but no interrupt is
generated when a bus error is detected. The bus error is detected when an
access to one of the IP slots is not responded to by IP hardware within the time-
out period of approximately 7.3 uS.
The bus error circuit is always enabled and automatically responds as if the IP
had responded. The data read will typically be $FF if the IP is not driving the bus
for a bus error read. For a bus error during a write, the write should be assumed
to not have taken place. The host will not know that the bus error has taken
place unless the host checks the status. The interrupt can provide a prompt to
check the status during operation. During initialization if the software is checking
to “see” what is installed or what address range is valid on an IP, the status can
be polled to see if the IP responded.
The Bus Error State-machine has 3 states, Idle, Armed, Clear. When in Idle
[default reset condition] the SM is waiting for a Bus Error to occur. The trigger is
the logical OR of any of the 7 bus error status bits from the 5 IP positions
including the two for 32 bit wide cards. When detected the SM moves to the
Armed state setting the status bit. The status bit is masked to become the
interrupt request if enabled. When SW sets the INT Clear bit the SM moves to
the CLEAR state and waits for the slot status to also be cleared before returning
to IDLE. This is to prevent the cleared SM from retriggering before the slot status
is cleared.
Bus Error Status / INT Clear when ‘1’ will clear the Bus Error status bit and
interrupt request [if enabled]. The Clear bit needs to be reset to ‘0’ to be able to
capture the next Bus Error as well as the slot status bit(s). The bus error timer
hardware operates independent of clearing the status and will continue to
monitor and intercede whether the status is read or cleared.
Each of the slot registers has an additional status bit to identify which slot caused
the bus error. The slot register bus error status is repeated in the upper bits to

Page 19 of 32 Embedded Solutions
allow single read ISR operation. Please see the PCI5IP Interrupt Register
description.
Bus Error Status Master Clear when set ‘1’ causes the Bus Error Status bits in all
of the channels to be cleared as well as the state-machine that manages the bus
error interrupt. Remember to reset to ‘0’ for normal operation. Usually only
needed after enumeration / slot discovery. The unfilled locations will have bus
error status set which needs to be cleared for proper operation of the bus error
interrupt state machine.

Page 20 of 32 Embedded Solutions
pci5ip_intreg_(a-e)
[$01000,2000,3000,4000,5000 Slot Control Register Port read/write]
Slot CONTROL REGISTER (A-E)
DATA BIT DESCRIPTION
31-9 Undefined
8 bus error status/clear
7 word swap control
6 byte swap control
5 Interrupt Enable 1
4 Interrupt Enable 0
3 High Word Access
2 Increment Disable
1 spare
0 Speed Control 1 = 32 MHz, 0 = 8 Mhz
FIGURE 6 PCI5IP SLOT CONTROL PORT
Speed Control selects the slot clock speed. 1 = 32 MHz. 0 = 8 MHz. Clock
selection change can be made at any time. Each slot has a separate speed
control bit. Default is 8 MHz.
Increment Disable, when ‘1’, turns off the address increment that normally
occurs between 16-bit IP cycles when a 32-bit PCI access is performed. This is
useful if, for instance, a FIFO is mapped to a single IP address since it allows
double IP accesses to the same address with a single PCI transfer. All types of
access are affected (i.e. MEM, IO, INT, and ID). Each slot has independent
controls and operation. Only 32 bit accesses are affected.
High Word Access controls which 16-bit word is accessed when the Increment
Disable is asserted. When ‘0’ the lower word is accessed twice, when ‘1’ the
upper word is accessed twice. This bit only has an effect when the Increment
Disable bit is ‘1’. For correct functioning, please make sure the PCI access is on
a long-word boundary.
Interrupt Enable 0,1 individual masks for the 2 interrupts from each of the 5
slots. 0 corresponds to INT0 and 1 corresponds to INT1.
Byte Swap when ‘1’ causes the byte lanes to be swapped. For a 16-bit access
the upper byte is swapped with the lower byte. For a 32-bit access to a 16-bit
port the upper and lower of each word are swapped. For a 32-bit access to a 32-