ELAN DIGITAL SYSTEMS AD135 User manual

Elan Digital Systems Ltd. 1AD125 USER’S GUIDE
ELAN DIGITAL SYSTEMS LTD.
LITTLE PARK FARM ROAD,
SEGENSWORTH WEST,
FAREHAM,
HANTS. PO15 5SJ.
TEL: (44) (0)1489 579799
FAX: (44) (0)1489 577516
e-mail: [email protected]
website: www.pccard.co.uk
AD125 PC-CARD USER’S GUIDE
ALSO COVERS AD135, AD126, AD136, AD132, AD121, AD131
AND “MF2xx” SERIES CARDS
REVISION HISTORY
ISSUE PAGES DATE NOTES
1 50 30.10.96 FIRST ISSUE
2 50 06.03.97 CORRECTION TO SAMPLE RATE
CALCULATIONS
3 50 06.06.97 REDUCED LOAD LIMIT ON +/-15V
4 50 17.06.97 ADDED AD132
5 48 26.01.98 SIMPLIFY PCCARDGO TEXT & ADD
NOTE ABOUT PRE-RUN IN
SECTION 3.5.3
6 50 15.07.98 ADD AD121/131 & SEC 1.1. ALSO
SOME MINOR SPEC CHANGES IN
5.2.
7 43 23.07.98 REMOVED SOFTWARE SECTION
TO PCCARDGO.DOC
8 45 04.01.99 MF SERIES CARDS

Elan Digital Systems Ltd. 2AD125 USER’S GUIDE
CONTENTS
1. OVERVIEW..................................................................................................4
1.1 MODEL NAMING CONVENTIONS.........................................................................................5
2. ABOUT THE AD125 ....................................................................................6
2.1 QUICK THEORY OF SUCCESSIVE APPROXIMATION CONVERTERS........................6
2.2 NOISE............................................................................................................................................6
2.3 POSSIBLE SOURCES OF MEASUREMENT ERROR...........................................................8
2.4 D to A Converters.........................................................................................................................9
3. CONTROLLING THE AD125.....................................................................10
3.1 ACQUISITION MODES............................................................................................................10
3.1.1 BURST MODE......................................................................................................................10
3.1.2 FIFO MODE..........................................................................................................................11
3.1.3 SINGLE-SHOT MODE.........................................................................................................11
3.2 A to D OUTPUT FORMAT / GAIN SETTING.......................................................................12
3.3 AD125 BUFFER ADDRESSING...............................................................................................14
3.3.1 BUFFER DATA ORDER......................................................................................................14
3.3.2 CONTROLLING THE SRAM POINTERS..........................................................................14
3.3.3 PRE-TRIGGER DEPTH .......................................................................................................15
3.3.4 READING THE SRAM DATA ............................................................................................16
3.4 TRIGGERING............................................................................................................................17
3.4.1 THRESHOLD........................................................................................................................17
3.4.2 TRIGGER MODES...............................................................................................................18
3.4.3 ENABLING TRIGGER.........................................................................................................19
3.5 OTHER FEATURES..................................................................................................................20
3.5.1 SAMPLE RATE....................................................................................................................20
3.5.2 INPUT MUX CONTROL .....................................................................................................21
3.5.3 SLEEP MODE.......................................................................................................................23
3.5.4 INTERRUPTS.......................................................................................................................23
3.5.5 CONFIG OPTION REGISTER.............................................................................................25
3.5.6 DIGITAL IO..........................................................................................................................26
3.6 DAC PROGRAMMING............................................................................................................27
4. AD125 REGISTER INTERFACE ...............................................................29
4.0 SETUP REG 1 (IR 0)..................................................................................................................31
4.1 SETUP REG 2 (IR 1)..................................................................................................................32
4.2 IODATA (IR 2)...........................................................................................................................33
4.3 IODIR (IR 3)...............................................................................................................................34
4.4 DIVLO / ADDRCTLO (IR 4) ....................................................................................................35

Elan Digital Systems Ltd. 3AD125 USER’S GUIDE
4.5 DIVHI / ADDRCTHI (IR 5).......................................................................................................35
4.6 MUXSEQ (IR 6)..........................................................................................................................36
4.7 TRIGTHRESH (IR 7) ................................................................................................................36
4.8 CTLEN (IR 9) .............................................................................................................................37
4.9 DECR (IR D)...............................................................................................................................37
4.10 DECW (IR E)............................................................................................................................38
4.11 CLRCT (IR F)...........................................................................................................................38
5. HARDWARE SPECIFICATION..................................................................39
5.1 PINOUT.......................................................................................................................................39
5.2 ANALOGUE...............................................................................................................................40
5.2.1 CALIBRATION DATA........................................................................................................41
5.3 DIGITAL.....................................................................................................................................43
5.4 POWER CONSUMPTION........................................................................................................43
5.5 MECHANICAL..........................................................................................................................43
5.6 ENVIRONMENTAL..................................................................................................................43
6. SOFTWARE...............................................................................................44
6.1 UNIVERSAL DRIVER..............................................................................................................44
6.2 C SOURCE CODE .....................................................................................................................44
7. OPERATIONAL PRECAUTIONS .............................................................45
Disclaimer
This document has been carefully prepared and checked. No responsibility can be
assumed for inaccuracies. Elan reserves the right to make changes without prior notice
to any products herein to improve functionality, reliability or other design aspects.
Elan does not assume any liability out of the use of any product described herein;
neither does it convey any licence under its patent rights not the rights of others. Elan
products are not authorised for use as components in life support services or systems.
Elan should be informed of any such intended use to determine suitability of the
products.
Source code supplied with Elan PC-Cards is provided “as-is” with no warranty, express
or implied, as to its quality or fitness for a particular purpose. Elan assume no liability
for any direct or indirect losses arising from use of the supplied code.
Copyright © 1996,1997,1998 Elan Digital Systems Ltd.

Elan Digital Systems Ltd. 4AD125 USER’S GUIDE
1. OVERVIEW
Before using the AD125, take some time to read the section
“OPERATIONAL PRECAUTIONS”.
The AD125 card is a general purpose Analogue Data Acquisition
card with the following features:
•12-bit 0.5MSPS A to D converter (0.625MSPS FOR AD1x6)
(0.25MSPS FOR AD132, 0.1MSPS FOR AD121/131)
•16 single ended / 8 differential fault protected analogue inputs (8
single ended / 4 differential for AD12x)
•2x12-bit D to A converters on MF series
•Bipolar and Unipolar input ranges
•20 different input range settings including +/-10V
•8 digital I/O lines for AD series or 4 I/O lines for MF series
•32K x 8 SRAM sample buffer (16K samples)
•Programmable conversion clock divider
•Three modes: BURST, FIFO, SINGLE-SHOT.
•Digital trigger threshold for BURST mode
•Programmable pre-trigger depth
This guide aims to familiarise you with the way that the AD125
works and so will help you to maximise its performance in your
application.
The AD125 is capable of high speed and high accuracy
measurements and can be used as part of a complete data acquisition
and control system. Its applications are limitless. All that is needed
is appropriate control and/or analysis software. Elan provides a
royalty free “kernel” of source code that can be used as a starting
point for your software design. By expanding and enhancing the
code provided, you will be able to gain a significant “time to
market” advantage.
Elan will be happy to quote for either customisation of the AD125 if
its exact specifications do not quite meet your needs, or to create
complete application software. We can also create drivers for 3rd
party “virtual instrument” software e.g. Signal Center or Keithley
Testpoint.

Elan Digital Systems Ltd. 5AD125 USER’S GUIDE
1.1 MODEL NAMING CONVENTIONS
The AD125 “family” of cards follows these naming conventions:
“AD1[X][Y]” for A to D cards
“MF2[X][Y]” for Multi-function A to D and D to A cards
[X] “2” ⇒8 single ended channels
“3” ⇒16 single ended channels
[Y] “1” ⇒100KSPS max sample rate
“2” ⇒250KSPS max sample rate
“5” ⇒500KSPS max sample rate
“6” ⇒625KSPS max sample rate

Elan Digital Systems Ltd. 6AD125 USER’S GUIDE
2. ABOUT THE AD125
2.1 QUICK THEORY OF SUCCESSIVE APPROXIMATION
CONVERTERS
The type of converter used in the AD125 approximates the analogue
level being applied to its input using a D to A converter and a
comparator. The converter starts in “track” mode where it is
following the input voltage and applying it to a track and hold
amplifier. Once the converter is told to perform a conversion, it
holds the current input voltage level on a capacitor while it
approximates its value.
The converter uses a clock to break the approximation process down
into 12 steps, one per bit. Each step attempts to approximate the
held input voltage to one more “bit” of resolution. The logic in the
A to D makes the most significant bit decision first as this is the
most “coarse” level, i.e. is the signal positive or negative.
Subsequent decisions are then made on the difference between the
output of the internal D to A converter and the held input value: if
the comparison is “greater” then the bit is set, if “less” the bit is
cleared. After 12 clocks the complete word is ready to be read out of
the converter.
2.2 NOISE
Noise in an A to D converter system will degrade the “effective
resolution” of the conversion. The noise can be power supply noise,
thermal noise, pick-up noise etc. All contribute to the degradation.
The Effective Number Of Bits for a converter expresses a measure
of the noise level relative to the input signal level.
The ENOB of a converter is expressed as:
ENOB = (SNR(dB) - 1.76) / 6.02
So, the better the signal to noise ratio the higher the effective
resolution. Be warned however, that this computation is based on
RMS noise. Taking individual samples from the AD125 will reveal

Elan Digital Systems Ltd. 7AD125 USER’S GUIDE
that the noise is Gaussian in distribution and is subject to the usual
statistical spread in its peaks and troughs from moment to moment.
So the converter output looks noisy, or at least more noisy than you
might expect. Normally this is not a problem but occasionally some
kind of post-processing of the data samples will be required in
software. This may mean a simple averaging process over say 10 or
more samples, or could be a properly designed digital filter. This
will depend on the exact application. Bear in mind that this
averaging could reduce the bandwidth of the data you are acquiring
and will increase the settling time needed for step-input changes.
The AD125 inevitably introduces several extra sources of noise:
•The voltage references
•The internal power rails
•Ground noise
•Noise from the front-end analogue circuits.
The power rails used inside the AD125 are designed to help
minimise power rail feedthrough.
All of these noise sources will act to degrade the ENOB attainable.
Post processing the data using a digital filter will help to improve the
effective resolution by reducing random noise.

Elan Digital Systems Ltd. 8AD125 USER’S GUIDE
2.3 POSSIBLE SOURCES OF MEASUREMENT ERROR
The following is a list of possible error sources that should be
considered when taking measurements with the AD125:
1. The offset voltage of the A to D device and the front end
electronics will mean that an input voltage of 0V will not produce
an output code of 000000000000b. Software could be used to
correct for zero-point offset errors by using one of the analogue
inputs to the AD125 and tying it to AGND. Switch to this channel
and measure its level to obtain the code for bipolar zero. A set of
factory calibration constants is held on the card and can be
accessed by software to compensate for this error is required.
2. Gain errors in the A to D device and the front end electronics will
cause full scale “end-point” errors. In other words the A to D
output code may reach 011111111111b before or after the input
gets to nominal full positive scale and similarly the code may
reach 100000000000b before or after the input voltage gets to
nominal negative full scale. A set of factory calibration constants
is held on the card and can be accessed by software to compensate
for this error is required.
3. Avoid ground loops. These can be caused when the source’s -ve
side is connected via the AD125 cable to AGND and to the shield
on the AD125’s connector. This shield is connected to the PC’s
chassis and so to “earth”( via the gold ESD strips on each side of
the card). The source’s -ve side (unless floating) will be the local
GND and if this too is connected “earth” then if there is any
difference between the two “earth” potentials current will flow in
the AGND wire between the source and the AD125 causing offset
voltages (due to I x R losses) (the current will return through the
mains wiring). Avoid such loops by not connecting the AD125
connector shield to any other terminal (the AD125 already
internally links the shield to the PC’s “earth”). You may also get
problems if you simply connect the shield to “earth” at the source
end; again differences in local “earth” potential will cause currents
to flow in the shield.
4. Avoid long connections to the AD125’s analogue inputs.
5. Keep AGND and GND separate. Any digital switching currents
that are allowed to share the same return path as analogue signals
will result in induced voltage noise. AGND and GND are linked

Elan Digital Systems Ltd. 9AD125 USER’S GUIDE
inside the AD125 at a “star-point”. All digital front-end circuits
use a separate ground trace to the front-end analogue circuits to
reduce such switching noise problems on the card itself. The
AGND/GND link occurs at the PCMCIA 68-way connector.
6. If using the inputs in differential mode, do not forget to keep the
common mode signal within the common mode range of the
AD125s inputs. The “best” you can achieve is to ensure that the -
side is very close to the card’s AGND level. This will give you
the maximum amount of “headroom” for the + signal. You can
arrange this (without making a direct connection) using an
external resistor of say 10K to “pull” the - side close to AGND.
2.4 D to A Converters
The two D to A converters on the MF series of cards can be set
individually to output a 12-bit resolution voltage. Each DAC drives
off card through a 10Oseries resistor and has a nominal range of 0 to
2.5V. Additionally, the output of each DAC is amplified and offset
so that a secondary nominal range of -10V to +10V is available.
These two amplifiers also drive off card through 10Oseries resistors.
This means that there is a total of four output pins for the two DACs.

Elan Digital Systems Ltd. 10 AD125 USER’S GUIDE
3. CONTROLLING THE AD125
3.1 ACQUISITION MODES
In all modes, the AD125 performs its conversions in around 2.0µs
(1.66µs for the AD1x6). The conversion rate is software
programmable and is achieved by “spreading-out” the conversions
using the PACER clock.
3.1.1 BURST MODE
This is the mode intended for transient capture or vibration analysis.
Summary:
The AD125 is set up with trigger threshold and edge. The READ
and WRITE POINTERS are put into a known starting state. The
pre-trigger depth is configured. The system is set into RUN mode
but with trigger disabled. The AD125 starts taking samples. After
some elapsed time, software sets ENTRIG to on to “arm” the system.
The AD125 will then wait until the incoming sample data meets the
trigger requirements. The buffer is circular so all the time that the
card is waiting for trigger samples are being stored away into
SRAM. When triggered, the READ POINTER freezes.
Conversions continue until the WRITE POINTER equals the READ
POINTER. Then the system halts and generates an interrupt. The
PC reads out the sample data from the SRAM for display /
processing.
The maximum sample rate in this mode is 500KSPS (or 600KSPS
for the AD1x6). This gives a buffer fill time of 32.768ms.
The slowest sample rate is 305SPS giving a buffer fill time of 53.7s.

Elan Digital Systems Ltd. 11 AD125 USER’S GUIDE
3.1.2 FIFO MODE
This is the mode intended for streaming data into the PC at high
speed.
Summary:
The AD125 takes continuous conversions in this mode. There is no
triggering. As soon as software sets RUN to on, the SRAM starts to
fill. The PC must empty the SRAM at a rate at least equal to the rate
at which it is being filled. An interrupt can be generated at 1/4 or
1/2 full to instruct the PC to fetch the correct amount of data from
the buffer. The throughput in this mode is PC speed dependent. If
an overrun occurs, i.e. the WRITE POINTER catches the READ
POINTER up, the AD125 will come out of RUN mode
automatically.
With well written Assembler/C software, 300KSPS should be
possible but the speed depends heavily on what happens to the data
once it is in the PC i.e. displayed / written to disk etc.
The “REP INSW” PC Assembler codes are essential to get high
speed.
3.1.3 SINGLE-SHOT MODE
This is the mode intended for streaming data into the PC at very low
rates.
Summary:
The AD125 takes single conversions in this mode. There is no
triggering. As soon as software sets RUN to on, a single conversion
occurs. The PC reads the sample out. The card automatically clears
the RUN state ready for the PC to set the next conversion in
progress. The time between conversions is totally controlled by the
PC. Remember to pre-clear the READ & WRITE POINTERS (and
do not try to set any pre-trigger) prior to commanding a single
conversion (this ensures that the process stops immediately after one
conversion rather than filling the whole SRAM buffer).

Elan Digital Systems Ltd. 12 AD125 USER’S GUIDE
3.2 A to D OUTPUT FORMAT / GAIN SETTING
The AD125 produces 2’s complement 12 bit output codes when in
Bipolar mode and “true binary” 12 bit codes when in Unipolar
mode. Table 3.2-1 summarises the codes.
THEORETICAL AD125 OUTPUT CODE
INPUT LEVEL BIPOLAR UNIPOLAR
(F.S. = FULL SCALE) BINARY HEX BINARY HEX
F.S. 011111111111 7FF 111111111111 FFF
F.S. - 1LSB 011111111110 7FE 111111111110 FFE
.... .... .... .... ....
0 + 2LSB 000000000010 002 000000000010 002
0 +1LSB 000000000001 001 000000000001 001
0 000000000000 000 000000000000 000
0 - 1LSB 111111111111 FFF
0 - 2LSB 111111111110 FFE
.... .... ....
-F.S. + 1LSB 100000000001 801
-F.S. 100000000000 800
Remember that the size of the LSB step changes depending on the
input range selected and whether you are operating in Unipolar or
Bipolar mode.

Elan Digital Systems Ltd. 13 AD125 USER’S GUIDE
20 different input ranges can be achieved with the AD125. The gain
is programmed using the top four bits of SETUP REG 1 (GS0..3).
The following table summarises the gains and input ranges
available:
GAIN GS0..3 AD125 INPUT VOLTAGE RANGE (volts)
BIPOLAR UNIPOLAR
4 0h ± 0.625 0 →1.25
2 1h ± 1.25 0 →2.5
4/3 2h ± 1.875 0 →3.75
1 3h ± 2.5 0 →5.0
4/5 4h ± 3.125 0 →6.25
2/3 5h ± 3.75 0 →7.5
4/7 6h ± 4.375 0 →8.75
1/2 7h ± 5.0 0 →10.0
4/9 8h ± 5.625
2/5 9h ± 6.25
4/11 Ah ± 6.875
1/3 Bh ± 7.5
4/13 Ch ± 8.125
2/7 Dh ± 8.75
4/15 Eh ± 9.375
1/4 Fh ± 10.0

Elan Digital Systems Ltd. 14 AD125 USER’S GUIDE
3.3 AD125 BUFFER ADDRESSING
3.3.1 BUFFER DATA ORDER
The AD125 always writes its A to D conversion samples into the
SRAM buffer. They can be read out directly by the PC software. 2
bytes of data get written to the SRAM for every conversion “event”.
The buffer is organised as follows:
Pointer Address Decreasing →→
7FFF 7FFE 7FFD 7FFC 7FFB 7FFA
Sample
n
low byte
Sample
n
high byte
Sample
n+1
low byte
Sample
n+1
high byte
Sample
n+2
low byte
etc etc...
The counters that control the SRAM addressing are 15-bit down
counters that address bytes. When cleared they are set to 7FFFh.
Each read by the PC of a byte of data decrements the READ
POINTER by one. Each conversion event decrements the WRITE
POINTER by two.
3.3.2 CONTROLLING THE SRAM POINTERS
The READ and WRITE pointers are 15 bits in length. They can also
be programmed to be 8,9,10,11,12,13 or 14 bits long if a “shorter”
buffer length is required. To achieve this, write to the CTLEN port
with a 7 bit value. The bits in this byte, referred to as the BUFFLEN
byte, are used to set the buffer length in the following way:
00h→8 bit
01h→9 bit
03h→10 bit
07h→11 bit
0Fh→12 bit
1Fh→13 bit
3Fh→14 bit
7Fh→15 bit
Note: The power up state of the CTLEN port is 00h
To decrement the READ POINTER by one, do a write access to the
DECR port with don’t care data.

Elan Digital Systems Ltd. 15 AD125 USER’S GUIDE
To decrement the WRITE POINTER by TWO, do a write access to
the DECW port with don’t care data. Remember that in FIFO mode,
you may get an IREQ when changing the WRITE POINTER
through a half or quarter count (just as you would if the AD125
passed these points whilst running at full speed...use the SELCTRD
bit to block interrupts whilst manipulating the WRITE POINTER if
this is a problem...see section on interrupts).
To clear all system counters to 7FFFh do the following:
1. Write access to CLRCT port with don’t care data. This will clear
the bottom 8-bits ONLY (it will also pre-load the MUXSEQ
counter...see section on INPUT MUX CONTROL)
2. With software, remember the value of the BUFFLEN byte (note
that the CTLEN port is WRITE ONLY), write to the CTLEN port
with 00h, then with BUFFLEN byte. This will clear the upper 7-
bits of the counters.
3. If in FIFO mode: pulse the SELCTRD bit in SETUP REG 2 to 0-
1-0 to clear the possible artificial IREQ event caused by the
internal counter outputs changing state.
The READ and WRITE POINTERS can be read via port 4 and 5
(low byte high byte respectively). Bit 6 of SETUP REG 2 controls
whether the READ or WRITE pointer is readable: 0→READ
POINTER, 1→WRITE POINTER. Do not read either pointer
while the AD125 is running or samples will be stored in the wrong
order in SRAM. Note that this bit is dual purpose and also serves to
clear IREQ events (without having to read the SRAM).
3.3.3 PRE-TRIGGER DEPTH
Before performing a BURST acquisition the WRITE POINTER
must be pre-decremented at least once by software (i.e. 2 bytes).
This will give a pre-trigger depth of 1 conversion. To make the pre-
trigger depth greater simply pre-decrement the WRITE POINTER
extra times, each write to the DECW port will give one conversion
more pre-trigger. So to set 200 conversions for the pre-trigger
depth, pre-clear the pointers (3.3.2) and then write 200 times to the
DECW port (don’t care data).

Elan Digital Systems Ltd. 16 AD125 USER’S GUIDE
Remember that you must control the RUN and ENTRIG bits
correctly to ensure that the pre-trigger buffer actually holds valid
conversion data: the AD125 could trigger before conversion results
have been written into the whole pre-trigger area of SRAM. The
rule is to set the AD125 into RUN mode but with ENTRIG off, in
software wait a minimum of (t x n) seconds before enabling trigger
(t is the sample period, n is the pre-trigger depth in conversions).
3.3.4 READING THE SRAM DATA
SRAM data is accessed via a single IO port at IOBASE+2. Each
read by the PC will fetch data and decrement the READ POINTER.
If the AD125 has halted after a BURST acquisition then the READ
POINTER must be “released” temporarily to read out the A to D
data. This is achieved by setting SINGLE mode (Bit 7 in SETUP
REG 2). Be sure to return this bit to zero before attempting to do
further BURST acquisitions.
SRAM data can be read as bytes or words. If reading bytes, read
two bytes to make a 16-bit value; the data is stored in the bottom 12
bits. If reading words, read 1 word to get a 16-bit value. The word
wide transfer will be broken into 2 byte wide transfers automatically
by the HOST PC. Pseudo word access throughput is faster than byte
access throughput. The HOST PCMCIA controller should be
configured with an 8-bit wide IO window running from IOBASE to
IOBASE+3 (NOT +2 else word-to-byte conversions may not work
correctly).
Note that the top 4 bits of the SRAM data hold the MUXSEQ count
of the conversion...see section on INPUT MUX CONTROL.

Elan Digital Systems Ltd. 17 AD125 USER’S GUIDE
3.4 TRIGGERING
3.4.1 THRESHOLD
The AD125 uses an 8-bit 2’s complement OR “true binary” trigger
threshold value. This is compared against the top 8-bits of the 12-
bits of A to D data to decide when to trigger the card. The value
loaded into the threshold register MUST be appropriate to the
conversion mode selected: 2’s complement for Bipolar, “true binary”
for Unipolar.
In C/C++ or PASCAL the threshold is calculated as a SHORT INT
in the following way:
Bipolar mode:
TRIGBYTE = ROUND(128*(Vtrig/Vfs)); /*Vfs = full scale input voltage */
Unipolar mode:
TRIGBYTE = ROUND(256*(Vtrig/Vfs)); /*Vfs = full scale input voltage */
Remember that the value loaded into the trigger threshold register
varies depending on the full scale input range selected via GS0..3.
When a trigger event occurs while ENTRIG is low in SETUP REG
1, the READ POINTER is frozen but the WRITE POINTER
continues to run. Once the READ and WRITE POINTER are equal
(i.e. the buffer is full) the AD125 halts and sets the RUN bit in
SETUP REG 1. This can be polled in software to see when the card
has halted. If enabled via the HOST, this will also cause an
interrupt. Software can also check the TRIGGER STATUS via Bit 5
of SETUP REG 1: a 1 indicates TRIGGERED.
Triggering is only used in BURST mode.

Elan Digital Systems Ltd. 18 AD125 USER’S GUIDE
3.4.2 TRIGGER MODES
There are various configurations of trigger on the AD125, they are
summarised below:
+ET
TREDGE=1 LVL=0 -ET TREDGE=0 LVL=0 > TREDGE=1 LVL=1 < TREDGE=0 LVL=1
TRIGGER WHEN
I/P TRANSITIONS
FROM BELOW
Vtrig TO ABOVE
Vtrig
TRIGGER WHEN
I/P TRANSITIONS
FROM ABOVE
Vtrig TO BELOW
Vtrig
TRIGGER
WHENEVER I/P IS
ABOVE Vtrig
TRIGGER
WHENEVER I/P IS
BELOW Vtrig
The modes are programmed via SETUP REG 2.
The AD125 can also be trigged externally via the nTRIGGER edge
connector signal. The signal is pulled up by 10K to Vcc inside the
card. Pulse the line low for a minimum of one sample period to
ensure the triggering is effective. This may mean external pulse
stretching is required for some applications.

Elan Digital Systems Ltd. 19 AD125 USER’S GUIDE
3.4.3 ENABLING TRIGGER
The AD125 will not trigger unless Bit 1 of SETUP REG 1 is low.
This allows software to “arm” the AD125 only when it is
appropriate to do so i.e. after some start up condition or when the
user has signalled that the system should arm ready to capture an
event.

Elan Digital Systems Ltd. 20 AD125 USER’S GUIDE
3.5 OTHER FEATURES
3.5.1 SAMPLE RATE
The SAMPLE RATE is programmed via a 14-bit divider, accessed
as an 8-bit register (DIVLO) and a 6-bit register (DIVHI). The clock
divider runs at 5MHz. Additionally, there is an extra control bit that
allows subtraction of a ¼ clock period from the divider. This is
located in SETUP REG 1 BIT-2 and is called “nTIMING”. The
purpose of this bit is to allow additional frequencies to be obtained
e.g. 571.4KSPS (at the top end).
The calculation for the two data bytes is given by:
nTIMING bit SET:
DIVHI = (round(1/(FSample*200E-9))-2) >> 8);
DIVLO =(round(1/(FSample*200E-9))-2) & 255);
( so FSample = 1/(200E-9 * (DIVHI:DIVLO + 2)) )
nTIMING bit RESET:
DIVHI = (round(1/(FSample*200E-9))-1.75) >> 8);
DIVLO =(round(1/(FSample*200E-9))-1.75) & 255);
( so FSample = 1/(200E-9 * (DIVHI:DIVLO + 1.75)) )
Where FSample is in Hz.
This gives:
FSample min = 305.1Hz (count=0x3FFF)
FSample max = 250KSPS (count=0x12 nTIMING=1 AD132)
500KSPS (count=0x08 nTIMING=1)
or 625KSPS (count=0x06 nTIMING=1 AD1x6 only)
For the AD1x5 and AD1x6 the input bandwidth of the card is
restricted to around 250KHz to aid with anti-aliasing requirements.
For the AD132 it is limited to around 120KHz. If slower sample
rates are used and signals greater than the Nyquist rate are present in
the input signal, some form of off card low-pass filtering may be
required. This filtering can be as simple as placing resistance in line
with the input signal. When adding series resistance, don’t forget
that you will also tend to degrade the card’s accuracy and induce
offset errors due to bias currents etc