ELAN DIGITAL SYSTEMS HD717 User manual

Elan Digital Systems Ltd. 1 HD717 USER’S
GUIDE
ELAN DIGITAL SYSTEMS LTD.
LITTLE PARK FARM ROAD,
SEGENSWORTH WEST,
FAREHAM,
HANTS. PO15 5SJ.
TEL: (44) (0)1489 579799
FAX: (44) (0)1489 577516
e-mail: [e-mail]
website: www.pccard.co.uk
HD717 PC-CARD USER’S GUIDE
ALSO COVERS HD712,HD713
REVISION HISTORY
ISSUE PAGES DATE NOTES
1 59 11.04.97 FIRST ISSUE
2 60 28.04.97 NEW FEATURES
3 60 09.09.97 SCC DATA/CLK TIMING NOTE p15
4 58 28.01.98 SIMPLIFY PCCARDGO TEXT
5 58 25.03.98 RS422 ENABLE BIT (GSR2)
6 52 24.07.98 REMOVED SOFTWARE SECTION
TO PCCARDGO.DOC
7 52 10.08.98 HD712 ADDED
8 52 16.04.99 HD713 ADDED
9 52 29.01.01 LOOPBACK CONNECTIONS
10 52 11.04.02 LOOPBACK CONNECTIONS
11 55 23.04.02 Figure 3.1.3-1 Added

Elan Digital Systems Ltd. 2 HD717 USER’S
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CONTENTS
1. OVERVIEW..................................................................................................5
2. ABOUT THE HD717 ....................................................................................6
2.1 THE SERIAL COMMS CONTROLLER........................................................6
2.2 LOW RATE DATA INTERFACES.................................................................7
2.3 DIGITAL I/O INTERFACE..............................................................................9
3. CONTROLLING THE HD717.....................................................................10
3.1 SCC....................................................................................................................10
3.1.1 SCC I/O PORTS...........................................................................................10
3.1.2 SCC BASIC CONFIGURATION................................................................11
3.1.3 SCC TX/RX CLOCK SELECTION............................................................14
3.1.4 SCC TRANSMIT PROCEDURE................................................................17
3.1.5 SCC RECEIVE PROCEDURE....................................................................21
3.1.6 RS485 SUPPORT (Issue 2(+) HD717 & HD712,713 Cards Only).............23
3.2 LOW RATE DATA..........................................................................................24
3.2.1 TRANSMIT..................................................................................................24
3.2.2 RECEIVE.....................................................................................................28
3.3 HANDLING INTERRUPTS............................................................................31
3.4 USING THE DIGITAL I/O PINS...................................................................35
4. HD717 REGISTER INTERFACE ...............................................................36
4.1 SCC CONTROL (IOBASE+0).........................................................38
4.2 SCC DATA (IOBASE+1).....................................................................38
4.3 IPR READ / IMR WRITE (IOBASE+2).....................................39
4.4 LRD RX LO READ / TX LO WRITE (IOBASE+3)..............40
4.5 LRD RX HI READ / TX HI WRITE (IOBASE+4)................40
4.6 SUB REG DATA (IOBASE+5).........................................................41
4.7 SUB REG IDX WRITE ONLY (IOBASE+6)............................41
4.8 RX 4K FIFO READ / TX 4K FIFO WRITE (IOBASE+7).43

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4.9 PCR (SUB REG 0)..................................................................................44
4.10 LBG (SUB REG 1)................................................................................45
4.11 SCS (SUB REG 2).................................................................................46
4.12 DIDI READ / DIDO WRITE (SUB REG 3)............................47
4.13 DIR (SUB REG 4).................................................................................47
4.14 SCR (SUB REG 5)................................................................................48
4.15 MSR READ ONLY (SUB REG 6)................................................49
4.15 IMR READ ONLY (SUB REG 7).................................................50
5. HARDWARE SPECIFICATION..................................................................51
5.1 PINOUT.............................................................................................................51
5.2 POWER CONSUMPTION..............................................................................53
5.3 MECHANICAL................................................................................................53
5.4 ENVIRONMENTAL........................................................................................53
5.5 LOOP BACK CONNECTIONS FOR TEST SOFTWARE.........................53
6. SOFTWARE...............................................................................................54
6.1 UNIVERSAL DRIVER....................................................................................54
6.2 C SOURCE CODE...........................................................................................54
7. OPERATIONAL PRECAUTIONS .............................................................55

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Disclaimer
This document has been carefully prepared and checked. No responsibility can be
assumed for inaccuracies. Elan reserves the right to make changes without prior notice
to any products herein to improve functionality, reliability or other design aspects.
Elan does not assume any liability out of the use of any product described herein;
neither does it convey any licence under its patent rights not the rights of others. Elan
products are not authorised for use as components in life support services or systems.
Elan should be informed of any such intended use to determine suitability of the
products.
Source code supplied with Elan PC-Cards is provided “as-is” with no warranty, express
or implied, as to its quality or fitness for a particular purpose. Elan assume no liability
for any direct or indirect losses arising from use of the supplied code.
Copyright © 1996,1997 Elan Digital Systems Ltd.

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1. OVERVIEW
Before using the HD717, take some time to read the section
“OPERATIONAL PRECAUTIONS”.
The HD717 card is a general purpose Serial Comms PC-Card with
the following features:
•Z85233 Serial Comms Control device (SCC) capable of both
synchronous and asynchronous protocols. SDLC mode can
operate at up to 4MBits / sec (also known as HDLC mode)
• 16MHz base clock rate to SCC (12MHz:HD712, 13MHz:HD713)
•Flexible clock routing network for synchronous modes, including
card generated 4,2,1 or 0.5MBits/sec clock to SCC’s TX and RX
clock pins (12,3,1.5,0.75MBits/s on HD712 or 16,4,2,1,0.5MBits/s on Iss2.01+
HD717, 13,3.25,1.625,0.8125MBits/s on HD713).
•RS422 interface drivers and receivers for SCC
•Issue 2+ HD717 and all HD712,713 cards have support for
RS485 shared data bus scheme
•4Kx8 transmit and receive FIFOs to decouple PC from high
speed transfers
•Bipolar RZ input and output to ARINC 717 spec with bit rates
from 768 to 6144 bits/sec
•Harvard Biphase (or “FM1”) input and output to ARINC 717
spec with bit rates from 768 to 6144 bits/per sec
•8 digital I/O lines with programmable 47K pull up-down.
This guide aims to familiarise you with the way that the HD717
works and so will help you to maximise its performance in your
application.
Elan will be happy to quote for either customisation of the HD717 if
its exact specifications do not quite meet your needs, or to create
complete application software.

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2. ABOUT THE HD717
2.1 THE SERIAL COMMS CONTROLLER
The HD717 uses the “industry standard” 85233 Serial Comms
Controller chip (or SCC). This device contains all the logic required
to handle a variety of synchronous and asynchronous serial
protocols. Its operation is not detailed in this document due to its
complexity and the possibility of data book transcription errors.
Instead the reader is strongly advised to obtain the latest User’s
Guide for the generic family of controllers from Zilog Inc. The full
title of the guide is:
“SCC USER’S MANUAL, Zilog Inc, Part No. DC-8293-02”
This is referred to as [REF 1] in this document.
In the UK, Zilog can be reached at (44) (0)1628 39200.
The HD717 maps the SCC directly into the PC’s IO space and so the
device appears just as it would if it were on say an ISA card or PCI
card. The only fundamental difference in the way the SCC operates
on the HD717 is that the data for TX and RX is buffered by 4096 x 8
FIFOs. On an ISA card, it is common to use the SCC in DMA
mode, where two DMA channels are used (one for TX and one for
RX data paths). This is precluded in PCMCIA as only one physical
DMA channel is possible. To overcome this, the HD717 uses
control logic in the card to act like a DMA controller to the SCC.
This means that the SCC must be set to operate in DMA mode even
though the source and destination for the DMA requests never leave
the PC card itself. Instead the data transfers operate transparently (to
the PC) into and out-of the FIFOs. The PC is notified by interrupt
when either the TX FIFO falls below half full or the RX FIFO rises
above half full or the SCC signals a “special condition” e.g. End Of
Message in synchronous modes.
The 4K FIFO buffers effectively shadow normal SCC operations: it
is still possible for the PC to directly read and write the SCC’s own
internal data buffers although doing so must be considered carefully
as accessing the SCC data registers directly may cause missed DMA

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cycles to the 4K FIFOs (the read or write acts as the DMA
acknowledge).
The following block diagram may help to clarify the role of the 4K
FIFOs in the system:
OSC:
16MHz HD717
12MHz HD712
TRxC PIN
OSC÷4,8,16,32MHz
TXClkExt
TX CLK IN
RX DATA
TX DATA
TX CLK OUT
RXClkExt
RTxC PIN
RX CLK IN
RX CLK OUT
SCC
4K
FIFO
RX
4K
FIFO
TX
LOGIC
PIO
PIO
DMA
DMA
PC
RS422
PCLK PIN
Rterm=220ohms
TRxCEn
HD712/Iss2.01+HD717
OSC÷4,8,16,32MHz
Figure 2.1-1 Functional Block Diagram of SCC + FIFOs
2.2 LOW RATE DATA INTERFACES
The HD717 provides inputs and outputs for two of the common
ARINC 717 serial data protocols, namely Bipolar Return-to-Zero
and Harvard Biphase (or FM1). The input and output circuits
function independently except that i) the encoding mode applies to
both input and output at the same time (i.e. can’t send BRZ and
receive Biphase simultaneously). ii) the input and output data rates
are derived from the same clock so that the send and receive circuits
always run at the same bit rate.
Data rates are software programmable and cover the “commonly”
used bit/sec settings of 768,1536,2304,3072,6144.

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The waveshapes for the two protocols are summarised below. Refer
to the ARINC specification for a more complete definition.
BIPOLAR R-Z
LINE A to LINE B +10V
-10V
0V
1 10 0 0
+5V
-5V
0V
+5V
-5V
0V
LINE A to GND
LINE B to GND
BIT-CELL
HARVARD BIPHASE
LINE A to LINE B +5V
-5V
0V
1 10 0 0
+5V
-5V
0V
+5V
-5V
0V
LINE A to GND
LINE B to GND
BIT-CELL
As can be seen, there is sufficient clocking information in both
waveforms to allow complete asynchronous reception without the
source clock present. The BRZ code is inherently simple to decode
due to its “transition-per-bit” nature. Harvard Biphase is more
complex to decode and relies on there being at least one zero in the
data stream to ensure the receiver is correctly in sync with the
transmitter. The HD717 provides a status bit and various control

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signals to control how it will behave when it first receives Biphase
data.
Note that the transmitter circuits in the HD717 are also capable of
operating in NRZ and FM0 modes. The receiver can cope with FM0
input data but cannot receive NRZ data (NRZ is simply generated as
“A-B”=5V ⇒Logic ‘1’, “A-B”= -5V ⇒Logic ‘0’).
The output drivers used for the Low Rate Data are slew rate limited
as required by ARINC specifications (typical 10-20us 10-90%).
Additionally, they are series terminated (in both A and B circuits)
with 22ohm resistors. This aids in driving highly capacitative loads
(i.e. very long cables).
2.3 DIGITAL I/O INTERFACE
8 Digital I/O drivers are provided on the HD717 to use as general
purpose control outputs and/or status monitoring inputs. The I/O
pins are logically grouped together in clusters of 1,1,2,4 I/O pins
(i.e. total = 8). These groupings define how the pins are set to inputs
or outputs. The groupings allow for any number of inputs or outputs
by using the correct combination of clusters. Additionally, each I/O
pin is “pulled” via a 47K resistor to a global control signal called
“DIOPull”. This signal can be set low or high in software to affect a
pull up or a pull down. The default (power-on) state is down.
The I/O pins are clamped to the internal Vcc and ground rails using
fast schottky diodes. This affords a good level of protection against
static damage.

Elan Digital Systems Ltd. 10 HD717 USER’S
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3. CONTROLLING THE HD717
3.1 SCC
3.1.1 SCC I/O PORTS
The control registers of the SCC are mapped for read and write at
IOBASE+0. The data registers (i.e. TX and RX data buffers) are
mapped at IOBASE+1. It is not recommended to directly access the
SCC data registers unless you intend to run the serial data at very
low rates. It is far easier to allow the SCC to DMA its data to/from
the 4K FIFOs and configure the SCC to create interrupts to notify
the PC to collect or deposit data to the FIFOs as required.
The SCC control registers use a two access process. The first access
to IOBASE+0 is a write, which contains the “pointer” to the SCC
internal register to read or modify. The second access will be a read
or write to IOBASE+0 to read or write to the register pointed to by
the first access. The two access sequence must be maintained by
software to ensure that incorrect accesses to internal registers are not
made. The only exception is when the first write cycle is to execute
one of the “commands” that are controlled by WR0 (Write Register
0 in Zilog terms). Here, no second cycle is required as the data is
essentially implicit in the command. Refer to [REF 1] for details.

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3.1.2 SCC BASIC CONFIGURATION
The following table shows the required SCC set-up to enable the
HD717 to operate correctly. Bits marked as ‘0’ or ‘1’ must be as
such, those marked as ‘x’ can take a state appropriate to the
configuration needed. Underlined bit states are recommended
recognising that other modes of operation are possible.
REGISTER REQUIRED STATE
(binary MSB...LSB)
76543210
WR1 11111x01 = F9h
Ext/status MIE = ON
TX int en = OFF
RX int on special conditions
DMA on RX = ON
Select RX DMA mode
Master RX DMA en = ON*1
*1 Set to on when s/w is ready to
RX...see also HD717 PCR for DMA
enabling.
WR2 xxxxxxxx = xxh
WR3 xxxxxxx1 = x1h
RX en = ON*1
*1
Set to on when s/w is ready to
RX...see also HD717 PCR for DMA
enabling.
WR4 xxxxxxxx = xxh
WR5 xxxxxxxx = xxh
WR6 xxxxxxxx = xxh
WR7 xxxxxxxx = xxh
WR7’ 0x010x11 = 13h
Auto TX flag (SDLC) = ON
Auto EOM reset = ON
RX DMA every char
DMA deassertion is fast
TX DMA every char
Must be 0

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WR8 xxxxxxxx = xxh
WR9 xx1x1x1x = 2Ah
No vector on INTACK
MIE = ON*1
Software INTACK mode = ON
*1
Set to on when s/w is ready to
service interrupts from the SCC...see
also HD717 PCR, IPR & IMR f
or
interrupt enabling / acknowledging,
status and masking.
WR10 xxxxx0xx = x0h
Send Flag on TX underrun
WR11 000010xx = 08h
Set TRxC pin as an INPUT
Select TRxC pin as TX clock
Select RTxC pin as RX clock
RTxC is NOT a crystal osc
NB: The TRxC pin on the SCC is wired
to a logic driver circuit (the output
of the TX clock select MUX on the
card). Therefore it MUST be set to an
input on the SCC if SCS2 is high in
the SCS register.
NB: The sources for the TX and R
X
clock can also be set to the BRGen or
DPLL of the SCC. The SCC does not
have to use the external clock
sources. When using DPLL, observe the
maximum data rates (Zilog data sheets)
for the SCC to be able to recover the
clock from the data stream.
See a
lso the HD717 SCS register for
the external clock selection options.
WR12 xxxxxxxx = xxh
WR13 xxxxxxxx = xxh

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WR14 xxxxx1xx = x4h
Select TX DMA mode
WR15 11000101 = C5h
Use to access WR7 or WR7'
No zero count int on BRGen
Enable status FIFO in SCC
No DCD int
No SYNC/hunt int
No CTS int
Enable int on TX underrun/EOM
Enable int on RX break/abort

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3.1.3 SCC TX/RX CLOCK SELECTION
As well as being able to select various clock sources for the SCC via
WR11, the HD717 also pre-muxes both the TX and RX clocks to
allow even greater flexibility on how the card is used in synchronous
systems. Refer to Figure 2.1-1 for a block diagram showing the
clock routing.
Various HD717 control registers effect the clock selection, they are
summarised here:
REGISTER BIT FUNCTION
SCS0 Together form a 2-bit selection code for the
frequency applied to the SCC’s TRxC & RTxC
pins when the HD717 derived clock is selected
(SCS6/7):
SCS1 SCS[1:0]=00: 4MHz (default)
SCS[1:0]=01: 2MHz
SCS[1:0]=10: 1MHz
SCS[1:0]=11: 0.5MHz
SCS2 TRxCEn. This bit allows the HD717 driver
connected to the SCC’s TRxC pin to be tri-
stated. When set high, the HD717 drives the
SCC. When low, the SCC can be programmed
to output on its TRxC pin if required e.g to
output its internal baud generator or DPLL clk.
SCS3 EdgeSel. This bit allows the HD717 clock
divider to use either the +ve or -ve edge of the
master 16MHz clock supplying the SCC. The
default state is 0: +ve edge. This bit should be
left at the default state.
SCS4 SCCPClkEn. This bit acts as a master enable
for the SCC’s master oscillator (PCLK). The
default state is 0: DISABLE PCLK. When
enabled, the SCC is clocked at 16MHz. UNTIL
THIS BIT IS SET, NO OPERATION WITH
THE SCC WILL BE POSSIBLE.

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SCS5 SCCTRClkEn. This bit acts as a master enable
for the SCC’s external clocks. The default state
is 0: DISABLE TX & RX clocks to SCC.
When enabled, the TRxC and RTxC pins are
driven from the HD717 derived clock or from
the off-card clock inputs. For the HD712/713
and Iss2.01+ HD717 cards this bit serves an
extra function: when an external source is
selected via SCS6 or 7 setting this bit high will
select the clock connected to T/RXCLKIN+/-
but setting it low will select the master OSC
that is also used to drive the PCLK pin on the
SCC. This allows greater flexibility in the baud
rates available when the SCC is used in async
mode. Note that when SCS5 is low only one of
two states can be selected for either the TRxC
or RTxC pins: disabled or OSC...there is no
way to route OSC to TRxC and an external
clock to RTxC simultaneously. See figure
3.1.3-1.
SCS6 SCCTXClkExt. When low, the TRxC SCC pin
is driven from the HD717 derived clock
(4,2,1,0.5MHz). When high, the SCC pin is
driven from the TXCLKIN+/-RS422 inputs to
the card (Pins 5&6) (For HD712,713 read note
for SCS5 bit)
SCS7 SCCRXClkExt. When low, the RTxC SCC pin
is driven from the HD717 derived clock
(4,2,1,0.5MHz). When high, the SCC pin is
driven from the RXCLKIN+/-RS422 inputs to
the card (Pins 11&12) (For HD712,713 read
note for SCS5 bit)

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Figure 3.1.3-1 Clock Routing Internal to HD717
Note that the SCC’s TRxC and RTxC pins are buffered to RS422
levels and driven off card as TXCLKOUT+/-(Pins 3 & 4: this is
TRxC), and as RXCLKOUT+/-(Pins 9 & 10: this is RTxC).
It is vital for correct opperation that the timings for the TX/RX clock
and data follow the requirements laid down in the Zilog SCC data
sheets. In a synchronous system there must be sufficient setup and
hold time for the data relative to the clock. In the external clock
case, the HD717 passes clock and data through the same type of
RS422 receiver / transmitter chips. This means that no significant
extra skew between clock and data is added. Typically, 0ns of setup
and 50ns of hold are required at the SCC in receive relative to the
RX clock edges. In transmit, the delay between TX clock edges and
data changing is 80ns.
Be aware that some combinations of data and clock will not work
reliably when used in a loop-back test mode. For example, clocking
the TX and RX clocks from the same source (internal to the card)
and sending the TX data “out” of the card through two pieces of
wire and back “in” to the card may not work properly at 2 or 4MHz.
This is because the RX data is grossly skewed relative to the RX
clock because the data has passed through two RS422 transcievers
but the clock has not.
SCS6
SCS7
SCS5
D0
D1
D2
D3
Y
S1
S0
1
2
3
4
6
7
5
D0
D1
D2
D3
Y
S1
S0
1
2
3
4
6
7
5
Y
1
TXCLKIN
RXCLKIN
TXCLK
RXCLK
16MHZ
16MHZ
0.5/1/2/4MHz

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3.1.4 SCC TRANSMIT PROCEDURE
The HD717 is intended to operate in a mode where interrupts from
the SCC only occur on special conditions. All data transfers are
performed by the SCC DMAing the data out of the TX 4K FIFO. In
this way the PC is able to load the 4K FIFO with TX data, configure
the SCC, HD717 and finally enable the HD717 DMA controller.
The TX data will automatically be sent without further intervention
from the PC unless the message length is greater than 4K. The
following flow diagram summarises the steps to transmit data:
DISABLE HD717
TX DMA
⇓⇓
CONFIGURE SCC AS
REQUIRED
WITH TX DMA ENABLED
AND
TX ENABLED
⇓⇓
LOAD TX 4K FIFO
WITH
TX DATA
⇓⇓
ENABLE HD717 TX DMA
⇓⇓
⇓⇓
The above process could generate an interrupt request for three
reasons:
1. The SCC signals that it has completed the message (EOM)
2. The HD717 signals that the TX 4K FIFO has fallen below half full
(only applies if original message was 2048 or more bytes long)
3. The HD717 signals that the TX 4K FIFO has fallen to empty
The HD717 will cease to acknowledge TX DMA requests from the
SCC when the TX 4K FIFO is empty. This will force the SCC to
terminate the message and so complete the transfer.

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Remember that before re-loading the TX 4K FIFO with the next
message to send, the HD717 TX DMA must be disabled. If this is
not done the HD717 will start honouring TX DMA requests as soon
as the FIFO holds data and there is a possibility (at high bit rates)
that the SCC will empty the TX 4K FIFO faster than it is being filled
by the PC. This could lead to a TX Underrun at the SCC causing the
premature termination of the message.
For messages longer than 4096 bytes, the Interrupt Service Routine
in the PC must detect that more data must be loaded to the TX 4K
FIFO (i.e. the next block of the message). It should use the 8086
“REP OUTSB” command to rapidly copy the TX data from its local
buffer to the TX 4K FIFO. The amount of data to copy depends on
the message length remaining, but at most 2048 bytes at a time can
be transferred (remember that the IRQ occurs when the TX 4K FIFO
is less than half full). For even greater efficiency, the ISR can also
inspect the TX 4K FIFO Full, Half Full and Empty flags. This
would allow the ISR to decide to write more data if required in an
attempt to better fill the TX 4K FIFO. If this technique is used
remember that once the initial 2K block has been written by the ISR,
every subsequent byte write must made conditional on the Full flag
being high (else the ISR could write “beyond” full). At high data
rates, this extra flag check could lead to the ISR filling the FIFO
more slowly than it is being emptied by the SCC which could
ultimately lead to a FIFO empty condition and the ISR getting
“stuck” trying to fill an ever emptying FIFO ! In such a case, use
only the single 2K block write and then exit the ISR.
HD717 control / status registers that relate to an SCC TX are listed
below:
REGISTER BIT FUNCTION
PCR0 MIRQEn: Set to ‘1’ to allow any interrupt
through to the PC
PCR1 IRQInService: Use this bit in the ISR routine
to lock the IRQ state, so indicating that an IRQ
is being serviced by software. Set the bit to ‘1’
to lock the IRQ state as the first action of the
ISR. Return it to ‘0’ as the last action of the
ISR (this may immediately re-activate the IRQ
to the PC).

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PCR2 TXDMAEn: Set to ‘1’ to allow the HD717 TX
DMA controller to honour SCC TX DMA
requests. The TX DMA controller will only
“run” if the TX 4K FIFO contains >0 bytes of
data.
IMR0 MaskSCCInt: Set to ‘1’ to mask interrupts
from the SCC. Set to ‘0’ to allow them.
IMR3 MaskTXFIFOHInt: Set to ‘1’ to mask
interrupts from the TX 4K FIFO as it falls
below half full. Set to ‘0’ to allow them.
IMR5 MaskTXFIFOEInt: Set to ‘1’ to mask
interrupts from the TX 4K FIFO as it falls to
empty. Set to ‘0’ to allow them.
IPR0 SCCIntPending: Reads back as a ‘1’ when
there is an interrupt pending from the SCC.
The SCC must be set to use a software
INTACK mode (WR9) so that the SCC’s
interrupt line is de-asserted when RR2 is
accessed to determine the reason for the SCC
interrupt.

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IPR3 TXFIFOHIntPending: Reads back as a ‘1’
when there is an interrupt pending due to the
TX 4K FIFO falling below half full. The
interrupt is cleared by a PC write to the TX 4K
FIFO. If this is not appropriate (i.e. there is no
more data to TX) then IMR3 should be set to
‘0’ ‘1’ ‘0’ to clear the interrupt. If messages
are always less than 4096 bytes then it is best to
always mask these interrupts (IMR3=‘1’).
IPR5 TXFIFOEIntPending: Reads back as a ‘1’
when there is an interrupt pending due to the
TX 4K FIFO falling to empty. The interrupt is
cleared by setting IMR5 to ‘0’ ‘1’ ‘0’.
MSR0 TXFIFOEmpty: Status of the TX 4K FIFO’s
empty flag (active low).
MSR1 TXFIFOHalf: Status of the TX 4K FIFO’s half
full flag (active low).
MSR2 TXFIFOFull: Status of the TX 4K FIFO’s full
flag (active low).
While the HD717 is transmitting data from the TX 4K FIFO via the
SCC, the PC can still access the SCC’s registers. A bus arbitrator in
the HD717 makes sure that the PC and SCC accesses to the
HD717’s internal bus do not clash. However, do not access the SCC
“too often” whilst TX DMA is enabled because the HD717 will
simply run out of time trying to arbitrate both sources (which will
make the SCC underflow and terminate the frame prematurely).
Accessing (reading) one SCC register every 50us is OK; every 1us is
not ! Also bear in mind that the situation gets worse if the HD717 is
both transmitting AND receiving data at the same time. Again the
arbitrator is working to share the bus between all sources and so the
potential to “run out of time” is greater in this instance (still the 50us
holds good).