Elma JetKit-3010 User manual

Elma User Manuals:
JetKit-3010
BACKPLANES
CHASSIS PLATFORMS
EMBEDDED BOARDS
EMBEDDED COMPUTING SOLUTIONS
POWER SOLUTIONS
©2022 Elma Electronic A20220804

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Revision History
Revision
Description
Date
By
1.00
Initial release
2022-08-04
FF
Preface
Disclaimer
Neither Elma Electronic nor any subsidiary will assume any responsibility for damage resulting from improper
use of its products or failure to comply with the manuals and the applicable rules and regulations.
Our General Terms and Conditions apply. You can download the current version of the General Terms and
Conditions from our website at www.elma.com by clicking on the link at the bottom of every page.
Copyright
All rights reserved.
All marks and names mentioned herein are trademarks or registered trademarks of the respective owners.
Copyright © 2022 Elma Electronic GmbH, Pforzheim, Germany.
Information subject to change without notice!

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Contents
Revision History ........................................................................................................... 3
Preface ......................................................................................................................... 3
Contents ....................................................................................................................... 4
Figures ......................................................................................................................... 6
Tables........................................................................................................................... 7
1Introduction .......................................................................................................... 9
1.1 Symbols Explanation ............................................................................................. 9
1.2 Electrostatic Discharge (ESD) ................................................................................. 9
2Hardware ............................................................................................................ 10
2.1 Overview ............................................................................................................10
2.2 NVIDIA®Xavier™ Software ...................................................................................10
2.3 Technical Specification ..........................................................................................10
2.4 Features .............................................................................................................12
2.4.1 Volta GPU ..................................................................................................12
2.4.2 Tensor Cores..............................................................................................13
2.4.3 Carmel CPU Complex ..................................................................................14
2.4.4 Memory Subsystem ....................................................................................15
2.5 Board Diagrams ...................................................................................................16
2.5.1 Block Diagram............................................................................................16
2.5.2 Front Panel ................................................................................................17
2.5.3 Board assembly ..........................................................................................18
2.5.4 Baseboard layout........................................................................................19
2.5.5 Mezzanine Layout .......................................................................................21
3Functional Description ........................................................................................ 22
3.1 CompactPCI Serial operation .................................................................................22
3.2 PCI Express operation...........................................................................................22
3.2.1 Overview ...................................................................................................22
3.2.2 PCI Express clock .......................................................................................23
3.2.3 PCI Express reset .......................................................................................23
3.3 Board Management Controller (BMC) ......................................................................23
3.3.1 Overview ...................................................................................................23
3.3.2 Command Line Interface (CLI) .....................................................................24
3.3.3 Firmware Update ........................................................................................25
3.4 USB Type C interface management ........................................................................28
3.5 Power Management ..............................................................................................30
3.6 Board Reset.........................................................................................................30

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3.7 Rear-I/O backplane support...................................................................................31
3.8 Board interfaces...................................................................................................31
3.8.1 USB Type C connectors ...............................................................................31
3.8.2 MicroUSB connector ....................................................................................32
3.8.3 MicroSD/UFS card slot .................................................................................32
3.8.4 Mezzanine connector ...................................................................................33
3.8.5 MiniHDMI connector ....................................................................................34
3.8.6 Ethernet connector .....................................................................................34
3.8.7 USB2.0 connector .......................................................................................35
3.8.8 Front Panel LEDs ........................................................................................35
3.8.9 Front Panel Push Buttons .............................................................................36
3.8.10 BMC Programming header ...........................................................................36
3.8.11 CompactPCI Serial connectors ......................................................................37
4Configuration ...................................................................................................... 39
5Mezzanines.......................................................................................................... 40
6Ordering Information .......................................................................................... 40
7Technical Support ............................................................................................... 41
7.1 Contact...............................................................................................................41
7.2 Returning Defective Products .................................................................................41

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Figures
Figure 1 - Matrix processing................................................................................................ 13
Figure 2 - Simplified Block Diagram ..................................................................................... 16
Figure 3 - Mezzanine Block Diagram .................................................................................... 16
Figure 4 - Front Panel ........................................................................................................ 17
Figure 5 - Board with NVIDIA®module, heat sinks and mezzanine .......................................... 18
Figure 6 - Board with NVIDIA®module, without heat sinks and mezzanine ............................... 18
Figure 7 - Baseboard top components .................................................................................. 19
Figure 8 - Board bottom components ................................................................................... 19
Figure 9 - Mezzanine top components .................................................................................. 21
Figure 10 - Mezzanine bottom components ........................................................................... 21
Figure 11 - Bootloader Main Window .................................................................................... 26
Figure 12 - Bootloader application with selected Firmware File ................................................ 26
Figure 13 - Bootloader application with selected MCU architecture ........................................... 27
Figure 14 - Bootloader serial port settings ............................................................................ 27
Figure 15 - Bootloader application configured for BMC update ................................................. 28
Figure 16 - 4 pole DIP switch .............................................................................................. 39

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Tables
Table 1 - Technical Specification.......................................................................................... 10
Table 2 - GPU Operation..................................................................................................... 12
Table 3 - CPU Operation ..................................................................................................... 14
Table 4 - LPDDR4x Memory Bus .......................................................................................... 15
Table 5 –Board main components....................................................................................... 20
Table 6 –Mezzanine main components ................................................................................ 21
Table 7 - CompactPCI Serial Sideband Signals ...................................................................... 22
Table 8 - BMC CLI serial port settings .................................................................................. 24
Table 9 - Measured board voltages ...................................................................................... 25
Table 10 - IO Expander IOs for PD controller configuration / indication .................................... 29
Table 11 - PD controller current advertisement ..................................................................... 30
Table 12 - USB-C 1 pinout .................................................................................................. 31
Table 13 - USB-C 1 pinout .................................................................................................. 31
Table 14 - MicroUSB pinout ................................................................................................ 32
Table 15 - MicroUSB interfaces............................................................................................ 32
Table 16 - MicroSD/UFS card slot pinout .............................................................................. 32
Table 17 –Mezzanine connector pinout legend...................................................................... 33
Table 18 - Mezzanine Connector pinout ................................................................................ 33
Table 19 - MiniHDMI pinout ................................................................................................ 34
Table 20 - RJ45 pinout ....................................................................................................... 34
Table 21 - RJ45 LED indication ............................................................................................ 34
Table 22 - USB2.0 pinout ................................................................................................... 35
Table 23 - Front Panel LEDs................................................................................................ 35
Table 24 - LED GPIO control ............................................................................................... 35
Table 25 –Push Buttons..................................................................................................... 36
Table 26 - BMC Prog pinout ................................................................................................ 36
Table 27 - CompactPCI Serial pinout legend ......................................................................... 37
Table 28 - P1 CompactPCI Serial connector .......................................................................... 37
Table 29 –P2 CompactPCI Serial connector .......................................................................... 38
Table 30 –P5 CompactPCI Serial connector .......................................................................... 38
Table 31 –P6 CompactPCI Serial connector .......................................................................... 38
Table 32 - DIP Switch SW3 Functionality .............................................................................. 39
Table 33 - DIP Switch SW5 Functionality .............................................................................. 39
Table 34 - DIP Switch SW6 Functionality .............................................................................. 39
Table 35 - Ordering Information .......................................................................................... 40

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1Introduction
1.1 Symbols Explanation
This symbol indicates danger of injury for user or risk of damage to product or
components.
This symbol indicates danger for electronic components, which can be damaged
or destroyed by discharge of electrostatic electricity.
This symbol indicates information to specific product configuration or settings
of hardware.
1.2 Electrostatic Discharge (ESD)
This product includes high sensitive microcontrollers and semiconductor products that can be
damaged by electrostatic discharge (ESD).
Electrostatic discharge can destroy static-sensitive devices or micro-circuitries. Damage due to
inappropriate handling is not covered by the warranty.
The following precautions must be taken:
Do not open the protective conductive packaging until you have read the following, and are at an
approved anti-static workstation.
Pay attention to a good grounding of persons, the workstation and devices around the system, tools
and packaging.
Transport the system or other electrostatic sensitive parts in a static safe container (box or bag).
Keep the parts in their container until the workspace around is ESD-safe.
Use a conductive wrist strap attached to a good earth ground.
Use anti-static mats on all surfaces in the workspace

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2Hardware
2.1 Overview
The Elma JetKit-3010 is based on the NVIDIA®Jetson AGX Xavier™Industrial System-on-Module.
It provides the ability to integrate the NVIDIA®Jetson AGX Xavier™seamlessly into existing
CompactPCI Serial infrastructure. With its industry leading performance, power efficiency,
integrated deep learning capabilities and rich I/O, the NVIDIA®Jetson AGX Xavier™enables
emerging technologies with compute-intensive requirements. Designed for applications converging
on artificial intelligence (AI), computer vision (CV) and advanced graphics, the AGX Xavier™is
ideal for (but not limited to): Intelligent Video Analytics (IVA), Robotics, Virtual Reality (VR),
Augmented Reality (AR), Portable Medical Devices and autonomous driving.
2.2 NVIDIA®Xavier™Software
Intentionally, the design of the JetKit-3010 was oriented on the design of the NVIDIA®AGX
Xavier™Developer Kit. This allows Software reutilization between platforms. Main differences
(influencing the Device Tree) are leaving out the audio codec and usage of a different USB type C
power delivery controller. The modified device tree file can be provided on request.
For more information on the NVIDIA®Xavier™module, please consult the NVIDIA®online
documentation:
Jetson™Download Center:
https://developer.nvidia.com/embedded/downloads
NVIDIA®Jetson™Linux Developer Guide:
https://docs.nvidia.com/jetson/l4t/
Getting Started:
https://developer.nvidia.com/embedded/learn/getting-started-jetson
2.3 Technical Specification
The Elma JetKit-3010 is based on the NVIDIA®AGX Xavier™Industrial module and inherits the
module’s features. The module adds further functionality and extendibility as well as it adapts the
interface to the CompactPCI Serial infrastructure. The technical specification of the JetKit-3010 can
be found in Table 1.
Table 1 - Technical Specification
Features
Specifications
SoC
GPU
Volta GPU
Tensor Cores
End-to-end lossless compression
Tile Caching
OpenGL® 4.6
OpenGL ES 3.2
Vulkan™ 1.0
CUDA® 10
CPU
Carmel CPU Complex
ARMv8.2 (64-bit) heterogeneous multi-processing (HMP) CPU
Architecture
Dual-core CPU clusters connected by a high-performance system
coherency interconnect fabric
L3 Cache: 4MB (shared across all clusters)
NVIDIA®Carmel (Dual-Core) Processor: L1 Cache: 128KB L1
instruction cache (I-cache) per core; 64KB L1 data cache (D-cache)
per core
L2 Unified Cache: 2MB per cluster

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Features
Specifications
Memory
Main Memory
256-bit DRAM interface
Secure External Memory Access Using TrustZone Technology
System MMU
Memory Type: LPDDR4x
Memory Size: 32GB
Storage
eMMC 5.1 Flash Storage
Bus Width: 8-bit
Maximum Bus
Frequency: 200MHz (HS400)
Storage Capacity: 64GB
Memory Slot
M.2 Slot size 2242
Socket 3 Type M
PCIe x4 interface
Multimedia
Display Controller
1x HDMI 2.0a/b (up to 6Gbps)
Multi-Stream HD
Video & JPEG
Video Encode:
Standards Supported: H.265 (HEVC), H.264, VP9
Video Decode:
Standards Supported: H.265 (HEVC), H.264, VP9, VP8, MPEG-4,
MPEG-2, VC-1
JPEG (Decode & Encode)
Audio Subsystem
Dedicated programmable audio processor
ARM Cortex A9 with NEON
2x I and Q baseband data channels
Industry-standard High Definition Audio (HDA) controller provides a
multi-channel audio path to the HDMI interface.
Interfaces
CompactPCI Serial
CompactPCI Serial Interface:
-Compliant with PICMG®CPCI-S.0 R1.0 CompactPCI®Serial
-Support for the following interfaces:
o1x PCI Express 3.0 x8
o1x Gigabit Ethernet
o1x USB3.0/2.0 (optional)
-12V Power Supply
-Operation in system slot and in peripheral slot
USB
2x USB Type C:
-USB 3.1 / 2.0
-USB Type C Power: max. 5V, 3A
-USB Device Mode for Programming (USB-C 1)
1x USB Type A:
-USB 2.0
-USB Type A Power: max. 5V, 0.5A
1x MicroUSB (client)
-Quad interface client chip
o1x I2C Interface
o1x JTAG Interface
o1x UART for BMC
o1x UART for NVIDIA®Xavier™
Ethernet
1x RJ45 connector
-10/100/1000Mbit/s operation
-Intel i210-AT Ethernet NIC
-Integrated LEDs for LINK/ACT and Gigabit Ethernet Indication
MiniHDMI
1x HDMI 2.0a/b (up to 6Gbps) via MiniHDMI connector
MicroSD / UFS
1x MicroSD / UFS card slot
Buttons
1x Reset Button, 1x Recovery Button
LEDs
1x Power LED, 3x User LEDs

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Features
Specifications
Interfaces
Extension
Interface
1x High-Speed Mezzanine Header:
-1x PCIe x4
-1x PCIe x2
-1x USB2.0
-4x CSI Camera Interfaces
-Utility signals
-Power
Board
Environmental
Operating Temperature: -20°C to +50°C (@40W power profile)
Storage Temperature: -20 to +85°C
Management
Integrated BMC controller handles reset management, power and
voltage monitoring
2.4 Features
1
2.4.1 Volta GPU
The same Volta GPU architecture that powers NVIDIA®high-performance computing (HPC)
products was adapted for use in Jetson AGX Xavier™series modules. The Volta architecture
features a new Streaming Multiprocessor (SM) optimized for deep learning. The new Volta SM is far
more energy efficient than the previous generations enabling major performance boosts in the
same power envelope. The Volta SM includes:
-New programmable Tensor Cores purpose-built for INT8/FP16/FP32 deep learning tensor
operations; IMMA and HMMA instructions accelerate integer and mixed-precision matrix-
multiply-and-accumulate operations.
-Enhanced L1 data cache for higher performance and lower latency.
-Streamlined instruction set for simpler decoding and reduced instruction latencies.
-Higher clocks and higher power efficiency.
The Volta architecture also incorporates a new generation of its memory subsystem and enhanced
unified memory and address translation services that increases memory bandwidth and improves
utilization for greater efficiency.
The Graphics Processing Cluster (GPC) is a dedicated hardware block for compute, rasterization,
shading, and texturing; most of the GPU’s core graphics functions are performed inside the GPC. It
is comprised of Texture Processing Clusters (TPC), with each TPC containing two SM units, and a
Raster Engine. The SM unit creates, manages, schedules and executes instructions from many
threads in parallel. Raster operators (ROPs) continue to be aligned with L2 cache slices and
memory controllers. The SM geometry and pixel processing performance make it highly suitable for
rendering advanced user interfaces; the efficiency of the Volta GPU enables this performance on
devices with power-limited environments.
Each SM is partitioned into four separate processing blocks (referred to as SMPs), each SMP
contains its own instruction buffer, scheduler, CUDA cores and Tensor cores. Inside each SMP,
CUDA cores perform pixel/vertex/geometry shading and physics/compute calculations, and each
Tensor core provides a 4x4x4 matrix processing array to perform mixed-precision fused multiply-
add (FMA) mathematical operations. Texture units perform texture filtering and load/store units
fetch and save data to memory. Special Function Units (SFUs) handle transcendental and graphics
interpolation instructions. Finally, the PolyMorph Engine handles vertex fetch, tessellation, viewport
transform, attribute setup, and stream output.
Table 2 - GPU Operation
GPU Configuration
Performance
(peak)
Max. Operating
Frequency per Core
# of TPC
CUDA Cores
Tensor Cores
4
512
64
10 TFLOPS | 30 TOPS
1.21GHz
1
Feature description taken from NVIDIA®Jetson AGX Xavier™Series System-on-Module Data Sheet.

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Features:
-End-to-end lossless compression
-Tile Caching
-OpenGL 4.6, OpenGL ES 3.2, and Vulkan 1.0
-Adaptive Scalable Texture Compression (ATSC) LDR profile supported
-DirectX 12 compliant
-CUDA support
-Iterated blend, ROP OpenGL-ES blend modes
-2D BLIT from 3D class avoids channel switch
-2D color compression
-Constant color render SM bypass
-2x, 4x, 8x MSAA with color and Z compression
-Non-power-of-2 and 3D textures, FP16 texture filtering
-FP16 shader support
-Geometry and Vertex attribute Instancing
-Parallel pixel processing
-Early-z reject: Fast rejection of occluded pixels acts as multiplier on pixel shader and
texture performance while saving power and bandwidth
-Video protection region
-Power saving: Multiple levels of clock gating for linear scaling of power
2.4.2 Tensor Cores
2
Tensor Cores and their associated data paths are custom-crafted to dramatically increase floating-
point compute throughput. Each Tensor Core performs 64 floating point FMA mixed-precision
operations per clock, eight Tensor Cores in an SM perform a total of 1024 floating point operations
per clock. Tensor Cores operate on FP16 input data with FP32 accumulation; the FP16 multiply
results in a full precision result that is accumulated in FP32 operations. Each Tensor Core provides
a 4 × 4 × 4 matrix processing array which performs the operation D = A × B + C, where A, B, C
and Dare 4 × 4 matrices. The matrix multiply inputs Aand Bare FP16 matrices, while the
accumulation matrices Cand Dmay be FP16 or FP32 matrices.
A graphical overview on this operation can be seen in Figure 1.
Figure 1 - Matrix processing
2
Tensor Cores description is taken from NVIDIA®Xavier™Series System-on-Chip Technical Reference Manual
Source: Nvidia®

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2.4.3 Carmel CPU Complex
The CPU complex (CCPLEX) is comprised of Carmel dual-core CPU clusters in a coherent multi-
processor configuration. A high-performance System Coherency Fabric (SCF) connects all CPU
clusters enabling simultaneous operation of all CPU cores (as needed) for a true heterogeneous
multi-processing (HMP) environment. The SCF also connects CPU clusters to:
-DRAM through the Memory Controller Fabric (MCF).
-Other processing and I/O blocks in the Memory Mapped I/O (MMIO) space through an ARM
Advanced eXtensible Interface (AXI).
Each CPU cluster contains two identical Carmel processors; each core includes 128 KB Instruction
(I-cache) and 64 KB Data (D-cache) Level 1 caches, a 2 MB L2 cache is shared by both cores.
Table 3 - CPU Operation
CPU Configuration
CPU Cores
Max. Operating
Frequency per Core*
CPU Cluster
L2 Cache
L3 Cache
4x dual core
8MB
4MB
8
2.03GHz
* Refer to the documentation provided with each software release for additional information on supported power modes and
CPU operation.
Features:
-NVIDIA®Dynamic Code Optimization
-10-wide Superscalar architecture
-Dynamic branch prediction with a Branch Target Buffer and Global History Buffer RAMs, a return stack
buffer, and an indirect predictor.
-Full implementation of ARMv8.2 ISA compliant architecture including:
oARMv8 TrustZone
oARMv8.0 Crypto ISA
oTrusted Memory
TZ-RAM
TZ-DRAM
Dynamic CMA VPR
GSC DRAM Carveouts
Clock Monitoring
Voltage Monitoring
Trusted Boot
Trusted Debug
oARMv8.2-FP16 support
-128 KB 4-way-associative parity protected L1 instruction cache per core
-64 KB 4-way-associative parity protected L1 data cache per core
-2 MB 16-way-associative ECC protected L2 cache per CPU cluster
-4 MB 16-way-associative ECC protected L3 cache (shared across all clusters)
-Performance Monitoring
-Interface to an external Generic Interrupt Controller (vGIC-400)
-Support for power management with multiple power domains

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2.4.4 Memory Subsystem
The Memory Subsystem (MSS) provides access to local DRAM, SysRAM, and provides a SyncPoint
Interface for inter-processor signaling. The memory subsystem supports full-speed I/O coherence
by routing requests through a scalable coherence fabric. It also supports a comprehensive set of
safety and security mechanisms.
Structurally, the MSS consists of:
1. MSS Data Backbone - routes requests from clients to the MSS Hub and responses from MSS
Hub to the clients.
2. MSS Hub - receives and arbitrates among client requests, performs SMMU translation, and
sends requests to the MCF.
3. Memory Controller Fabric (MCF) - performs security checks, feeds I/O coherent requests to
the Scalable Coherence Fabric (SCF), and directs requests to the multiple memory channels.
4. Memory Controller (MC) Channels - row sorter/arbiter and DRAM controllers.
5. DRAM IO - channel-to-pad fabric, DRAM I/O pads, and PLLs.
Xavier™series modules integrate a 256-bit wide LPDDR4X memory interface implemented as eight
32-bit channels with x16 subpartitions. The memory controller provides a single read or write
command and row address to both sub-partitions in the channel to transfer 64 bytes, but provides
three independent column address bits to each sub-partition, allowing it access different 32 byte
sectors of a GOB between the sub-partitions. It provides connections between a wide variety of
clients, supporting their bandwidth, latency, quality-of-service needs and any special ordering
requirements that are needed. The MSS supports a variety of security and safety features and
address translation for clients that use virtual addresses.
Table 4 - LPDDR4x Memory Bus
Size
Maximum Bandwidth
Maximum Bus Frequency
ECC Support
32GB
136.5GB/s
2133MHz
Enabled by software
Features:
-LPDDR4X: x32 DRAM chips
-256-bit wide data bus
-Low Latency Path and Fast Read/Response Path Support for the CPU Complex Cluster
-Support for low-power modes:
oSoftware controllable entry/exit from: self-refresh, power down, deep power down
oHardware dynamic entry/exit from: power down, self-refresh
oPads use DPD-mode during idle periods
-High-bandwidth interface to the integrated Volta GPU
-Full-speed IO coherence with bypass for Isochronous (ISO) traffic
-System Memory-Management Unit (SMMU) for address translation based on the ARM
SMMU-500
-High-bandwidth PCIe ordered writes
-AES-XTS encryption with 128-bit key
-DRAM ECC (enabled by software)
oSEC (Single Error Correction)
oDED (Double Error Detection)
oParity protection support

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2.5 Board Diagrams
The following diagrams provide an overview on the JetKit-3010 components and interfaces.
2.5.1 Block Diagram
Figure 2 and Figure 3 show the simplified block diagrams of the Elma JetKit-3010 baseboard and
the mezzanine board.
Figure 2 - Simplified Block Diagram
Figure 3 - Mezzanine Block Diagram

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2.5.2 Front Panel
Figure 4 shows the front panel of the JetKit-3010.
Figure 4 - Front Panel
PWR: Power LED –lit as soon as Power is provided for the NVIDIA®Xavier™module.
D1/D2/D3: User LEDs are controlled by GPIOs from the NVIDIA®Xavier™.
D1/2: green
D3: red
SD/UFS: MicroSD / UFS card socket
USB Client: USB client port to provide access to BMC and NVIDIA®Xavier™console ports.
HDMI: MicroHDMI connector with HDMI 2.0a/b compliant interface
USB-C 1/2: USB Type C connectors with USB3.1/2.0 interfaces
USB-C 1 provides Device functionality for programming.
Recov.: NVIDIA®Xavier™Recovery Button.
Note: For Recovery functionality, the button must be pressed during power up or
reset of the NVIDIA®Xavier™. Power up of the NVIDIA®Xavier™takes ~3
seconds after powering / reset of the board for BMC booting.
The Power LED provides indication when the NVIDIA®Xavier™is powered.
Reset: Reset Button for Board reset
USB2.0: USB2.0 interface of the NVIDIA®Xavier™
: 1000Base-T RJ45 Ethernet interface.
LINK/ACT: Link / Activity LED
GBE: 1000Mbit/s Link
M.2 ACT: Activity of M.2 module

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2.5.3 Board assembly
The images in the following show the complete board with NVIDIA®module, heat sinks and
mezzanine (Figure 5) and with NVIDIA®module, but without heat sinks and mezzanine (Figure 6).
Figure 5 - Board with NVIDIA®module, heat sinks and mezzanine
Figure 6 - Board with NVIDIA®module, without heat sinks and mezzanine

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2.5.4 Baseboard layout
In the following, Figure 7 and Figure 8 show the baseboard top and bottom view, highlighting the
positons of the main components. Table 5 lists the components by number.
Figure 7 - Baseboard top components
Figure 8 - Board bottom components
1
2
3
4
5
7
8
10
9
19
16
17
18
14
15
13
22
20
21
23
24
25
26
6
12
11

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Table 5 –Board main components
#
Side
RefDes
Description
1
Top
J1
NVIDIA®Xavier™module connector
2
Top
U44
MicroSD/UFS card socket
3
Top
J3
MicroUSB client connector
4
Top
HDMI
MiniHDMI connector
5
Top
USB2
USB type C connector (USB-C 2 interface)
6
Top
USB1
USB type C connector (USB-C 1 interface)
7
Top
SW1
Reset and Recovery Button
8
Top
J6
High-speed mezzanine connector
9
Top
P1
CompactPCI Serial P1 connector
10
Top
P2
CompactPCI Serial P2 connector
11
Top
P5
CompactPCI Serial P5 connector
12
Top
P6
CompactPCI Serial P6 connector
13
Top
SW3
DIP switch SW3
14
Top
SW5
DIP switch SW5
15
Top
SW6
DIP switch SW6
16
Top
U36
USB quad UART
17
Top
U1
Ethernet PHY
18
Top
U3
BMC
19
Top
T1
Ethernet Magnetics
20
Top
D1
PHY LED0 (Link)
21
Top
D2
PHY LED1 (ACT)
22
Top
J5
BMC Prog programming header
23
Bottom
PWR_ON
Power On LED (green)
24
Bottom
LD1
User LED 1 (green)
25
Bottom
LD2
User LED 2 (green)
26
Bottom
LD3
User LED 3 (red)