Phytec phyCORE-XC167 User manual

A product of a PHYTEC Technology Holding company
phyCORE-XC167
Hardware Manual
Edition June 2003

phyCORE-XC167
PHYTEC Meßtechnik GmbH 2003 L-623e_1
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Copyright 2003 PHYTEC Meßtechnik GmbH, D-55129 Mainz.
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Adresse: PHYTEC Technologie Holding AG
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GERMANY
PHYTEC America LLC
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Bainbridge Island, WA 98110
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Web Seite: http://www.phytec.de http://www.phytec.com
1st Edition June 2003

Table of Contents
PHYTEC Meßtechnik GmbH 2003 L-623e_1
Preface ......................................................................................................1
1 Introduction .........................................................................................3
1.1 Block Diagram..............................................................................6
1.2 View of the phyCORE-XC167.....................................................7
2 Pin Description.....................................................................................9
3 Jumpers..............................................................................................17
3.1 J1, J2 A/D Reference Voltage ...................................................23
3.2 J3 Internal or External Program Memory..................................23
3.3 J4, J35 SRAM U6/U7 Chip Select ............................................24
3.4 J5 SRAM Memory Size.............................................................25
3.5 J6 E²PROM/FRAM Supply Voltage .........................................25
3.6 J7 Write Protection of E²PROM /FRAM ..................................26
3.7 J8, J9 Address of the Serial E²PROM/ FRAM..........................26
3.8 J11, J12, J15, J16 CAN Interfaces.............................................27
3.9 J13, J14, J17, J18 CAN Transceiver..........................................28
3.10 J19 RTC Interrupt Output..........................................................29
3.11 J20, J21 Configuration of P9.4 and P9.5 for I²C Bus................29
3.12 J22 RTC (U13) Clock Output....................................................30
3.13 J23, J24 First Serial Interface ....................................................30
3.14 J25, J26 Second Serial Interface................................................31
3.15 J27 Ethernet Controller Chip Select..........................................32
3.16 J29 Ethernet Controller Sleep Mode..........................................32
3.17 J30 Ethernet Controller IRQ Signal...........................................33
3.18 J32 Write Protection of Flash....................................................33
3.19 J33, J34 SRAM Chip Select U5 ................................................34
3.20 J36 Organization of E²PROM U15...........................................34
4 System Configuration........................................................................35
4.1 System Startup Configuration.....................................................35
5 Memory Models.................................................................................39
5.1 Bus Cycle Phases........................................................................42
6 Serial Interfaces.................................................................................45
6.1 RS-232 Interface.........................................................................45
6.2 CAN Interface.............................................................................46
7 Real-Time Clock RTC-8564 (U13)...................................................47
8Serial E²PROM/FRAM (U8) ............................................................49
9 Flash Memory (U4)............................................................................51
10 Battery Buffer and Voltage Supervisor Chip (U9).........................52
11 CS8900A Ethernet Controller..........................................................53

phyCORE-XC167
PHYTEC Meßtechnik GmbH 2003 L-623e_1
11.1 Fundamentals..............................................................................53
11.2 Memory Mode............................................................................53
12 Debug Interface.................................................................................55
13 Technical Specifications....................................................................59
14 Hints for Handling the phyCORE-XC167......................................61
15 The phyCORE-XC167 on the phyCORE Development
Board HD200 2.5V............................................................................63
15.1 Concept of the phyCORE Development Board HD200.............63
15.2 Development Board HD200 2.5V Connectors and Jumpers......65
15.2.1 Connectors.....................................................................65
15.2.2 Jumpers on the phyCORE Development
Board HD200 2.5V .......................................................67
15.2.3 Unsupported Features and Improper Jumper Settings ..69
15.3 Functional Components on the phyCORE Development
Board HD200 2.5V.....................................................................70
15.3.1 Power Supply at X1.......................................................71
15.3.2 Activating the Bootstrap Loader ...................................73
15.3.3 First Serial Interface at Socket P1A..............................75
15.3.4 Power Supply to External Devices via Socket P1A......77
15.3.5 Second Serial Interface at Socket P1B..........................79
15.3.6 First CAN Interface at Plug P2A...................................82
15.3.7 Second CAN Interface at Plug P2B ..............................88
15.3.8 Programmable LED D3.................................................93
15.3.9 Pin Assignment Summary of the phyCORE, the
Expansion Bus and the Patch Field...............................93
15.3.10 Battery Connector BAT1.............................................102
15.3.11 Releasing the /NMI Interrupt ......................................102
15.3.12 DS2401 Silicon Serial Number...................................102
15.3.13 Pin Header Connector X4 ...........................................103
16 Ethernet Port...................................................................................105
17 Revision History..............................................................................107
Index ..................................................................................................109

Table of Contents
PHYTEC Meßtechnik GmbH 2003 L-623e_1
Index of Figures
Figure 1: Block Diagram phyCORE-XC167 ...............................................6
Figure 2: View of the phyCORE-XC167.....................................................7
Figure 3: Pinout of the phyCORE-Connector (Top View, with Cross
Section Insert).............................................................................11
Figure 4: Numbering of the Jumper Pads...................................................17
Figure 5: Location of the Jumpers (Controller / Connector Side)..............18
Figure 6: Timing Phases for Multiplexed Bus Mode.................................40
Figure 7: Timing Phases for Demultiplexed Bus Mode.............................40
Figure 8: JTAG Interface (Top View) .......................................................55
Figure 9: JTAG Interface (Bottom View)..................................................56
Figure 10: Physical Dimensions...................................................................59
Figure 11: Modular Development and Expansion Board Concept with
the phyCORE-XC167.................................................................64
Figure 12: Location of Connectors on the phyCORE Development
Board HD200 2.5V.....................................................................65
Figure 13: Numbering of Jumper Pads ........................................................67
Figure 14: Location of the Jumpers (View of the Component Side)...........67
Figure 15: Default Jumper Settings of the phyCORE Development
Board HD200 2.5V with phyCORE-XC167 ..............................68
Figure 16: Connecting the Supply Voltage at X1 ........................................71
Figure 17: Pin Assignment of the DB-9 Socket P1A as First RS-232
(Front View) ...............................................................................75
Figure 18: Location of Components at U12 and U13 for Power
Supply to External Subassemblies..............................................77
Figure 19: Pin Assignment of the DB-9 Socket P1B as Second
RS-232 (Front View).................................................................79
Figure 20: Pin Assignment of the DB-9 Plug P2A (CAN Transceiver on
phyCORE-XC167, Front View) .................................................82
Figure 21: Pin Assignment of the DB-9 Plug P2A (CAN Transceiver on
Development Board)...................................................................84

phyCORE-XC167
PHYTEC Meßtechnik GmbH 2003 L-623e_1
Figure 22: Pin Assignment of the DB-9 Plug P2A (CAN Transceiver on
Development Board with Galvanic Separation).........................86
Figure 23: Pin Assignment of the DB-9 Plug P2B (CAN Transceiver on
phyCORE-XC167) .....................................................................88
Figure 24: Pin Assignment of the DB-9 Plug P2B (CAN Transceiver on
phyCORE-XC167) .....................................................................89
Figure 25: Pin Assignment of the DB-9 Plug P2B (CAN Transceiver on
Development Board with Galvanic Separation).........................92
Figure 26: Pin Assignment Scheme of the Expansion Bus..........................94
Figure 27: Pin Assignment Scheme of the Patch Field................................94
Figure 28: Connecting the DS2401 Silicon Serial Number.......................103
Figure 29: Pin Assignment of the DS2401 Silicon Serial Number............103
Figure 30: Ethernet Transformer Module Connector ................................105
Index of Tables
Table 1: Pinout of the phyCORE-Connector X1......................................15
Table 2: Jumper Settings ..........................................................................22
Table 3: J1, J2 A/D Converter Reference Voltage..................................23
Table 4: J3 Code Fetch Selection ............................................................23
Table 5: J4 SRAM U6/U7 Chip Select Configuration ............................24
Table 6: J35 SRAM U6/U7 Chip Select Configuration ..........................24
Table 7: J5 SRAM U6/U7 Size Configuration........................................25
Table 8: J6 E²PROM Supply Voltage Configuration..............................25
Table 9: J7 Write Protection of E²PROM/FRAM...................................26
Table 10: J8, J9 E²PROM/FRAM Address Configuration........................26
Table 11: J11, J12, J15, J16 CAN Interface Configuration.......................28
Table 12: J19 P2.11 / RTC Interrupt Configuration..................................29
Table 13: J20, J21 P9.4, P9.5 / I2C Bus Configuration .............................29
Table 14: J22 RTC Clock Output Configuration.......................................30

Table of Contents
PHYTEC Meßtechnik GmbH 2003 L-623e_1
Table 15: J23, J24 First Serial Interface Configuration.............................31
Table 16: J25, J26 Second Serial Interface Configuration ........................31
Table 17: J27 Ethernet Controller Chip Select Configuration...................32
Table 18: J29 Ethernet Controller Sleep Mode Configuration..................32
Table 19: J30 Ethernet Controller IRQ Signal Configuration...................33
Table 20: J32 Write Protection of Flash....................................................33
Table 21: J33, J34 Chip Select SRAM Configuration................................34
Table 22: J36 Organization of E²PROM U15............................................34
Table 23: Functional Settings on Port P0 for System Startup
Configuration..............................................................................36
Table 24: System Startup Configuration Registers.....................................38
Table 25: Bus Timing Calculation Examples.............................................41
Table 26: Memory Device Options for U8.................................................49
Table 27: E²PROM/FRAM Write Protection .............................................49
Table 28: E²PROM/FRAM Address...........................................................50
Table 29: JTAG Connector X2 Pin Assignment.........................................57
Table 30: Improper Jumper Setting for JP16 on the
Development Board....................................................................69
Table 31: Improper Jumper Setting for JP30/33 on the
Development Board....................................................................69
Table 32: JP9, JP16 Configuration of the Supply Voltages
VCC/VCC2.................................................................................71
Table 33: JP9, JP16 Improper Jumper Settings for the Supply
Voltages......................................................................................72
Table 34: JP28 Configuration of the Boot Button.....................................73
Table 35: JP28 Configuration of a Permanent Bootstrap Loader Start .....74
Table 36: JP22, JP23, JP10 Configuration of Boot via RS-232................74
Table 37: Improper Jumper Settings for Boot via RS-232.........................74
Table 38: Jumper Configuration for the First RS-232 Interface.................75
Table 39: Improper Jumper Settings for DB-9 Socket P1A as
First RS-232................................................................................76

phyCORE-XC167
PHYTEC Meßtechnik GmbH 2003 L-623e_1
Table 40: JP24 Power Supply to External Devices Connected to P1A
on the Development Board.........................................................78
Table 41: Jumper Configuration for the Second RS-232 Interface............79
Table 42: Improper Jumper Settings for DB-9 Socket P1B
(2nd RS-232)................................................................................80
Table 43: Jumper Configuration of the DB-9 Socket P1B (no Second
RS-232) ......................................................................................80
Table 44: Improper Jumper Settings for DB-9 Socket P1B (no Second
RS-232) ......................................................................................81
Table 45: Jumper Configuration for CAN Plug P2A using the CAN
Transceiver on the phyCORE-XC167........................................82
Table 46: Jumper Configuration for CAN Plug P2A using the CAN
Transceiver on the Development Board.....................................83
Table 47: Improper Jumper Settings for the CAN Plug P2A (CAN
Transceiver on the Development Board)....................................84
Table 48: Jumper Configuration for CAN Plug P2A using the CAN
Transceiver on the Development Board with Galvanic
Separation...................................................................................85
Table 49: JP39 CAN Bus Voltage Supply Reduction...............................86
Table 50: Improper Jumper Settings for the CAN Plug P2A (CAN
Transceiver on Development Board with
Galvanic Separation)..................................................................87
Table 51: Jumper Configuration for CAN Plug P2B using the CAN
Transceiver on the phyCORE-XC167........................................88
Table 52: Jumper Configuration for CAN Plug P2B using the CAN
Transceiver on the Development Board....................................89
Table 53: Improper Jumper Settings for the CAN Plug P2B (CAN
Transceiver on the Development Board)....................................90
Table 54: Jumper Configuration for CAN Plug P2B using the CAN
Transceiver on the Development Board with Galvanic
Separation...................................................................................91
Table 55: Improper Jumper Settings for the CAN Plug P2B (CAN
Transceiver on Development Board with
Galvanic Separation)..................................................................92

Table of Contents
PHYTEC Meßtechnik GmbH 2003 L-623e_1
Table 56: JP17 Configuration of the Programmable LED D3...................93
Table 57: Pin Assignment Data/Address Bus for the phyCORE-XC167 /
Development Board / Expansion Board.....................................95
Table 58: Pin Assignment Port P1, P2, P3 for the phyCORE-XC167 /
Development Board / Expansion Board.....................................96
Table 59: Pin Assignment Port P4, P5, P6, P7 for the phyCORE-XC167 /
Development Board / Expansion Board.....................................97
Table 60: Pin Assignment Port P9 for the phyCORE-XC167 /
Development Board / Expansion Board.....................................98
Table 61: Pin Assignment Interface Signals for the phyCORE-XC167 /
Development Board / Expansion Board.....................................98
Table 62: Pin Assignment Control Signals for the phyCORE-XC167 /
Development Board / Expansion Board.....................................99
Table 63: Pin Assignment Power Supply for the phyCORE-XC167 /
Development Board / Expansion Board...................................100
Table 64: Unused Pins on the phyCORE-XC167 / Development Board /
Expansion Board.......................................................................101
Table 65: JP28 Releasing the /NMI Interrupt..........................................102
Table 66: JP19 Jumper Configuration for Silicon Serial Number Chip..102
Table 67: Ethernet Transformer Connector Pinout...................................105
Table 68: Jumper for Ethernet Transformer Port......................................106

phyCORE-XC167
PHYTEC Meßtechnik GmbH 2003 L-623e_1