Avnet Ultra96-V1 Installation manual

Page 1
Copyright © 2020 Avnet, Inc. AVNET, “Reach Further,” and the AV logo are registered
trademarks of Avnet, Inc. All other brands are the property of their respective owners.
LIT# Ultra96-HW-User-Guide-rev-1-0-V1.1
Ultra96-V1 Single Board Computer
Hardware User’s Guide
Version 1.1

Page 2
Contents
1Document Control .................................................................................................3
2Version History......................................................................................................3
3End of Life.............................................................................................................3
4Introduction ...........................................................................................................4
4.1 Glossary................................................................................................................................... 5
4.2 Reference Documents............................................................................................................. 5
5Ultra96-V1 Architecture and Features...................................................................6
5.1 List of Features ........................................................................................................................ 6
5.2 Ultra96-V1 Block Diagram ....................................................................................................... 7
6Functional Description...........................................................................................8
6.1 Zynq UltraScale+ MPSoC........................................................................................................ 8
6.1.1 SBVA484 Package........................................................................................................... 9
6.1.2 PL I/Os (Banks 26, 65, 66)............................................................................................. 10
6.1.3 PS MIOs (Banks 500, 501, 502).................................................................................... 13
6.1.4 PS Bank 503 .................................................................................................................. 17
6.1.5 PS Bank 504 .................................................................................................................. 18
6.1.6 PS Bank 505 .................................................................................................................. 20
6.2 LPDDR4 Memory................................................................................................................... 21
6.3 microSD Card......................................................................................................................... 21
6.4 USB........................................................................................................................................ 22
6.4.1 USB5744 Implementation Details.................................................................................. 22
6.5 Wi-Fi / Bluetooth..................................................................................................................... 23
6.5.1 Wi-FI............................................................................................................................... 23
6.5.2 Bluetooth........................................................................................................................ 23
6.5.3 Bluetooth Audio.............................................................................................................. 23
6.6 Mini DisplayPort..................................................................................................................... 23
6.7 UART ..................................................................................................................................... 23
6.8 I2C.......................................................................................................................................... 24
6.9 User LEDs.............................................................................................................................. 24
6.10 MPSoC Thermal Bracket with Fan......................................................................................... 24
6.11 Expansion Connectors........................................................................................................... 24
6.11.1 Low Speed Expansion Connector (J7) .......................................................................... 24
6.11.2 High Speed Expansion Connector................................................................................. 26
7Configuration and Debug ....................................................................................27
7.1 Boot Mode.............................................................................................................................. 27

Page 3
7.2 JTAG Configuration and Debug............................................................................................. 27
8Power..................................................................................................................28
8.1 External Power Connection ................................................................................................... 28
8.2 Power Estimation Using XPE................................................................................................. 29
8.3 Power Regulators .................................................................................................................. 29
8.4 Power Sequence.................................................................................................................... 30
9Clocks .................................................................................................................31
10 Reset...................................................................................................................31
11 Getting Help and Support....................................................................................31
1 Document Control
Document Version: 1.1
Document Date: 25 February 2020
2 Version History
Version
Date
Comment
0.9
18 Mar 2018
Preliminary release of Ultra96-V1 Hardware User’s Guide
1.0
07 Aug 2018
Updated release
1.1 25 Feb 2020 Added info regarding EOL
3 End of Life
The original Ultra96 Single Board Computer was released in 2018 and shipped until April 2019. After that
time, it was replaced with an updated version, called Ultra96-V2. To help with the nomenclature, the original
Ultra96 is now referred to as Ultra96-V1. The term Ultra96 may be used to refer to the family, meaning both
Ultra96-V1 and Ultra96-V2.
Information about Ultra96-V1 is still available at http://avnet.me/ultra96-v1.
Information about Ultra96-V2 is available at http://avnet.me/ultra96-v2.

Page 4
4 Introduction
The main purposes of the Ultra96-V1 Single Board Computer are:
•Provide a Xilinx entry in the 96Boards community
•Combine ARM processing with programmable logic in a convenient and expandable board
•Showcase a wide range of potential peripherals and acceleration engines in theprogrammable logic
that is not available from other 96Boards offerings
•Be a low-cost starter kit for Zynq UltraScale+ MPSoC developers
•Showcase hardware acceleration for software bottlenecks
•Allow expansion to a variety of sensors and peripherals through the 96Boards mezzanine
connectors
•Target applications for development, including:
oArtificial Intelligence
oMachine Learning
oIoT/Cloud connectivity for add-on sensors
oEmbedded Computing
oRobotics
oWireless design and demonstrations using Wi-Fi and Bluetooth

Page 5
4.1 Glossary
Term
Definition
PS
Zynq UltraScale+ MPSoC Processing System
PL
Zynq UltraScale+ MPSoC Programmable Logic
MIO
PS Multiplexed Input Output Pins
POR
Power On Reset
APU
Application Processing Unit
RPU
Real-time Processing Unit
GPU
Graphics Processing Unit
SYSMON
System Monitor
HD
High Density PL I/O Pins
HP
High Performance PL I/O Pins
PMBus
Power Management Bus
4.2 Reference Documents
[1] Zynq UltraScale+ MPSoC Overview
[2] Zynq UltraScale+ MPSoC DC and AC Switching Characteristics
[3] Zynq UltraScale+ MPSoC Technical Reference Manual
[4] Zynq UltraScale+ MPSoC Packaging and Pinout Product Specification
[5] Zynq UltraScale+ MPSoC PCB Design Guide
[6] UltraScale Architecture SelectIO Resources
[7] SBVA484 Package File
[8] Xilinx Vivado Design Suite
[9] Xilinx Software Development Kit
[10] 96Boards Specification
[11] WiLink8 2.4GHz WiFi + Bluetooth Module
[12] USB3320 Hi-Speed USB 2.0 ULPI Transceiver
[13] USB5744 Smart Hub
[14] Micron MT53B512M32D2NP-062 WT:C LPDDR4 SDRAM datasheet
[15] Delkin Devices Utility Industrial MLC microSD

Page 6
5 Ultra96-V1 Architecture and Features
This section summarizes the features of the development board, followed by functional descriptions of each
circuit.
5.1 List of Features
The Ultra96-V1 Single Board Computer supports the following features:
•Zynq UltraScale+ MPSoC ZU3EG SBVA484
•Storage
oMicron 2 GB (512M x32) LPDDR4 Memory
oMicroSD Socket
Ships with Delkin Utility MLC Industrial 16GB card
•Wi-Fi / Bluetooth
•DisplayPort
•1x USB 3.0 Type Micro-B upstream port
•2x USB 3.0 Type A downstream ports
•40-pin Low-speed expansion header
•60-pin High speed expansion header
•Mounted on thermal bracket with fan
Note that there is no on-board, wired Ethernet interface. All communications must be done via USB,
Wi-Fi, JTAG, or expansion interface.

Page 7
5.2 Ultra96-V1 Block Diagram
Figure 1 – Ultra96-V1 Block Diagram

Page 8
6 Functional Description
The following sections provide brief descriptions of each feature provided on the Ultra96-V1 board.
6.1 Zynq UltraScale+ MPSoC
The Zynq UltraScale+ MPSoC ZU3EG device (in the SBVA484 package) contains:
•Processor System (PS):
oApplication Processing Unit
Quad-core ARM Cortex-A53 MPCore with CoreSight; NEON & Single/Double
Precision Floating Point; 32KB/32KB L1 Cache, 1MB L2 Cache
oReal-Time Processing Unit
Dual-core ARM Cortex-R5 with CoreSight; Single/Double Precision Floating
Point; 32KB/32KB L1 Cache, and TCM
oEmbedded and External Memory
256KB On-Chip Memory w/ECC; External DDR4; DDR3; DDR3L; LPDDR4;
LPDDR3; External Quad-SPI; NAND; eMMC
oGeneral Connectivity
214 PS I/O; UART; CAN; USB 2.0; I2C; SPI; 32b GPIO; Real Time Clock;
WatchDog Timers; Triple Timer Counters
oHigh-Speed Connectivity
4 PS-GTR; PCIe Gen1/2; Serial ATA 3.1; DisplayPort 1.2a; USB 3.0; SGMII
oGraphic Processing Unit
ARM Mali™-400 MP2; 64KB L2 Cache
•Programmable Logic (PL)
oSystem Logic Cells 154,350
oCLB Flip-Flops 141,120
oCLB LUTs 70,560
oDistributed RAM (Mb) 1.8
oBlock RAM Blocks 216
oBlock RAM (Mb) 7.6
oUltraRAM Blocks 0
oUltraRAM (Mb) 0
oDSP Slices 360
oCMTs 3
oSystem Monitor 2
•I/O oMax PS MIO 78
MIO = multiplexed I/O (up to three banks of 26 I/Os) with support for I/O
voltage of 1.8V or 3.3V
oMax. PS Transceiver I/O 4 transmit and 4 receive pairs
oMax. PL HP I/O 156
HP = High-performance I/O with support for I/O voltage from 1.0V to
1.8V
oMax. PL HD I/O 96
HD = High-density I/O with support for I/O voltage from 1.2V to 3.3V
oMax. PL Transceiver I/O 4 transmit and 4 receive pairs

Page 9
6.1.1 SBVA484 Package
Figure 2 – SBVA484 Package Diagram

Page 10
6.1.2 PL I/Os (Banks 26, 65, 66)
Zynq UltraScale+ MPSoC Promammable Logic (PL) provides two types of I/O banks: High-
density (HD) banks and high-performance (HP) banks. HD banks support a limited number of
single-ended I/O standards with speeds up to 250Mbps and VCCO voltages up to 3.30V. HP
bankssupporta largevarietyofhigh-speedI/Ostandards,includingdifferentialI/O,and support
VCCO voltages up to 1.80V.
ZU3EG provides one HD bank (Bank 26) with 24 pins, one HP bank (Bank 65) with 52 pins,
and another HP bank (Bank 66) with 6 pins.
The PL I/Os on Ultra96-V1 are tied to the Low-Speed 96Boards Mezzanine, the High-Speed
96Boards Mezzanine, Bluetooth, and the fan.
Table 1 – PL IO Bank 26
MPSoC Pin Number
Bank
MPSoC Site Name
Function
C8
26
IO_L8P_HDGC_AD4P_26
Bluetooth
A8
IO_L10P_AD2P_26
A9
IO_L9N_AD3N_26
B9
IO_L9P_AD3P_26
B5
IO_L11N_AD1N_26
B7
IO_L12P_AD0P_26
E8
IO_L6P_HDGC_AD6P_26
HS Expansion
D8
IO_L6N_HDGC_AD6N_26
D7
IO_L5P_HDGC_AD7P_26
LS Expansion
F8
IO_L4P_AD8P_26
E5
IO_L3N_AD9N_26
D6
IO_L5N_HDGC_AD7N_26
D5
IO_L7P_HDGC_AD5P_26
C7
IO_L8N_HDGC_AD4N_26
B6
IO_L11P_AD1P_26
C5
IO_L7N_HDGC_AD5N_26
F7
IO_L4N_AD8N_26
G7
IO_L2P_AD10P_26
F6
IO_L2N_AD10N_26
G5
IO_L1N_AD11N_26
A6
IO_L12N_AD0N_26
A7
IO_L10N_AD2N_26
G6
IO_L1P_AD11P_26
E6
IO_L3P_AD9P_26

Page 11
Table 2 – PL IO Bank 65
MPSoC Pin Number
Bank
MPSoC Site Name
Function
F4
65
IO_T3U_N12_65
Fan
P1
IO_L7N_T1L_N1_QBC_AD13N_65
HS
Expansion
N2
IO_L7P_T1L_N0_QBC_AD13P_65
N4
IO_L8N_T1L_N3_AD5N_65
N5
IO_L8P_T1L_N2_AD5P_65
M1
IO_L9N_T1L_N5_AD12N_65
M2
IO_L9P_T1L_N4_AD12P_65
M4
IO_L10N_T1U_N7_QBC_AD4N_65
M5
IO_L10P_T1U_N6_QBC_AD4P_65
L1
IO_L11N_T1U_N9_GC_65
L2
IO_L11P_T1U_N8_GC_65
T2
IO_L1N_T0L_N1_DBC_65
T3
IO_L1P_T0L_N0_DBC_65
R3
IO_L2N_T0L_N3_65
P3
IO_L2P_T0L_N2_65
U1
IO_L3N_T0L_N5_AD15N_65
U2
IO_L3P_T0L_N4_AD15P_65
H5
IO_L16N_T2U_N7_QBC_AD3N_65
J5
IO_L16P_T2U_N6_QBC_AD3P_65
F1
IO_L19N_T3L_N1_DBC_AD9N_65
G1
IO_L19P_T3L_N0_DBC_AD9P_65
E3
IO_L20N_T3L_N3_AD1N_65
E4
IO_L20P_T3L_N2_AD1P_65
D1
IO_L21N_T3L_N5_AD8N_65
E1
IO_L21P_T3L_N4_AD8P_65
C3
IO_L22N_T3U_N7_DBC_AD0N_65
D3
IO_L22P_T3U_N6_DBC_AD0P_65
C2
IO_L24N_T3U_N11_PERSTN0_65
D2
IO_L24P_T3U_N10_PERSTN1_I2C_SDA_65
NC
F2
IO_L23N_T3U_N9_65
F3
IO_L23P_T3U_N8_I2C_SCLK_65
G2
IO_L17N_T2U_N9_AD10N_65
G4
IO_L18N_T2U_N11_AD2N_65
H2
IO_L17P_T2U_N8_AD10P_65
H3
IO_T2U_N12_65
H4
IO_L18P_T2U_N10_AD2P_65
J1
IO_L15N_T2L_N5_AD11N_65

Page 12
J2
IO_L13N_T2L_N1_GC_QBC_65
J3
IO_L13P_T2L_N0_GC_QBC_65
K1
IO_L15P_T2L_N4_AD11P_65
K3
IO_L14N_T2L_N3_GC_65
K4
IO_L14P_T2L_N2_GC_65
K5
VREF_65
L3
IO_L12N_T1U_N11_GC_65
L4
IO_L12P_T1U_N10_GC_65
N3
IO_T1U_N12_65
P5
IO_L6P_T0U_N10_AD6P_65
R1
IO_L5P_T0U_N8_AD14P_65
R4
IO_L4P_T0U_N6_DBC_AD7P_SMBALERT_65
R5
IO_L6N_T0U_N11_AD6N_65
T1
IO_L5N_T0U_N9_AD14N_65
T4
IO_L4N_T0U_N7_DBC_AD7N_65
P2
IO_T0U_N12_VRP_65
VRP
Table 3 – PL IO Bank 66
MPSoC Pin
Number
Bank MPSoC Site Name Function
A2
66
IO_T3U_N12_66
HS Expansion
A3
66
IO_L12N_T1U_N11_GC_66
NC
A4
66
IO_L12P_T1U_N10_GC_66
B1
66
IO_L11N_T1U_N9_GC_66
B2
66
IO_L11P_T1U_N8_GC_66
B4
66
IO_T0U_N12_VRP_66
C4
66
VREF_66

Page 13
6.1.3 PS MIOs (Banks 500, 501, 502)
Table 4 – MIO Overview
012345678910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
SPI1 WE BE I2C PB SD0 USB
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51
PI INA PK TP SPI0
52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77
IW
PMI
Bank 500
1.80V
SD0
LED
LSE
Bank 501
1.80V
PMIC
DPAUX
SD0
SPI1
UART1
UART0
I2C1
SD1
SPI0
LSE
Bank 502
1.80V
USB0
USB1
LSE
UART1 - Header
UART0 - Bluetooth (+ PL RTS/CTS)
I2C1 - I2C Hub
SPI1 - HS Expansion Header
WE - (GPIO) WiFi Enable
BE - (GPIO) Bluetooth Enable
I2C - (GPIO) I2C Hub Reset
SD0 - SD Card (3.3V level shifter)
LED - (GPIO) User LEDs
PB - (GPIO) User Pushbutton
USB - (GPIO) USB Hub Vbus detect
PI - (GPIO) Power Pushbutton Controller INT_B (PMU input)
DPAUX - DiplayPort Auxiliary Signals
INA - (GPIO) INA226 PMBUS Alert (PMU Input)
PMIC - (GPIO) FPU, PL power control (PMU Output)
PK - (GPIO) Power Pushbutton Controller KILL_B (PMU output)
TP - (GPIO) Test Point (PMU Output)
LSE - (GPIO) LS Expansion Header GPIO[A..L]
SPI0 - LS Expansion Header
SD1 - WiFi
USB0 - Upstream USB
USB1 - Downstream USB, Hub
IW - (GPIO) WiFi IRQ
PMI - (GPIO) PMIC Interrupt

Page 14
Table 5 – MIO Bank 500 (MIOs 0 to 25)
Bank
Pin #
Device
Signal
I/O
Notes
500
0
UART1
MIO0_UART1_TX
O
UART Header J6
1
MIO1_UART1_RX
I
2
UART0
MIO2_UART0_RX_BT_HCI_TX
I
WL1831 B
3
MIO3_UART0_TX_BT_HCI_RX
O
4
I2C1
MIO4_I2C1_SCL
O
I2C Mux
5
MIO5_I2C1_SDA
IO
6 SPI1 MIO6_SPI1_SCLK O Hi-speed Expansion
Header
7
GPIO
MIO7_WLAN_EN
O
WL1831 WiFi enable
8
GPIO
MIO8_BT_EN
O
WL1831 BT enable
9
SPI1
MIO9_SPI1_CS
O
Hi-speed Expansion
Header
10
MIO10_SPI1_MISO
I
11
MIO11_SPI1_MOSI
O
12
GPIO
MIO12_I2C_MUX_RESET_B
O
I2C Mux reset
13
SD0
MIO13_SD0_DAT0
IO
SDIO0 Data 0
14
MIO14_SD0_DAT1
IO
SDIO0 Data 1
15
MIO15_SD0_DAT2
IO
SDIO0 Data 2
16
MIO16_SD0_DAT3
IO
SDIO0 Data 3
17
GPIO
MIO17_PS_LED3
O
User LED 3
18
MIO18_PS_LED2
O
User LED 2
19
MIO19_PS_LED1
O
User LED 1
20
MIO20_PS_LED0
O
User LED 0
21
SD0
MIO21_SD0_CMD
IO
SDIO0 Command
22
MIO22_SD0_CLK
O
SDIO0 Clock
23
GPIO
MIO23_GPIO_PB
I
User Pushbutton
24
SD0
MIO24_SD0_DETECT
I
SDIO Card Detect
25
GPIO
MIO25_VBUS_DET
O
USB Hub VBUS

Page 15
Table 6 – MIO Bank 501 (MIOs 26 to 51)
Bank
Pin #
Device
Signal
I/O
Notes
501 26 GPIO MIO26_POWER_INT_B I Pushbutton On/Off Controller
Interrupt, Pushbutton turn-off
event detected
27
DPAUX
MIO27_DP_AUX_OUT
O
DPAUX single-ended output
28
MIO28_DP_HPD
I
DPAUX Hot Plug Detect
29
MIO29_DP_OE
O
DPAUX Output Enable
30
MIO30_DP_AUX_IN
I
DPAUX single-ended input
31 GPIO MIO31_INA226_PMBUS_
ALERT
I INA226 Alert
32 GPIO MIO32_PS_FP_PWR_EN O PMU power off
Full Power Domain
33
GPIO
MIO33_PL_PWR_EN
O
PMU power off PL
34 GPIO MIO34_POWER_KILL_B O LTC2950
Pushbutton On/Off Controller
Release enable output, power
off system
35
GPIO
IO
Test Point
36
GPIO
MIO36_PS_GPIO1_0
IO
Low-speed Expansion GPIO-C
37
GPIO
MIO37_PS_GPIO1_1
IO
Low-speed Expansion GPIO-D
38
SPI
MIO38_SPI0_SCLK
O
SPI Serial Clock
39
GPIO
MIO39_PS_GPIO1_2
IO
Low-speed Expansion GPIO-E
40
GPIO
MIO40_PS_GPIO1_3
IO
Low-speed Expansion GPIO-F
41
SPI0
MIO41_SPI0_CS0
O
SPI Chip Select 0
42
SPI0
MIO42_SPI0_MISO
I
SPI Data In
43
SPI0
MIO43_SPI0_MOSI
O
SPI Data Out
44
GPIO
MIO44_PS_GPIO1_4
IO
Low-speed Expansion GPIO-G
45
GPIO
MIO45_PS_GPIO1_5
IO
Low-speed Expansion GPIO-H
46
SDIO
MIO46_SD1_D0
IO
SDIO1 Data 0
47
SD1
MIO47_SD1_D1
IO
SDIO1 Data 1
48
SD1
MIO48_SD1_D2
IO
SDIO1 Data 2
49
SD1
MIO49_SD1_D3
IO
SDIO1 Data 3
50
SD1
MIO50_SD1_CMD
O
SDIO1 Command
51
SD1
MIO51_SD1_CLK
O
SDIO1 Clock

Page 16
Table 7 – MIO Bank 502 (MIOs 52 to 77)
Bank
Pin #
Device
Signal
I/O
Notes
502
52
USB0
MIO52_USB0_CLK
I
USB0 Clock
53
MIO53_USB0_DIR
I
USB0 Data bus direction
54
MIO54_USB0_DATA2
IO
USB0 Data 2
55
MIO55_USB0_NXT
I
USB0 Data flow
56
MIO56_USB0_DATA0
IO
USB0 Data 0
57
MIO57_USB0_DATA1
IO
USB0 Data 1
58
MIO58_USB0_STP
O
USB0 Stop transfer
59
MIO59_USB0_DATA3
IO
USB0 Data 3
60
MIO60_USB0_DATA4
IO
USB0 Data 4
61
MIO61_USB0_DATA5
IO
USB0 Data 5
62
MIO62_USB0_DATA6
IO
USB0 Data 6
63
MIO63_USB0_DATA7
IO
USB0 Data 7
64
USB1
MIO64_USB1_CLK
I
USB1 Clock
65
MIO65_USB1_DIR
I
USB1 Data bus direction
66
MIO66_USB1_DATA2
IO
USB1 Data 2
67
MIO67_USB1_NXT
I
USB1 Data flow
68
MIO68_USB1_DATA0
IO
USB1 Data 0
69
MIO69_USB1_DATA1
IO
USB1 Data 1
70
MIO70_USB1_STP
O
USB1 Stop transfer
71
MIO71_USB1_DATA3
IO
USB1 Data 3
72
MIO72_USB1_DATA4
IO
USB1 Data 4
73
MIO73_USB1_DATA5
IO
USB1 Data 5
74
MIO74_USB1_DATA6
IO
USB1 Data 6
75
MIO75_USB1_DATA7
IO
USB1 Data 7
76 MIO76_WLAN_IRQ I WL1831MOD WLAN
Interrupt
77
PMIC IRQ
I
PMIC IRQ

Page 17
6.1.4 PS Bank 503
Bank 503 contains system-level pins, including Mode, config, PSJTAG, error, SRST, and POR.
Table 8 – PS Bank 503
MPSoC Pin
Number
Bank MPSoC Site Name
K16
503
PS_ERROR_OUT_503
K18
PS_ERROR_STATUS_503
K15
PS_INIT_B_503
H15
PS_MODE1_503
J15
PS_MODE2_503
H18
PS_MODE3_503
H17
PS_PADI_503
J17
PS_PADO_503
K12
PS_POR_B_503
H14
PS_REF_CLK_503
K13
PS_SRST_B_503

Page 18
6.1.5 PS Bank 504
Bank 504 contains the DDR Controller pins which are connected to LPDDR4 on Ultra96-V1.
Table 9 – PS Bank 504
MPSoC Pin
Number
Bank MPSoC Site Name
AA22
504
PS_DDR_A0_504
AB20
PS_DDR_A1_504
AB17
PS_DDR_A2_504
AB19
PS_DDR_A3_504
AB21
PS_DDR_A4_504
AB16
PS_DDR_A5_504
Y21
PS_DDR_A10_504
AA21
PS_DDR_A11_504
AA18
PS_DDR_A12_504
AA19
PS_DDR_A13_504
AA17
PS_DDR_A14_504
AA16
PS_DDR_A15_504
W20
PS_DDR_CK_N0_504
V19
PS_DDR_CK_N1_504
V20
PS_DDR_CK0_504
V18
PS_DDR_CK1_504
U22
PS_DDR_CKE0_504
U21
PS_DDR_CKE1_504
V22
PS_DDR_CS_N0_504
U20
PS_DDR_CS_N1_504
AB9
PS_DDR_DM0_504
AB14
PS_DDR_DM1_504
U9
PS_DDR_DM2_504
W13
PS_DDR_DM3_504
AB11
PS_DDR_DQ0_504
Y10
PS_DDR_DQ1_504
AB10
PS_DDR_DQ2_504
W10
PS_DDR_DQ3_504
AA8
PS_DDR_DQ4_504
Y8
PS_DDR_DQ5_504
AB7
PS_DDR_DQ6_504
AA7
PS_DDR_DQ7_504
AA11
PS_DDR_DQ8_504
Y11
PS_DDR_DQ9_504

Page 19
AA12
PS_DDR_DQ10_504
AB12
PS_DDR_DQ11_504
Y14
PS_DDR_DQ12_504
AA14
PS_DDR_DQ13_504
Y15
PS_DDR_DQ14_504
AB15
PS_DDR_DQ15_504
W8
PS_DDR_DQ16_504
W7
PS_DDR_DQ17_504
V7
PS_DDR_DQ18_504
V10
PS_DDR_DQ19_504
U7
PS_DDR_DQ20_504
T9
PS_DDR_DQ21_504
U10
PS_DDR_DQ22_504
T10
PS_DDR_DQ23_504
U11
PS_DDR_DQ24_504
U12
PS_DDR_DQ25_504
W12
PS_DDR_DQ26_504
W11
PS_DDR_DQ27_504
V14
PS_DDR_DQ28_504
U14
PS_DDR_DQ29_504
W15
PS_DDR_DQ30_504
V15
PS_DDR_DQ31_504
AA9
PS_DDR_DQS_N0_504
AA13
PS_DDR_DQS_N1_504
V8
PS_DDR_DQS_N2_504
V13
PS_DDR_DQS_N3_504
Y9
PS_DDR_DQS_P0_504
Y13
PS_DDR_DQS_P1_504
V9
PS_DDR_DQS_P2_504
V12
PS_DDR_DQS_P3_504
T18
PS_DDR_RAM_RST_N_504
T19
PS_DDR_ZQ_504

Page 20
6.1.6 PS Bank 505
Bank 505 contains the transceivers.
Table 10 – PS Bank 505
MPSoC Pin
Number
Bank MPSoC Site Name
L20
505
PS_MGTREFCLK0N_505
L19
PS_MGTREFCLK0P_505
J20
PS_MGTREFCLK1N_505
J19
PS_MGTREFCLK1P_505
K22
PS_MGTRTXN0_505
K21
PS_MGTRTXP0_505
F22
PS_MGTRTXN1_505
F21
PS_MGTRTXP1_505
D22
PS_MGTRRXN2_505
D21
PS_MGTRRXP2_505
C20
PS_MGTRTXN2_505
C19
PS_MGTRTXP2_505
B22
PS_MGTRRXN3_505
B21
PS_MGTRRXP3_505
A20
PS_MGTRTXN3_505
A19
PS_MGTRTXP3_505
M20
PS_MGTRREF_505
E19
PS_MGTREFCLK3P_505
E20
PS_MGTREFCLK3N_505
G19
PS_MGTREFCLK2P_505
G20
PS_MGTREFCLK2N_505
H21
PS_MGTRRXP1_505
H22
PS_MGTRRXN1_505
M21
PS_MGTRRXP0_505
M22
PS_MGTRRXN0_505