EMAC PRIMER User manual

THE
PRIMER
TRAINER
SELF INSTRUCTION
MANUAL
Manual Revision 3.0
For board revision 3
Copyright 2005, EMAC INC.
UNAUTHORIZED COPYING, DISTRIBUTION,
OR MODIFICATION PROHIBITED
ALL RIGHTS RESERVED
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2
INTRODUCTION TO THE PRIMER TRAINER 5
INTRODUCTION TO COMPUTERS 7
Computer Math 7
Computer Logic 9
A BRIEF OVERVIEW OF THE PRIMER HARDWARE 10
MEMORY 10
INPUT/OUTPUT 10
REGISTERS 10
TECHNICAL CIRCUITRY DESCRIPTION 12
Schematic Sheet 2: Microprocessor and Expansion Bus 12
Schematic Sheet 3: I/O Decoding and Memory 13
Schematic Sheet 4: Display and Keypad Circuitry 14
Schematic Sheet 5: Digital I/O and Timer 15
Schematic Sheet 6: Optional Serial Communication Port 16
Schematic Sheet 7: Analog I/O 16
Schematic Sheet 8: Power Supply, Speaker and Miscellaneous 16
HARDWARE FEATURES 18
LANGUAGES USED BY THE PRIMER 20
8085 Machine Language 20
Assembly Language 20
GETTING STARTED 22
LESSON 1: USING THE MONITOR OPERATING SYSTEM 24
LOADING A PROGRAM INTO MEMORY 24
VIEWING AND CHANGING REGISTER CONTENTS 25
ADDRESS/REGISTER PAIR DISPLAYS 25
SOME TIPS ABOUT CHANGING REGISTERS 26

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LESSON 2 : RUNNING YOUR FIRST PROGRAM 27
LESSON 3: LOADING REGISTERS AND TRANSFERRING DATA BETWEEN REGISTERS 29
LESSON 4: EIGHT BIT ADDITION 31
LESSON 5: EIGHT BIT SUBTRACTION 32
LESSON 6: SIXTEEN BIT SUBTRACTION 33
LESSON 7: SIXTEEN BIT ADDITION 35
LESSON 8: SIXTEEN-BIT SUBTRACTION USING TWO'S COMPLEMENT ADDITION 37
LESSON 9: BINARY CODED DECIMAL SIXTEEN-BIT ADDITION 38
LESSON 10: MULTIPLICATION 40
LESSON 11: DIVISION 42
LESSON 12: USING LOGIC INSTRUCTIONS 43
LESSON 13: USING CONDITIONALS 45
LESSON 14: USING REGISTER INDIRECT ADDRESSING 47
LESSON 15: USING REGISTER INDIRECT ADDRESSING TO PERFORM 24-BIT ADDITION49
LESSON 16: USING REGISTER INDIRECT ADDRESSING TO MOVE DATA 51
LESSON 17: USING VARIABLES 53
LESSON 18: THE STACK AND RELATED INSTRUCTIONS 56
LESSON 19: USING THE XTHL INSTRUCTION. 60
LESSON 20: SUBROUTINES 63
LESSON 21: USING MONITOR OPERATING SYSTEM SUBROUTINES 66
LESSON 22: USING PITCH (SERVICE 10) 67
LESSON 23: USING ADCIN (SERVICE 9) 69

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LESSON 24: USING COMPARE INSTRUCTIONS 71
LESSON 25: USING INTERRUPTS 75
LESSON 26: WRITING YOUR OWN PROGRAMS 78
APPENDIX A: JUMPER DESCRIPTIONS AND I/O ADDRESSES 82
APPENDIX B: THE PRIMER KEYPAD DESCRIPTION 83
APPENDIX C: 8085A CPU INSTRUCTIONS IN OPERATION CODE SEQUENCE 85
APPENDIX D: MOS SERVICES 87

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Introduction to the PRIMER Trainer
The PRIMER Trainer is a compact, low cost, 8085 based microprocessor system, designed primarily for educational
purposes. In spite of its low cost and small size, it contains many important and educational features. The PRIMER has
digital I/O, analog I/O, and a display plus keypad for human interface. There are also several options that can be added to
the basic unit to enhance flexibility and functionality.
STANDARD FEATURES OF ALL PRIMERS
• 80C85 microprocessor operating at 3.072 MHZ.
• 256 bytes of RAM
• 8-bit digital inputs via 8 station DIP switch.
• 8 digital outputs with LED's for status indication.
• 6 digit numeric LED display.
• 20 key keypad for data entry.
• Digital to analog converter, 6-bit resolution.
• Analog to digital converter 6-bit resolution.
• A sound port, which consists of a piezoelectric beeper driven by a programmable counter, can produce variable
frequencies.
• Monitor Operating System (MOS) EPROM.
• Operation from a 7 to 10 VDC supply.
Additionally, the PRIMER may be assembled with the following on-board options, or they may be added later :
• Extra RAM: A 32K byte static RAM or RAMDISK may be installed.
• Extra RAM/Real Time Clock: A 32K byte battery backed static RAM with Real Time Clock may be installed. The
clock keeps time in hundredths of seconds, seconds, minutes, hours, day of week, day of month, month and year,
even when the PRIMER is off. It automatically compensates for leap years, and keeps time in military or AM/PM
mode.
• Extra EPROM: The student may create his own programs, or other operating systems may be added, including
high level languages such as E-FORTH, MTBASIC, etc.
• RS-232 port: Provides the PRIMER with the ability to hook up to a "dumb terminal" or personal computer.
The following peripheral boards may be connected to the expansion bus connector CN1.
• 32 LINE PARALLEL I/O BOARD: This gives the user 32 lines of digital I/O on two Opto-22 I/O rack compatible
connections. Of the 32 lines, 8 are output only and the other 24 are programmable as inputs or outputs. The 24
lines are implemented using the popular 8255 PPI chip.
• EPROM PROGRAMMER BOARD: This allows programming of popular EPROM devices such as the 27c512,
27c256, 27c128 and 27c64 with 21V and 12.5V programming voltage capability. This option is required along
with the RAM and serial port upgrade in order to take full advantage of the EPROM programmer interface menu.
Documentation on this interface is included when you purchase the EPROM PROGRAMMER BOARD. (To see
the EPROM programmer interface menu on your PC monitor, connect your serial port to a PC running a terminal
emulation package and press “func.” then “4" on the PRIMER keypad. The only interaction after this point is
through the PC keyboard).

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Unit Description
The standard PRIMER will allow the student to enter programs into the units' memory, allow the student to run them, and
to view the results.
The Monitor Operating System ( the standard monitor software in EPROM ) included will cause the keyboard controller chip
to scan the keypad buttons, interpret the entries, and allow storage of data into the 256 byte RAM included in the PRIMER.
The operating system also displays related data on the 6-digit LED display. The operating system will allow the student to
examine the data stored at various memory locations, examine the contents of the microprocessor's registers and other
functions, via the display and keypad. The operating system software will permit the student to run ( execute ) the program
entered, and to execute the program in steps, instruction by instruction, to permit debugging of programs.
The instruction manual contains several lessons in which the student may write programs to access and use the digital I/O,
analog I/O, and experiment with the sound port, interrupts, and timers. All that is needed to perform this is included in the
basic PRIMER kit.
Optional Hardware and Software
POWER SUPPLY
Any filtered DC power source from seven ( 7 ) to ten ( 10 ) volts DC may be used to power the PRIMER. Power is
fed to the unit via power jack J1. Make sure that the power supply's output plug has a positive tip and a negative
sleeve. Current consumption will be less than 500 mA. ( 350mA to 420mA typically ). If desired, a wall plug/DC
power supply with built in power plugs may be ordered separately. Note: Be careful to observe correct type of
voltage and polarity, or else the PRIMER may be seriously damaged!
MEMORY
The PRIMER's built-in RAM memory is 256 bytes. The Monitor Operating System uses a few bytes at the top of
this memory. This leaves more than two-hundred bytes for code that may be entered, which is quite a lot
considering it is entered by hand. However, if larger memory is desired, as is the case when higher level operating
systems such as E-FORTH and MT-BASIC are used, an additional 32 K byte static RAM may be added. Also an
Extended Monitor Operating System (EMOS) may be installed in place of the standard Monitor Operating System
EPROM.
DATA/FUNCTION KEYS
The standard PRIMER comes with a twenty key keypad to select functions, and enter data.
COMMUNICATION PORT
Without all the options, the PRIMER is a powerful, stand-alone unit that has the potential to do more than just be a
training device. It has a easy to use interface that has the potential, with a little more hardware added to become a
full blown computer/controller. One of the additions to the PRIMER that help accomplish this end is the Serial RS-
232 Communication Port. With this hardware option installed, the PRIMER can communicate with a terminal or
PC, permitting greatly increased flexibility. This option is essential when the high-level language EPROMS are
installed on the PRIMER.
EXPANSION PORT
The expansion port is a 50 pin header connector that provides access to the 8085 microprocessor's multiplexed
Address/Data Bus, control signals, and PRIMER DC power. Connection of other circuit cards to this bus allows
the PRIMER to perform an almost unlimited number of functions. The connector footprint allows the PRIMER to
interface with most of EMAC's standard peripherals, the most notable being EMAC's EPROM Programmer card
and digital parallel I/O board. The connector also has extra pins not used by EMAC peripherals, but which are
useful to the students who may design peripheral boards of their own.
EXTERNAL I/O PORT
The External digital I/O port connector can be added at any time to provide direct access to the TTL level digital
output and input lines, via a ribbon cable. These ports are 8 bits each, and are in parallel with the DIP switch and
output LEDs. The I/O port connector permits easy access to the I/O lines so the student may connect switches
and relay contacts to the digital input lines and relay drivers, solid state relays (SSRs) to the output lines. These
inputs and outputs are used to allow the PRIMER to control various devices for very interesting projects.

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Introduction to Computers
Computers basically perform three functions: inputing data, processing the data and outputing data. Some devices that are
commonly used to input information to a computer are keyboards, DIP switches and joysticks. Common computer output
devices are light emitting diodes (LEDs), liquid crystal displays (LCDs), video monitors, and printers. Disk drives and
modems are common devices that have both input and output characteristics. To process the information obtained by the
input devices and to control what information will be sent to the output devices we must introduce the next lower level of a
computer; the microprocessor.
A microprocessor, which is also referred to as the central processing unit (CPU), processes the information that is input to
the computer and determines what data will be sent to the output devices. The microprocessor has within it an arithmetic
logic unit (ALU) which performs addition, subtraction, comparisons and logical functions, which will be discussed later.
One thing you must know about computers is that they don't really think like people do. They can only do what the
computer manufacturer or the computer user tells them to do. The microprocessor can do many different things, but in
order for something useful to be done it must follow a group of instructions called a program. Below is a "program" or a
group of instructions that you could write which a person may follow in order to quench their thirst.
1) Get a glass.
2) Get some milk from the refrigerator.
3) Pour the milk in the glass.
4) Drink the milk.
5) If you are still thirsty continue from step three.
6) Put glass in sink
7) put milk in refrigerator.
In the same way, by knowing the microprocessor's language, you can give it a group of instructions that it can perform and
it would perform them exactly as you commanded it. The microprocessor can only obey one instruction of a program at a
time and these instructions tell the microprocessor whether to input data, output data or perform one of the ALU functions.
Computer Math
A microprocessor performs all arithmetic in binary, although it may be translated to different forms (i.e. decimal,
hexadecimal..). The binary number system consists of the numbers 0 and 1 which are called binary digits or bits for short.
There are several words used to represent the binary numbers 0 and 1 and they are often used interchangeably,
depending on the context in which they are used. They are as follows:
binary 1 = true on high set +5 volts set
binary 0 = false off low reset 0 volts clear
In the 8085 microprocessor the binary numbers are organized in groups of 8 bits which are called bytes and groups of 16
bits which are called words. When referring to a byte, it is often necessary to describe particular bits, so the numbering of
each of the 8 bits is as follows:
7 6 5 4 3 2 1 0
So in the binary number, 10001000, bit 7 and bit 3 are 1 and the rest are 0. In binary number 00010001, bit 4 and bit 0 are
have a value of 1 and the rest are 0. When referring to a word, the bits are numbered:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
s you know, in decimal numbers, each position of a digit has a different weight. For example in the decimal number 1732:
(The digit numbers are read from right to left, 0 to 3)
digit # weight value = decimal result
3 103* 1 = 1000
2 102* 7 = 700
1 101* 3 = 30
0 100* 2 = 2
sum of numbers * weights = 1732
In the same way the binary system has weights for each bit position. The weight for a bit is 2 to the power of the bit

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number (2(bit number)). The binary number 11111111 can be converted to decimal by knowing the weights of each bit, as in
the example below:
bit # weight value = decimal result
7 27* 1 = 128
6 26* 1 = 64
5 25* 1 = 32
4 24* 1 = 16
3 23* 1 = 8
2 22* 1 = 4
1 21* 1 = 2
0 20* 1 = 1
sum of bits * weights = 255
The three forms of numbers we will use in this manual are binary, hexadecimal (hex, for short) and decimal. Below is a
table of the binary, and hex equivalents of the decimal numbers 0 through 20.
DECIMAL HEX BINARY
0 0 0000
1 1 0001
2 2 0010
3 3 0011
4 4 0100
5 5 0101
6 6 0110
7 7 0111
8 8 1000
9 9 1001
10 A 1010
11 B 1011
12 C 1100
13 D 1101
14 E 1110
15 F 1111
16 10 10000
17 11 10001
18 12 10010
19 13 10011
20 14 10100
Hexadecimal is used to represent binary values because it is very easy to convert numbers from binary to hexadecimal.
For example, to convert the following binary number to hexadecimal:
101101101101011
Start from the right digit and put the number into groups of four binary digits (bits). If there are not enough bits in the
number to make a full four bits in the group on the left side, add zeros to the left of the number.
0101 1011 0110 1011
Now replace the binary groups with their hexadecimal equivalents using the table above and you will get the following
result:
5 B 6 B
It is just as easy to convert hex to binary. Merely replace each hex digit with the corresponding 4 binary digits from the
table above and you have your binary number, for example:
HEX
F C 1 8
BINARY
1111 1100 0001 1000
In this manual you will see the words "least significant" or "low order" and "most significant" or "high order". These refer to
the mathematical weight of the part of a number that is being described. In all number systems the digit on the left end is
the most significant or high order digit and the digit on the right end is the least significant or low order digit. For example in
the binary number 00010010, the bit on the left end is the most significant bit and the bit on the right end is the least
significant bit. In the hex word 01FF the left two digits are the most significant byte (MSB) and the two right digits are the

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least significant byte (LSB).
Computer Logic
The 8085 supports 4 logical operations:
1) The AND operation takes two input bits and returns a 1 bit if both input bits are 1 and a 0 bit if either bit is 0.
2) The OR operation takes two input bits and returns a 1 bit if either input bit is 1 and a 0 bit if both input bits are 0.
3) The XOR operation takes two input bits and returns a 0 bit if the input bits are the same and a 1 bit if they are different.
4) The NOT operation takes one input bit and returns a 1 if the input bit is 0 and returns a 0 if the input bit is 1. This is
called complementing or inverting.
The 8085 performs these operations 8 bits at a time, by performing the logic operation on each bit position, For example:
01110010 <-X
AND 10010011 <-Y
00010010 <-Z
Bit 0 of X is ANDed with bit 0 of Y and gives the result in bit 0 of Z. Bit 1 of X is ANDed with bit 1 of Y and gives the result
in bit 1 of Z and the pattern continues on up to bit 7.
The following show the way logical operations work with bytes:
00010010
AND 01000010
00000010
01100111
OR 10101110
11101111
11101101
XOR 01111001
10010100
NOT 11001010
00110101

A Brief Overview of the PRIMER Hardware
MEMORY
The 8085 microprocessor can access 65536
individual memory locations in the range 0 to 65535 in
decimal (0 to FFFF in hex) but only one at a time.
There are two types of memory in most
microprocessor based systems, memory that can be
read but not written to, which is called Read Only
Memory (ROM), and memory that can be read from
and written to, which is called Read/Alter Memory or
Random Access Memory (RAM). Both RAM and
ROM chips have address pins which are connected to
the microprocessor's address pins. These pins are
connected through what is called an address bus and
through this bus the microprocessor can select a
memory location for writing or reading of data.
Writing to ROM chips has no effect.
The RAM and ROM chips in the PRIMER trainer have
eight pins which send data to, or receive data from
the microprocessor through a group of eight
connections called the data bus. Since there are 8
pins in the RAM and ROM chips, this allows numbers
from 0 to 255 (0 to FF in hex) to be read from or
written to each memory location.
INPUT/OUTPUT
The 8085 microprocessor can also send data to and receive data from chips other than the RAM or ROM. When the
microprocessor wants to perform input or output it disables the RAM and ROM chips and sends an input/output (I/O)
address to the address bus. The I/O address is only 8 bits but it appears on the lower 8 bits (A0-A7) and the higher 8 bits
(A8-A15) of the address bus simultaneously. Since the address generated is only 8 bits long, only I/O addresses from 0-
255 (0-FF hex) can be selected. Most microprocessor-based systems have circuitry which decode the address from the
address bus and select the appropriate I/O device. Usually these devices are dedicated to either input only or output only.
If an input device has been selected, 8 bits of data is transmitted from the input device to the data bus and into the
microprocessor. If an output device has been selected, the 8 bits of data is sent from the microprocessor to the data bus
and to the output device.
The control bus is a group of connections which provide control over reading or writing of memory or I/O devices. Below is
a block diagram showing the way the CPU (microprocessor) connects to the memory and I/O devices through the address
bus, data bus and control bus.
REGISTERS
The 8085 microprocessor has within it temporary storage devices called registers. Registers work similarly to RAM in that
they store binary values. The 8 bit general purpose registers provided by the 8085 are named A, B, C, D, E, H and L. The
A register is often referred to as "the accumulator".
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The 8085 has many instructions which use these individual
general purpose registers. There are also instructions which
view a pair of the general purpose registers as a single 16
bit register. The register pairs that are used in these
instructions are BC, DE, and HL. When they are paired with
other registers C,E and L represent the least significant 8
bits of the register pairs (bits 0-7) and B,D and H represent
the most significant 8 bits (bits 8-15). Some instructions
view the A register and flag register (described below) as a
16 bit register called the processor status word (PSW). The
A register is the most significant 8 bits and the flag register
is the least significant 8 bits of register. The PSW is shown
with a diagram of the individual bits of the flag register,
below.
There are also registers that are dedicated to special
purposes. The registers and their descriptions are as
follows:
The stack pointer (SP) is a 16 bit register which
points to a memory location in RAM which will hold
temporary values in an area of RAM called the
stack. The stack is explained in detail in a later
lesson.
The program counter (PC) is a 16 bit register which
points to the memory location of the next machine
language instruction to be executed.
The flag register is an 8 bit register which has
individual bits, called flags, that indicate the result
of arithmetic or logical operations. Most of these
flags will be described later in the manual.
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Technical Circuitry Description
Following is a technical description of the actual hardware circuitry of the PRIMER. It describes circuitry on a sheet by
sheet basis and is intended to be understood by a person with a background in digital electronics, though a person without
this background may be able to glean some useful information from it. It is not necessary to understand this section in
order to use the PRIMER.
Schematic Sheet 2: Microprocessor and Expansion Bus
The Microprocessor
The 8085 microprocessor chip is the brain of the PRIMER system. It coordinates almost all activity in the PRIMER. The
8085 microprocessor is a collection of counters, gates, registers, decoders, (etc.) that sequentially fetches instructions from
memory, finds the purposes of each instruction, and executes the purpose of each instruction. The instructions are placed
in memory in the order they are expected to be used. The types of instructions are widely variant, but very concise. They
operations consist of moving data, logical operations, branching and conditional branching, some mathematical operations,
and input/output. When correctly assembled into a logical order, these primitive instructions form what is called a program.
Programs can simply move data from an input port to an output port, using a few instructions, or they can perform complex
control operations using many different input and output ports and the number of instructions would stretch out to the
thousands.
The 8085 is built to be able to access 65,536 possible memory locations, and 256 I/O locations. The architecture of the
microprocessor expects both the program and the data to reside in sequentially arranged memory. The programmer (a
person who creates programs) must assemble the program correctly so the microprocessor will know what memory
contents are intended to be instructions and which ones are data.
The 8085 and most other microprocessors must start executing the program at its beginning, which in the case of the 8085
is at memory address 0. This is accomplished by a circuit that applies a signal to the pin named RST-IN on the
microprocessor when the computer is turned on. On the PRIMER, this signal comes from the Power-on/Pushbutton Reset
circuit shown on the schematic. When power is applied to the PRIMER, capacitor C1, initially discharged, holds the
microprocessor's RST-IN* pin, low ( the " * " means the signal is active low ). The low signal on the RST-IN pin causes the
8085 to reset some of its internal devices and make an internal register called the program counter point to the beginning of
the program. Another event that occurs is that RST-OUT signal is asserted, which resets the PPI chip (U4), display/keypad
controller (U5) and if populated, the optional UART (U17). Note that since U5 has a different reset polarity, it is instead
reset by the inverse of RST-OUT which comes from U19 pin 1. If EMAC peripherals are connected to the expansion port
they are also affected by the RST-OUT signal. This reset condition can also be brought about by pressing the reset button
(PB1) which merely shorts out C1 and brings the RST-IN pin low.
As the capacitor charges through R1, the RST-IN* line voltage rises until a logic high de-asserts this signal. Diode D1
serves to quickly discharge capacitor C1 through the power supply only when power is off. With RST-IN* de-asserted, the
8085 begins operation.
The system clock oscillator, whose frequency is set to 6.144 MHZ by crystal Y1, drives all timing functions within the 8085
and it runs as long as power is applied to the PRIMER. It is possible to run the 8085 under a wide range of frequencies,
but in the PRIMER we use 6.144 MHZ to provide compatibility with circuits used elsewhere in the system. The oscillator
signal is divided by two within the 8085, and this signal is now the main system clock, referred to as SYSCLK. All timing of
the microprocessor's operation is driven by this SYSCLK, which in our case is 3.072 MHZ. Even asynchronous input
signals like RST-IN*, and interrupts are internally synchronized to this oscillator. Each pulse of this clock signal, is called a
"T state", when referring to operations internal to the 8085 and its busses.
The first thing the microprocessor will do after RST-IN* de-asserts, is to fetch an instruction at memory address 0. Before
the instruction can be fetched, the memory address of the instruction must be output from the microprocessor. To reduce
the number of pins on the 8085's package, a scheme called multiplexing is employed. Multiplexing allows the AD0-AD7
pins to be used as the data bus and also to output the lower 8 bits of the 16 bit address needed to select the first
instruction. These pins must be demultiplexed before they can be used properly. The 8085 outputs the low byte of the
address on signal lines AD0-AD7, and the high byte directly on signal lines A8-A15. A signal called Address Latch Enable
(ALE) strobes high, then low, causing the address latch (chip U8) to trap the address byte that is on pins AD0-AD7. The
output of this latch then joins up with address lines A8-A15, to provide a 16 bit, filtered, stable, linear address to the
memory chips and decoders ( described later ).

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The 16 bit linear address is applied to the memory block ( memories and decoders ) to select the address that the 8085
wants to read from or write to. In the case of an instruction fetch, the 8085 signal RD* will be asserted, to read the byte
from the memory selected. This byte will then go into the instruction decoder, which will determine what instruction it is,
and then the 8085 will execute the instruction. Depending on what type of instruction it is, the 8085 will either fetch
additional data or read/write data to other memory locations or perform I/O, (etc.). Each time a bus transaction occurs
these operations will occur: the low byte of the address will be sent to AD0-AD7, which will then be held by the address
latch. A complete cycle of instruction fetch, decode, and execution, forms a "bus cycle", using anywhere from 3 to 14 T-
States, ( SYSCLK pulses ) depending on the type of instruction.
The 8085 has five pins dedicated to "interrupting" the microprocessor. These pins are named TRAP, RST 7.5, RST 6.5,
RST 5.5 and INTR. When a signal is applied to one of these pins an "interrupt" is generated. An interrupt is a special
function of the 8085 to suspend the program it is running then execute a program related to the interrupt that requested it.
Once the interrupt is completed, the 8085 must RESTORE the original program's data and status, and RETURN to it where
it left off from. Sometimes the interrupt is deliberately ignored by MASKING the interrupt, so interrupts can be turned on or
off as needed, should a section of code be so important to require that it not be interrupted until it is finished.
An interrupt may be likened to answering the telephone while reading a book. When the telephone rings, you put the book
down on it's face to mark your place, then you answer the phone. When you are done, you pick up the book and begin
reading where you left off. Should you be too engrossed in the story, you can ignore the ringing telephone (you can mask
it). But if you ignore it too long, you'll miss the call. Sometimes interrupts can be missed as well. Some interrupts can be
made to latch, usually by hardware. These latched interrupt requests will persist, just as a person on the phone might
continue ringing ( interrupting ) until you answer it.
Bus Expansion Port
The PRIMER's Bus Expansion Port is also shown on Schematic Sheet 1. It is actually a simple connector with leads
running to power sources and microprocessor pins. The 8085's AD0-AD7 lines run out to the connector, as well as
address lines A0-A15, control signal IO/M* ( which the 8085 asserts to tell whether it is doing a memory or I/O transaction ),
RD*, WR*, RST-OUT, SYSCLK, GROUND, and PWR ( this is directly from the power jack, 5V is not provided on the bus
connector). Also inclued are INTRQ, and INTA*, which allow the use of a multi-level interrupt controller; S0, and S1, which
are part of the 8085 machine status output; RDY/WT* which is used to put the 8085 into a wait state; HOLDRQ and
HLDACK which are used to allow another bus master to assume control of the bus; and finally, ID* and EXTIOCS*, which
are used by external I/O devices of the EPAC 2000 family. The Bus Expansion Port footprint permits direct connection of
the PRIMER to most EPAC peripheral cards, via a 50 pin ribbon cable.
The schematic shows " Module Ports " , which are connections to other parts of the board not shown on this page of the
schematic. Often one page of a schematic is not big enough to show an entire circuit but, of course, the actual wiring on
the printed circuit board is one complete unit. Module ports denote that these connections actually do exist, only they are
shown elsewhere. The name or label of the module port must match exactly on another sheet of the schematic to denote
that the connections go there. Individual lines to module ports also connect these lines to corresponding points on other
sheets of the schematic, such as lines RD*, and WR*.
Schematic Sheet 3: I/O Decoding and Memory
The decoder section of a microprocessor system sorts out the address bus signals from the 8085, and picks out ( selects )
the correct chip(s) in the memory or I/O sections that the 8085 wants to access. The decoder must evaluate the address
applied to it, and determine whether the address is for a memory access, or an I/O map access. Most decoders are
custom hardware collections of gates, using various levels of integration. As every system has a different configuration of
memory and I/O, every decoder is unique to that design.
In the PRIMER, two types of memory maps may be decoded based on the setting of OJ3. In the standard map (OJ3 in
position A), a 16K (K=1024 bytes) byte space is reserved for program EPROM, starting at address 0000 hex and ending at
3FFF hex ( remember the 8085 begins execution at 0000 hex after reset ). This socket may hold 32K EPROM chips but
only the lower 16K can be used with this jumper setting. The monitor operating system program is actually very small,
requiring less than 4K, but 32K EPROM chips are the smallest memory chip of compatible footprint that will fit there.
Almost all programs ( the PRIMER's monitor is no exception ) will require some memory that can be written to as well as
read. The PRIMER can provide this type of memory, without additional discrete RAM chips. The 8155
PPI/MEMORY/TIMER I.C. is a multi-function chip, with digital I/O ports, a timer/counter, and 256 bytes of RAM in it. When
OJ3 is in position A , this memory is used for storage of variables, pointers, executable code and various other functions.
Because the 8155 has both I/O and memory mapped elements, the decoder section provides an additional specially
encoded line called 8155CS for this device. The 8155 will be described in more detail later. The optional 32 K byte

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memory socket allows a 32 K static RAM chip to be installed onto the PRIMER. In the standard map it starts at 4000 hex
and goes to BFFF hex.
With OJ3 in position A, the 8155 PPI's memory space begins at C000 hex and ends at the top of the 8085's address range
at FFFF hex. Note that this range is 16 K, but the actual memory is only 256 bytes. What happens is the same 256 bytes
repeat themselves over and over again, in this case 64 times over. In other words, hexadecimal addresses C000, C100,
F300 and FD00 all refer to the first memory address within the 8155 and C0FF, C1FF, F3FF and FDFF all refer to the last
memory address within the 8155. Programs that are written must use only the amount of memory that is available.
The alternate memory map (OJ3 set to position B) reserves 32 K of EPROM at addresses 0000 hex to 7FFF hex, and 32 K
static RAM from 8000 hex to FFFF hex. The 256 bytes of RAM in the 8155 PPI are ignored, so in this map, the entire 64 K
of memory that the 8085 is capable of accessing contain no duplicate memory cells as does the standard map.
The PRIMER uses a very simple decoder. Two, "2 to 4 line" decoders decode the appropriate 8085 address lines to select
the proper chips. The memory decoder observes the code on address lines A14 and A15. The state of these lines
represent 16 K intervals of address. To change the decoder interval to 32 K bytes boundaries, the decoder pin that is
connected to A14 can instead be connected to ground. The I/O decoder observes the state of address lines A6 and A7.
The I/O map is only 256 addresses wide. The I/O decoder is maximally used at select rates of 64 addresses per output.
The 8085 signal line IO/M* tells the decoders that the address is an I/O MAP transaction, if it is high, or that it is a memory
map transaction, if it is low. A simple inverter changes the polarity of IO/M* to IO*/M. Since each decoder has an active
low enable input, connection of the appropriate polarity signal of IO/M* to the appropriate decoder, will enable the right
decoder for the job at hand. Also all decoder outputs are active low signals, and will be de-asserted unless the right
address in the right map selects it.
The EPROM chip select will be valid for memory addresses 0000 hex to 3FFF hex, (or to 7FFF hex if OJ3 is set to B) and
simply goes directly to the EPROM's chip enable. The optional static RAM chip select must be valid for addresses 4000
hex to BFFF hex, (or 8000 to FFFF hex if OJ3 is set to B) which is an interval of 32 K. As the memory decoder outputs at
intervals of 16 K, ( standard map ) two chip selects are logically negative OR'ed by AND gate U10A. This produces a single
32 K wide chip select for this memory.
The 8155 chip has elements of both the memory map and the I/O map, so a similar AND gate logically negative OR's the
memory and I/O map selects into a single dual mapped chip select for the 8155. The memory portion of this chip select is
valid throughout C000 hex to FFFF hex. The I/O portion is I/O addresses 00 hex to 3F hex.
The keypad and display controller (U5), which will be described in more detail later, is I/O mapped from 40 hex to 7F hex,
and the optional 8251A communication controller from I/O addresses 80 hex to BF hex. A special I/O chip select, used
primarily for EPAC expansion peripherals, via the bus expansion connector, uses the remaining I/O space of C0 hex to FF
hex. As in the memory chip select description, many of the addresses repeat in the I/O map, since these chips only use a
few of the available addresses.
The rest of the address bus lines, not used by the chip select decoder described, go directly to the memory chip(s) other
I/O chips, and bus expansion connector. Inside these chips are decoders which select the precise internal memory cells or
device registers denoted by the address pins. In more complex systems, the chip select decoders can be more precise,
but this increases the complexity and cost of the system. The simple device select decoder used here in the PRIMER will
serve quite well, as long as programs are written carefully.
Schematic Sheet 4: Display and Keypad Circuitry
The PRIMER has a key pad matrix of pushbuttons, for entering commands, loading data or programs, and testing
programs. It also has a 6 digit LED matrix display, to view data. U5 is a specialized Display/Keypad controller chip, which
removes the chores of keyboard scan, switch de-bounce, and display refresh, from the microprocessor. The controller
contains its own memory which stores key press data and data to be displayed. Through the I/O map, the 8085 sends
commands to the controller that configure the operational characteristics of the display/keypad system, then writes the
display characters themselves to the controller’s internal display RAM. The controller scans this display RAM, and drives
the outputs to the display LED's continuously thereafter. No further microprocessor action need be taken until a new
display pattern is needed.
Display/Keypad controller has 8 data bus lines that connect directly to the 8085's AD0 to AD7 lines. These bi-directional
bus leads transfer data and control information between the 8085 and controller. Signals RD*, and WR* determine whether
data is read from or written to it. Address line A0 is used by the controller to determine whether the byte is a command

15
byte, or a data byte for the internal RAM and the 8279CS* chip select pin determines whether it will perform bus
transactions or not. The 8279_RDY signal is a signal sent out to the 8085 that the controller momentarily drives low when it
is not able to receive data. This basically suspends the 8085’s operation until the signal is asserted high again. Because
address line A0 is used to select the function, two I/O map addresses exist for the Display/Keypad controller. A program
that operates the controller merely writes to or reads from two consecutive addresses to control all functions. With A0
being low, the controller’s memory can receive data from, or send data to the data bus. If A0 is high, the bus transaction is
a command or status byte.
The base address of U5 in the PRIMER is 40 hex. The I/O decoder's chip select will be valid for all I/O map transactions
up to 7F hex. Therefore, the two addresses for U5 repeat themselves throughout this range, just as the memory addresses
repeat in the 8155. This repetition is common to all I/O devices on the PRIMER, due to the broad nature of the chip select
decoder used.
The signals RST-OUT*, and KEYINT also terminate at the Display/Keypad controller. RST-OUT* will hardware clear the
controller’s internal control registers to their default state, which at a later time can be changed to other states by the
PRIMER's program in the EPROM. However, the data in the internal RAM is not cleared by hardware. Finally, the KEYINT
signal is a special control line that is set active high by the controller when a valid key entry is made. This line goes through
a jumper that (in its default connection) connects to the RST 5.5 interrupt pin on the 8085 microprocessor.
The controller scans the keypad buttons and debounces the key inputs to avoid erroneous entries due to contact bounce or
key rollover. After this, it stores the key inputs in the internal keypad RAM. When a valid key entry is made, the controller
generates an interrupt request to the 8085 via the KEYINT line, and holds the key data in the keypad RAM until the 8085
actually reads the key memory. Should the microprocessor not respond immediately, the controller will store in the internal
key RAM up to 8 key entries.
When the PRIMER is turned on, the Display/Keypad controller is configured by the PRIMER software to produce what is
referred to as an "encoded scan" on its SCBIT0-SCBIT3 lines. This encoded scan is decoded by a A6259K "3 to 8"
decoder and driver, to produce 1 of 6 active low high current sinks for the common cathode LED's. The SCBIT0-SCBIT3
lines also go to a 74HC138 to provide a keyboard row decoder.
When a key is pressed, a low signal will be presented to one of the corresponding return lines COL0-COL3 which are
connected to pullup resistors. The key must be closed and scanned several times in order to be recognized by the
Display/Keypad controller. It is then entered into key RAM and an interrupt request is generated which tells the
microprocessor to read the controller’s keypad RAM and interpret the key code to perform the function that is dedicated to
the key. The key must be released and stay that way for several more scans before that key or another key will be
accepted. This is the keypad debounce feature. The controller will also ignore additional key closures if a key is already
being pressed.
Schematic Sheet 5: Digital I/O and Timer
The 8155 combination Digital I/O, Timer, and Memory Chip provides the PRIMER with capability to experiment with Digital
input and output, programmable timing, and provides the read/write memory function for the system. Its bus interface is
very similar to the interface for the Display/Keypad controller. The 8155 also has 8 data bus lines, RD*, and WR* control
signals, and RESET input. There are additional bus control lines, but no individual address inputs are required since the
lower byte of the address and the data are demultiplexed within the 8155 from the AD0-AD7 inputs. The 8155 is missing
the address line(s) the Display/Keypad controller has, instead, it uses two new signals, IO/M*, and ALE. These signal lines
are the same as described in the previous microprocessor description. The 8155 chip is a special function chip made
specifically to work along with the 8085. It has an internal address latch, and an internal address decoder, which operates
in parallel with the PRIMER's address latch. The internal address latch and decoder uses the 8085 ALE signal, to trap the
low order 8 bits of multiplexed address. Since the internal RAM is only 256 bytes and there are only 4 I/O addresses, only
the low 8 multiplexed address/data bits are needed anyway. The chip select signal for the 8155 resolves whether bus
transactions will occur to the address internally latched and selected during microprocessor read or write cycles, to either
the I/O or memory sections of the 8155.
The Digital I/O ports are two "byte wide" (8-bit) ports, and one six bit port. The ports can be independently set to be
OUTPUT or INPUT ports. On the PRIMER unit, Port A is set by monitor software to function as an output port and eight
LEDs serve as status indicators of the bit state for each output line. Each LED lights when the bit for it is set LOW ( 0 ),
and it is off when the bit is set HIGH ( 1 ). Therefore, negative logic levels are assumed.
Port B of the 8155 is set by software to input. An eight station DIP switch is used to set each bit LOW ( 0 ) when each
station is turned on. Negative logic is also assumed here. When a switch station is switched OFF, a resistor pullup brings
the line HIGH. Port C of the 8155 goes to the digital to analog converter which is described later. The 8155 chip is totally

16
flexible as to what kind and data and direction is present on each port, however, for hardware purposes on the PRIMER,
the default configuration should be maintained.
The 8155 has a programmable timer/counter in it that is software programmable to count from 1 to 16,383. The counter
becomes a timer if it is fed a regular pulse train, as it is in the PRIMER. The SYSCLK signal is first divided by ten, and fed
to the 8155 timer input. The timer's output goes to the 8085's RST 7.5 interrupt input, and to an AND gate that drives a
piezo-electric speaker element (see sheet 7 for more details).
Schematic Sheet 6: Optional Serial Communication Port
If MTBASIC, E-FORTH or EMOS are installed on the PRIMER, this option will be required. The 8251A chip is called a
Universal Asynchronous Receiver Transmitter or UART. The UART interfaces serial data transmissions or receptions to
parallel data. The PRIMER's UART uses a very common communication protocol known as the RS-232 standard which
uses special voltage levels to connect to computer terminals, desktop PCs, etc.
The 8251A connects to the 8085 bus, and through software the 8085 can communicate to the terminal or PC via the
8251A. The UART operates on standard TTL-MOS voltage levels, and because the RS-232 standard uses Bi-polar
voltage levels, a special interface chip, the MAX-232 ( or equivelent ) converts the TTL levels to RS-232 voltages. The
MAX-232 chip contains special power supply circuits, called a "charge pump" that boosts the 5 volts used in the PRIMER to
+8 volts and -8 volts for the RS-232 link. Voltage translating drivers are also built into the chip. The optional serial
communications port interfaces to a terminal or PC through a DB-9 shell connector.
The serial communication rate (or baud rate) must be set to the rate used by the terminal or PC. Placement of jumper JP1
can set the baud rate from 300 baud up to 19,200 baud. The 614.4 KHZ COMCLK, which is generated by a circuit on
Schematic Sheet 4, is divided down by U16 providing seven different frequencies.
The PRIMER allows interrupt driven serial communications. To enable the hardware to do this, jumper OJ1 can be moved
to connect the 8085's RST 6.5 interrupt input to the RXRDY ( receive ready ) pin of the 8251A UART, instead of its default
connection to Vcc.
Schematic Sheet 7: Analog I/O
This sheet of the PRIMER shows the Analog I/O system for the unit. Many Microprocessor systems read analog signals,
such as temperatures, pressures, and amperage. Because microprocessors are digital devices, some sort of interface is
required to change an analog voltage into a digital code the microprocessor can deal with. In many cases, the
microprocessor system will also output a digital signal, after processing the analog and digital inputs it has reviewed.
The PRIMER has a 1 channel analog output, and a 1 channel analog input with the range of both at approximately 0 to 5
volts. The digital to analog ( D/A ) output comes from a R-2R ladder network of resistors, which is then buffered by op-amp
U14A. The D/A ladder is driven by port C of the 8155. The D/A converter has 6 bit resolution, so programs may be written
which write a value in the range of 0-63 decimal to the D/A port, resulting in an analog voltage proportional to the number
written to the port.
The analog to digital ( A/D ) input is a voltage comparator, made up of U14B, and some digital level shifting circuitry. The
comparator has an input pin on connector CN3, where the voltage to be measured is applied. The comparator then
compares this input voltage to the D/A ladder output voltage, and sends a digital signal to the SID input of the 8085. This
digital signal is high (or 1) when the D/A voltage is higher than the input voltage and the digital signal is low (or 0) when the
D/A voltage is lower than the input voltage. The PRIMER's monitor operating system contains a built in program which
converts an input voltage to a decimal value in the range of 0-63. Using this built in program within other programs and
attaching the appropriate hardware will allow the PRIMER to function as a voltmeter, temperature gauge, pressure gauge
or any other kind of analog measurement device. The PRIMER can then be used as what is often referred to as an
"embedded controller".
Schematic Sheet 8: Power Supply, Speaker and Miscellaneous
The final area of the PRIMER schematics is the power supply section. In the PRIMER only a very simple power supply is
required. The D.C. input is fed from power jack J1, and is pre-filtered by C8, then applied to an LM7805 regulator. The
LM7805 regulator is an industry standard device found in almost all small microprocessor systems, because its application
is very simple. The LM7805 regulator steps the 7 to 10 VDC power supply input down to the +5 volts required by the
microprocessor and all the other digital logic chips. Some of the input power bypasses the LM7805, and goes directly to
the LM358 dual op-amp chip, U14. The LM358 needs " voltage overhead " to work correctly for the analog voltages it

17
operates with.
Capacitor C9, and several other capacitors spread about the board provide D.C. power supply bypass. These bypass
capacitors stabilize the power supply voltage fed to the logic devices on the PRIMER.
To understand the speaker circuit, remember that as described earlier, the SYSCLK signal is first divided by ten, and fed to
the 8155 timer input. The timer's output goes to the 8085's RST 7.5 interrupt input, and to an AND gate that drives a piezo-
electric speaker element. The piezo-electric speaker has a limited frequency range, but many useful sounds can still be
produced by appropriate setting of the timer's divide ratio, and turning the output on and off through the 8085's SOD signal.
The SYSCLK frequency of 3.072 MHZ is divided down by U12 to 307.2 KHZ, then fed to the timer input of the 8155. By
setting the timer's divide ratio from 2 to 16383 ( in software ), the range of frequencies can be from 153.6 KHZ down to
18.75 Hz.
Also shown on this sheet, are the spare gates that are not used by the PRIMER circuit, but present on the board. This
often occurs since gate packages often come with multiple gates on one chip. As is customary, unused gate inputs should
be defined to an idle logic state to prevent random oscillations, latchup, etc. This is done primarily for CMOS and NMOS
devices, because TTL gates usually have built-in pullups on their inputs.

18
Hardware Features
HARDWARE RESET: The PRIMER board can be reset through the reset button provided on the board. There is a reset
output pin on the expansion connector which allows the resetting of the PRIMER to reset any devices that may be
connected to the expansion connector.
SERIAL COMMUNICATION PORT: The PRIMER uses an RS232 standard serial communication port. The port
interfaces to a PC or terminal through a DB-9 shell connector. The serial communication rate (or baud rate) must be set to
the rate used by the terminal or PC. Placement of jumper JP1 can set the baud rate from 300 baud up to 19,200 baud.
MOS services are available which access the 8251 serial communication port.
DIP SWITCH: The DIP switch has 8 switches which may be used for applications such as selection of program options.
The DIP switch is connected to the system data bus and is accessed through I/O, address 012H. A MOS service is
available which accesses the DIP switch.
DIGITAL OUTPUTS: The PRIMER has 8 outputs and each output can be independently programmed to an ON (+5v or
binary 1) or OFF (0v or binary 0) state. The outputs are connected directly to the digital output LEDs and an LED can be
turned on by the output of a binary 0, and turned off by the output of a binary 1. The outputs are also connected to the
digital I/O connector CN3.
The output is driven by the 8155 I/O I.C. which, in the standard configuration, uses PORT A (11H) as the output port, PORT
B (12H) as the input port and PORT C (13H) as an analog output port.
NOTE: The standard configuration of the 8155 which is set up by MOS should not be changed. Also, since PORT A
outputs have limited drive capabilities, buffering should be considered if these outputs are to be used.
DIGITAL INPUTS: The PRIMER allows 8 inputs through 8155 port B. These inputs are connected directly to the 8 station
DIP switch. The inputs are also connected to digital I/O connector CN3, so if the DIP switches are all turned off, you may
input external TTL level signals through this connector.
D/A: An analog output voltage in the range of approximately 0 to +5v can be output from the PRIMER. This digital to
analog convertor is implemented through an R-2R ladder which is connected to bits 0-5 of output PORT C. The output
from the R-2R ladder is available on pin 19 of the digital I/O connector CN3. MOS provides a service which uses this D/A
convertor.
A/D: The PRIMER provides an analog input (digital I/O Connector CN3 pin 20) which can convert a voltage in the range of
0 to +5 volts to a 6 bit value. This conversion is done by a MOS service using the D/A convertor and a comparator. The
service starts by outputting 0 volts from the D/A convertor and then increasing the output voltage until the comparator
senses that the output voltage exceeds the input voltage. When the input voltage has been exceeded, the last number that
was output to the D/A convertor is the digital representation of the analog input voltage. The schematic of the circuitry for
D/A and A/D is on Schematic Sheet 7.
Note: Since the service that performs the A/D conversion uses the D/A convertor, the D/A convertor cannot be
used at the same time an analog signal is being converted to digital.
TIMER/COUNTER: The PRIMER comes equipped with a 14 bit timer/event counter. This timer/counter is resident in the
8155 I/O I.C. By loading a user programmable termination count, time intervals from 3.25 microseconds to 53.3
milliseconds. When the termination count is reached, a RST 7.5 interrupt can then be issued to the CPU. If interrupts are
not desirable the timer can be read directly or the interrupt line can be polled. The timer can also be set up to reload itself
or to stop counting upon reaching the termination count. In either case, an interrupt can be issued.
The timer/counter is a 14 bit down counter that counts the 'timer input' pulses and provides a pulse or square wave to the
8085 RST 7.5 interrupt when the terminal pulse is reached. The user can reprogram the length of the count before the

19
termination pulse is reached if so desired. The user can also determine the timer interval by programming the counter
register from values 2H to 3FFFH. The timer/counter has four operating modes which are:
Mode 0 No operation mode (NOP) does not affect the timer.
Mode 1 Stop mode stops the timer/counter if it is running otherwise NOP.
Mode 2 Stops the timer if running immediately after the terminal count has been reached otherwise NOP.
Mode 3 The start mode loads the output mode and count length and starts the timer/counter immediately if timer is not
running, otherwise it waits for the terminal count then starts the timer/counter.
The timer/counter has four output modes which are as follows:
Mode 0 Outputs a low during the second half of the count, which is equivalent to a single square wave.
Mode 1 Outputs a continuous square wave when the terminal count is reached.
Mode 2 Outputs a single pulse when the terminal count is reached.
Mode 3 Outputs a single pulse and reloads automatically.
The timer/counter operating modes are programmed through the 8155 control register (I/O address 10H). The lower 8 bits
of the count length is written to I/O address 14H. The upper 6 bits of the count length along with the 2 bit output mode is
written to I/O address 15H. The timer/counter can be used as an external program interval timer. If you wish to perform a
software operation at a specific time interval, then the timer/counter can be programmed to that interval. Upon the resulting
timer interrupt your program can execute the desired software.
The timer/counter is also used to drive the PRIMER's speaker. Different frequencies can be output from the speaker using
a MOS service.
See the 8155 PDF for more details.
EXPANSION CONNECTOR
The PRIMER has a 40 pin expansion connector (CN1) on board which provides additional expansion capabilities.
Primarily, this port gives access to the Data and Low Address Busses and Control Lines. EMAC offers modular expansion
boards that plug into this connector.

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Languages Used By the PRIMER
8085 Machine Language
The 8085 microprocessor has 246 instructions and each instruction is represented by an 8 bit binary value, which is called
an op code or an instruction byte. The Instruction Set Encyclopedia ( (c) Intel Corporation ) included at the end of this
manual, divides these instructions into five general categories which are as follows:
1) Data Transfer Group: Moves data between registers or between memory locations and registers.
2) Arithmetic Group: Adds, subtracts, increments or decrements data in registers or memory.
3) Logic Group: AND's, OR's, XOR's, compares, rotates or complements data in registers or between memory and a
register.
4) Branch Group: Initiates conditional or unconditional jumps, calls, returns, and restarts.
5) Stack, I/O, and Machine Control Group: Includes instructions for maintaining the stack, reading from input ports,
writing to output ports, setting and reading interrupt masks, and changing the flag register.
Some machine language instructions require a byte or even two bytes of additional information. The microprocessor reads
the instruction and determines whether it requires an extra byte or two bytes. If the instruction requires another byte the
8085 will get the byte from the next consequtive address following the instruction byte, and if the instruction requires two
bytes the 8085 will get them from the next two consequtive addresses following the instruction byte. In instructions that
require two extra bytes, the byte following the op code is the least significant byte and the second byte after the op code is
the most significant byte. To help you remember this order, remember that the high order byte is in the higher memory
address than the low order byte.
Microprocessors can only run (execute) programs written in machine language. Programs written in languages such as
BASIC or assembly language (discussed later) first must be translated to machine language before they can be executed.
Assembly Language
Intel (c) has designed a way to represent the 8085's machine language instructions using words called "mnemonics".
Using these mnemonics, a language called "assembly language" was created which allows you to write machine language
programs in a more readable form. An assembly language program cannot be understood by the 8085 until it is translated
to machine language with a program called an "assembler". In the following lessons, programs will be listed in assembly
language followed by the machine language translation of the program.
Below is an example assembly language program, showing the four basic fields of a line of assembly language: label,
mnemonic, operand and comment. Note that assembly language programs usually don't have line numbers, but these are
included to aid in explaining assembly language.
LABEL MNEMONIC OPERAND COMMENT
1dips equ 12h ; port for the DIP switches
2num equ 4 ; number of reads of the DIP switches
3org 0ff01h ; starting address of the program
4lxi h,dtaspac ; load the HL register with start
5; of storage space
6mvi c,num ; load C register with value of num
7loop: in dips ; load A register with the DIP
8; switch values
9 mov m,a ; store the value of A register
10 ; at memory address pointed to by HL
11 dcr c ; decrement the C register
12 jnz loop ; if C<>0, jump to loop
13
14 rst 7 ; return to MOS
15 dtaspac: ds num ; set aside the number of bytes
16 ; specified by num
17 db 12h,4,1001b,0 ; store this data in memory
18 end ; end of the assembly language
In order to make assembly language more readable and easier to modify, the provision was included which allows the use
of a string of characters called a symbol or label to represent a numerical value. In the program above, the string of