ESD ECS-PCIe/FPGA User manual

ECS-PCIe/FPGA
Hardware Manual Doc.-Nr.: E.1106.21 /-Rev 1.1
Page 1 of 28
ECS-PCIe/FPGA
PCI Express® EtherCAT® Slave Interface
ESC-PCIe/FPGA-LP (E.1106.04)
Hardware Manual
to Products E.1106.02, E.1106.04

Page 2 of 28
Hardware Manual Doc.-Nr.: E.1106.21 /Rev. 1.1
ECS-PCIe/FPGA
This manual contains important information and instructions on safe and efficient
handling of the ECS-PCIe/FPGA. Carefully read this manual before commencing any
work and follow the instructions.
The manual is a product component, please retain it for future use.
Trademark Notices
Intel® is a registered trademark of Intel Corporation or its subsidiaries in the U.S. and/or other countries
PCI Express® is a registered trademark of PCI-SIG.
EtherCAT® is registered trademark and patented technology, licensed by Beckhoff Automation GmbH, Germany.
All other trademarks, product names, company names or company logos used in this manual are reserved by their
respective owners.
Notes
The information in this document has been carefully checked and is believed to be entirely reliable.
esd electronics makes no warranty of any kind with regard to the material in this document and
assumes no responsibility for any errors that may appear in this document. In particular descriptions
and technical data specified in this document may not be constituted to be guaranteed product
features in any legal sense.
esd electronics reserves the right to make changes without notice to this, or any of its products, to
improve reliability, performance or design.
All rights to this documentation are reserved by esd electronics. Distribution to third parties, and
reproduction of this document in any form, whole or in part, are subject to esd electronics' written
approval.
© 2021 esd electronics gmbh, Hannover
esd electronics gmbh
Vahrenwalder Str. 207
30165 Hannover
Germany
Tel.:
[phone]
Fax:
[phone]
E-Mail:
[email protected]
Internet:
www.esd.eu

ECS-PCIe/FPGA
Hardware Manual Doc.-Nr.: E.1106.21/ 1.1
Page 3 of 28
Document Information
Document file:
I:\Texte\Doku\MANUALS\EtherCAT\ECS-PCIeFPGA\ECS-PCIeFPGA_Hardware_en_11.docx
Date of print:
2021-03-02
Document-type
number:
DOC0800
Hardware version.:
1.0
Document History
The changes in the document listed below affect changes in the hardware as well as changes in the
description of the facts, only.
Rev.
Chapter
Changes versus previous version
Date
1.0
-
First English manual
2016-10-10
1.1
2.1, 6.10
Note on Busmaster DMA Support inserted
2021-03-02
6.2, 6.3
Description of FPGA Type changed/corrected (Intel)
7.3
Description of Pin Assignment of Connector X601 changed
8
New Declaration of Conformity
Technical details are subject to change without further notice.

Page 4 of 28
Hardware Manual Doc.-Nr.: E.1106.21 /Rev. 1.1
ECS-PCIe/FPGA
Classification of Warning Messages and Safety Instructions
This manual contains noticeable descriptions, warning messages and safety instructions, which you
must follow to avoid personal injuries or death and property damage.
This is the safety alert symbol.
It is used to alert you to potential personal injury hazards. Obey all safety messages
and instructions that follow this symbol to avoid possible injury or death.
DANGER, WARNING, CAUTION
Depending on the hazard level the signal words DANGER, WARNING or CAUTION are used to
highlight safety instructions and warning messages. These messages may also include a warning
relating to property damage.
DANGER
Danger statements indicate a hazardous situation which, if not avoided, will result in
death or serious injury.
WARNING.
Warning statements indicate a hazardous situation that, if not avoided, could result in
death or serious injury.
CAUTION
Caution statements indicate a hazardous situation that, if not avoided, could result in
minor or moderate injury.
NOTICE
Notice statements are used to notify people on hazards that could result in things other than personal
injury, like property damage.
NOTICE
This NOTICE statement indicates that the device contains components sensitive to
electrostatic discharge.
NOTICE
This NOTICE statement contains the general mandatory sign and gives information that
must be heeded and complied with for a safe use.
INFORMATION
INFORMATION
Notes to point out something important or useful.

ECS-PCIe/FPGA
Hardware Manual Doc.-Nr.: E.1106.21/ 1.1
Page 5 of 28
Safety Instructions
●
When working with the ECS-PCIe/FPGA follow the instructions below and read the manual
carefully to protect yourself from injury and the ECS-PCIe/FPGA from damage.
●
The device is a built-in component. It is essential to ensure that the device is mounted in a way
that cannot lead to endangering or injury of persons or damage to objects.
●
Do not use damaged or defective cables to connect the ECS-PCIe/FPGA.
●
In case of damages to the device, which might affect safety, appropriate and immediate
measures must be taken, that exclude an endangerment of persons and domestic animals and
property.
●
Current circuits which are connected to the device have to be sufficiently protected against
hazardous voltage (SELV according to EN 60950-1).
●
The ECS-PCIe/FPGA may only be driven by power supply current circuits, that are contact
protected. A power supply, that provides a safety extra-low voltage (SELV) according to EN
60950-1, complies with these conditions.
●
The device has to be securely installed in the control cabinet before commissioning.
●
Protect the ECS-PCIe/FPGA from dust, moisture and steam.
●
Protect the ECS-PCIe/FPGA from shocks and vibrations.
●
The ECS-PCIe/FPGA may become warm during normal use. Always allow adequate ventilation
around the ECS-PCIe/FPGA and use care when handling.
●
Do not operate the ECS-PCIe/FPGA adjacent to heat sources and do not expose it to
unnecessary thermal radiation. Ensure an ambient temperature as specified in the technical
data.
DANGER
Hazardous Voltage - Risk of electric shock due to unintentional contact with
uninsulated live parts with high voltages inside of the system into which the ECS-
PCIe/FPGA is to be integrated.
→ Disconnect all hazardous voltages (mains voltage) before opening the system.
→ Ensure the absence of voltage before starting any electrical work
NOTICE
Electrostatic discharges may cause damage to electronic components.
To avoid this, perform the steps described on page 18 before you touch the ECS-
PCIe/FPGA, in order to discharge the static electricity from your body
Qualified Personnel
This documentation is directed exclusively towards personnel qualified in control and automation
engineering. The installation and commissioning of the product may only be carried out by qualified
personnel, which is authorized to put devices, systems and electric circuits into operation according
to the applicable national standards of safety engineering.
Conformity
The ECS-PCIe/FPGA is an industrial product and meets the demands of the EU regulations and
EMC standards printed in the conformity declaration at the end of this manual.
Warning:
In a residential, commercial or light industrial environment the ECS-PCIe/FPGA may
cause radio interferences in which case the user may be required to take adequate
measures.
The ECS-PCIe/FPGA is a sub-assembly intended for incorporation into an apparatus. The
manufacturer of the final system must decide whether additional EMC or EMI protection
requirements are necessary.

Page 6 of 28
Hardware Manual Doc.-Nr.: E.1106.21 /Rev. 1.1
ECS-PCIe/FPGA
Data Safety
This device is equipped with an Ethernet or other interface which is suitable to establish a connection
to data networks. Depending on the software used on the device, these interfaces may allow
attackers to compromise normal function, get illegal access or cause damage.
esd does not take responsibility for any damage caused by the device if operated at any networks.
It is the responsibility of the device's user to take care that necessary safety precautions for the
device's network interface are in place.
Intended Use
The intended use of the ECS-PCIe/FPGA is the operation as PCI Express® EtherCAT® Slave
Interface. The guarantee given by esd does not cover damages which result from improper use,
usage not in accordance with regulations or disregard of safety instructions and warnings.
●
The ECS-PCIe/FPGA is intended for installation in PCI Express slots only.
●
The operation of the ECS-PCIe/FPGA in hazardous areas, or areas exposed to potentially
explosive materials is not permitted.
●
The operation of the ECS-PCIe/FPGA for medical purposes is prohibited.
Service Note
The ECS-PCIe/FPGA does not contain any parts that require maintenance by the user. The ECS-
PCIe/FPGA does not require any manual configuration of the hardware. Unauthorized intervention
in the device voids warranty claims
Disposal
Devices which have become defective in the long run have to be disposed in an appropriate way or
have to be returned to the manufacturer for proper disposal. Please, make a contribution to
environmental protection.
Typographical Conventions
Throughout this manual the following typographical conventions are used to distinguish technical terms.
Convention
Example
File and path names
/dev/null or <stdio.h>
Function names
open()
Programming constants
NULL
Programming data types
uint32_t
Variable names
Count
Number Representation
All numbers in this document are base 10 unless designated otherwise. Hexadecimal numbers have a prefix
of 0x. For example, 42 is represented as 0x2A in hexadecimal notation.
Abbreviations
API
Application Programming Interface
CAN
Controller Area Network
CPU
Central Processing Unit
CiA
CAN in Automation
HW
Hardware
I/O
Input/Output
LSB
Least Significant Bit
MSB
Most Significant Bit
n.a.
not applicable
OS
Operating System
SDK
Software Development Kit

ECS-PCIe/FPGA
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Table of Contents
Safety Instructions ..........................................................................................................................5
1Quick Start ..................................................................................................................................9
1.1 Requirements.......................................................................................................................9
1.2 Steps ...................................................................................................................................9
1.3 Driver Installation...............................................................................................................10
1.3.1 Windows..................................................................................................................10
1.3.2 Linux........................................................................................................................10
1.4 Sample Slave Application ..................................................................................................11
1.5 Testing the Sample App. with the Workbench....................................................................11
1.6 Further Steps.....................................................................................................................13
2Overview...................................................................................................................................14
2.1 2.1 Description...................................................................................................................14
3PCB View with Connectors........................................................................................................15
4LEDs.........................................................................................................................................16
4.1 Position of the LEDs...........................................................................................................16
4.2 LED Indication....................................................................................................................16
4.2.1 Status LEDs.............................................................................................................17
4.2.2 EtherCAT LEDs.......................................................................................................17
5Hardware Installation.................................................................................................................18
6Technical Data..........................................................................................................................19
6.1.1 General Technical Data...........................................................................................19
6.2 Hardware Components...................................................................................................... 19
6.3 FPGA................................................................................................................................. 20
6.4 PCI Express Interface........................................................................................................ 20
6.5 Ethernet Interface .............................................................................................................. 20
6.6 Temperature Sensor..........................................................................................................20
6.7 SYNC / LATCH Interface ...................................................................................................21
6.8 User-I/O on X600............................................................................................................... 21
6.9 User-I/O on X601............................................................................................................... 21
6.10Software Support...............................................................................................................22
7Connector Assignments ............................................................................................................23
7.1 Connector Assignment RJ45.............................................................................................. 23
7.2 X600 26 Pin Header...........................................................................................................24
7.2.1 X600 26 Pin Header configured for LVTTL I/O.........................................................24
7.2.2 X600 26 Pin Header configured for differential I/O...................................................25
7.3 X601 26 pin header for user I/O......................................................................................... 26
7.4 JTAG FPGA (X1300) .........................................................................................................26
8Declaration of Conformity.......................................................................................................... 27
9Order Information......................................................................................................................28

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ECS-PCIe/FPGA
List of Tables
Table 1: LED states (according to ETG.1300-documentation)......................................................16
Table 2: Description of Status LEDs.............................................................................................17
Table 3: Description of Link/Activity LEDs ....................................................................................17
Table 4: General data of the module ............................................................................................19
Table 5: Hardware components....................................................................................................19
Table 6: FPGA .............................................................................................................................20
Table 7: Data of PCI Express interface.........................................................................................20
Table 8: Data of the EtherCAT interface .......................................................................................20
Table 9: Data of the temperature sensor ......................................................................................20
Table 10: Data of SYNC/LATCH interface ....................................................................................21
Table 11: Data of User-I/O interface on X600...............................................................................21
Table 12: Data of User-I/O interface on X601...............................................................................21
Table 13: Order information hardware..........................................................................................28
Table 14: Available manuals ........................................................................................................28
List of Figures
Figure 1: Windows Device Manager.............................................................................................10
Figure 2: Update Driver Software.................................................................................................10
Figure 3: Installing ESI to EtherCAT Workbench (picture detail) ..................................................11
Figure 4: Scan result showing “Slave 1 (ECS-PCIe/FPGA)”, (picture detail) ................................11
Figure 5: Process data view with “Slave 1 (ECS-PCIe/FPGA)”, (picture detail) ............................12
Figure 6: Block circuit diagram.....................................................................................................14
Figure 7: PCB top view of ECS-PCIe/FPGA-LP...........................................................................15
Figure 8: Connectors and LEDs of ECS-PCIe/FPGA...................................................................16

Quick Start
ECS-PCIe/FPGA
Hardware Manual Doc.-Nr.: E.1106.21/ 1.1
Page 9 of 28
1 Quick Start
This chapter describes first steps with the ECS-PCIe/FPGA. It uses an esd EtherCAT Slave Stack
sample application and the esd EtherCAT Workbench to show the functionality of the ECS-
PCIe/FPGA.
•EtherCAT knowledge. The ETG (EtherCAT Technology Group, http://ethercat.org) has
several brochures/introductions that should be studied first
•Windows PC
◦with esd EtherCAT Workbench*
◦with network interface card (100 BASE-TX capable) dedicated to EtherCAT
◦with ANSI C compiler etc. (Makefile/Project for Microsoft Visual Studio and GCC
included)
•esd EtherCAT Slave Stack*
•Network cable to connect the ECS-PCIe/FPGA to the PC’s NIC (where the EtherCAT
Master will run)
* Demo version of the EtherCAT Workbench and full version of the EtherCAT Stack object for Windows and
Linux are included in delivery of ECS-PCIe/FPGA
Following steps have to be performed:
1. Install the ECS-PCIe/FPGA into your system, as described in chapter “Hardware
Installation”.
2. Install the esd EtherCAT Slave Stack according to its manual
(Usually this is just running its “setup.exe” etc.)
3. Install the ECS-PCIe/FPGA driver, see section 1.3 “Driver Installation”
(It is within the Stack installation’s “driver” folder)
4. Install the esd EtherCAT Workbench according to its manual
(Usually this is just running its “setup.exe” etc.)
5. Connect the EtherCAT port “IN” of the ECS-PCIe/FPGA to the NIC of the PC
6. Start the Sample Slave Application, see section 1.4 “Sample Slave Application “
7. Start the Workbench and run the tests, see section 1.5 “Testing the Sample App. with the
Workbench
1.1 Requirements
1.2 Steps

Quick Start
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ECS-PCIe/FPGA
1.3.1Windows
Open the Device Manager, select the device, and choose Update Driver Software as shown in
Figure 1:
Figure 1: Windows Device Manager
with esd EtherCAT card displayed as
“Network Controller” (picture detail)
When you are asked where to look for the driver files select “Browse my computer for driver
software”.
Select the folder that matches your operating system (e.g. “...\driver\ECS-...\win64\”
when using 64-bit Windows) and click Next:
Figure 2: Update Driver Software
1.3.2Linux
The Linux driver for the esd EtherCAT slave device (ECS-PCIe/FPGA) is usually delivered as
source code. Please refer to “.../driver/ECS-.../linux/README” from the extracted Slave
Stack Linux archive.
1.3 Driver Installation

Quick Start
ECS-PCIe/FPGA
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Page 11 of 28
The sample applications are installed as source code only. Please refer to the Slave Stack manual
for details on how to build it. This document refers to the “complex.c” sample.
This sample application contains input and output variables:
- Input variables are set by the application, i.e., they will be read by the Workbench.
- Output variables are written by the Workbench (and the sample application displays them when
changed).
The Slave and all its variables etc. are described in the Slave’s ESI (EtherCAT Slave Information).
This ESI exists as binary within the card’s EtherCAT EEPROM and as .xml file for configuration
tools such as the EtherCAT Workbench.
In case of changes to the application the EEPROM content and .xml ESI file must be adapted
accordingly.
At first the .xml ESI file must be imported into the Workbench:
(It is installed in the Slave Stack’s “driver\ECS-...\ESI\”folder.)
When the Workbench is running, this can be done by the menu entry Copy ESI file(s) to slave
library (under menu item Tools), see Figure 3. Otherwise, the Workbench's start menu entry Open
slave library can be used to copy the file manually.
Figure 3: Installing ESI to EtherCAT Workbench (picture detail)
After the Workbench was (re)started a slave scan can be performed. Use the Online button to let
the Workbench connect to its included Master and click the Scan button then:
Figure 4: Scan result showing “Slave 1 (ECS-PCIe/FPGA)”, (picture detail)
1.4 Sample Slave Application
1.5 Testing the Sample App. with the Workbench

Quick Start
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ECS-PCIe/FPGA
INFORMATION
These samples show your ECS-PCIe/FPGA described as “Slave 1 (ECS-.....)”, because
the actions/behavior described here remain compatible for all esd's EtherCAT slave
devices.
After switching to online mode all slaves are in “Pre-Operational” state. In this state (e.g., indicated
by the orange symbol in Figure 4) no process data is exchanged.
Use the Free run button to switch your slave to “Operational” mode, see Figure 5.
Then open the Variables tab of Process Data/Image as shown in Figure 5.
On this page you see all process variables of the EtherCAT network. For this sample, the first two
entries belong to the ECS-PCIe/FPGA.
As described earlier, outputs are written, and inputs are read here. So click one of the two Reread
all buttons to have the input (“Slave 1 (ECS-PCIe/FPGA).RxPDO1.Input1”) read.
Figure 5: Process data view with “Slave 1 (ECS-PCIe/FPGA)”, (picture detail)
Double click the output (“Slave 1 (ECS-PCIe/FPGA).RxPDO1.Output1”) to write a new value to the
slave. The Slave sample application shows the new value in its console output, for example:
“[Application] *** output1 changed to 1234”
The value for the input is changed every second by the sample application, but it becomes visible
only by manual updates in the Workbench (the Reread all buttons etc.).

Quick Start
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Page 13 of 28
Study the Workbench and Slave Stack manuals to get more details about the steps performed here.
Then try to map the other variables (that already exist in the application and ESI) too and finally add
your own variables.
Do not forget to update the ESI accordingly. While many EtherCAT masters acquire most of the
slave information needed from the .xml ESI, others might rely solely on EEPROM ESI! (The binary
ESI can be created by the .xml ESI, e.g. with the Workbench. The .xml ESI is described in the
ETG.2000 document.)
You also must follow the ETG requirements defined in the EtherCAT Conformance Guide which can
be downloaded for free from the website of the EtherCAT TechnologyGroup http:\\ethercat.org. This
includes using your own EtherCAT vendor ID and testing the final product with the EtherCAT CTT
(Conformance Test Tool).
1.6 Further Steps

Overview
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ECS-PCIe/FPGA
2 Overview
In this hardware manual the ECS-PCIe/FPGA and the ECS-PCIe/FPGA-LP are described together.
Both versions only differ in the dimensions of the slot bracket, differences are noted.
Figure 6: Block circuit diagram
The ECS-PCIe/FPGA is an EtherCAT Slave controller board designed for the PCI Express bus.
It utilizes a Beckhoff IP core which is implemented in an Intel®FPGA and configured for 8 FMMUs,
8 Sync Managers, 60 kB DPRAM and 64-bit Distributed Clocks. The FPGA connects between the
PCI Express bus and the two Ethernet interfaces on the front panel.
Because of this simple hardware topology and the use of a “soft” controller the design offers a
maximum of flexibility and versatile application options.
The PCI Express system can act as an I/O node. An EtherCAT Master can use several EtherCAT
protocols like CoE, FoE and EoE to communicate with this EtherCAT Slave device.
Via pin header connectors equipped on the ECS-PCIe/FPGA 40 3.3 V LVTTL I/Os are available,
including the signals from the EtherCAT slave controller: 2x Sync and 2x Latch for system
synchronization. On request 16 I/Os can be configured as 8 I/Os with 2.5 V level LVDS.
The FPGA contains Bus Master DMA Support to offload the CPU from copying the output process
image data into the host memory. This is utilized by the esd EtherCAT Slave Stack.
Device drivers for Windows®and Linux®with documentation and EtherCAT Slave examples are
included in the scope of delivery. Drivers for other operating systems, especially real-time operating
systems, are available on request.
The EtherCAT Slave card is also available as PCI Express low-profile version (ECS-PCIe/FPGA-
LP).
For XMC and PMC systems similar boards are available (ECS-XMC/FPGA, ECS-PMC/FPGA).
2.1 2.1 Description

PCB View with Connectors
ECS-PCIe/FPGA
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Page 15 of 28
3 PCB View with Connectors
Figure 7: PCB top view of ECS-PCIe/FPGA-LP
NOTICE
Read chapter “Hardware Installation” on page 18, before you start with the installation of
the hardware!
Figure 7 shows the low-profile version ECS-PCIe/FPGA-LP. The ECS-PCIe/FPGA only differs in the
length of the slot bracket.
See also page 23 for signal assignment of the CAN connectors.

LEDs
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ECS-PCIe/FPGA
4 LEDs
Figure 8: Connectors and LEDs of ECS-PCIe/FPGA
Figure 8 shows the ECS-PCIe/FPGA. The low-profile version ECS-PCIe/FPGA-LP only differs in
the length of the slot bracket.
Indicator states
Description
blinking
LED blinking cycle: 200 ms on, 200 ms off.
flickering
LED blinking cycle: 50 ms on, 50 ms off.
single flash
LED blinking cycle: 200 ms on, 1000 ms off.
double flash
LED blinking cycle: 200 ms on, 200 ms off, 200 ms on, 1000 ms off.
Table 1: LED states (according to ETG.1300-documentation)
4.1 Position of the LEDs
4.2 LED Indication

LEDs
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4.2.1Status LEDs
The four status LEDs are
LED
Function
Colour
Indicator
State
Description
LED name in
schematic
diagram
U1
User LED1
yellow
user defined via FPGA and driver
LED800A
U2
User LED2
yellow
user defined via FPGA and driver
LED900A
RUN
RUN LED
green
off
Init
LED800C
flickering
BootStrap
blinking
Pre-Operational
single flash
Safe-Operational
on
Operational
ERR
Error LED
green
off
no error
LED900C
blinking
“EtherCAT state”- change failed
single flash
“EtherCAT state”-change
because of configuration error
double flash
SM watchdog triggered
Table 2: Description of Status LEDs
4.2.2EtherCAT LEDs
The Link/Activity LEDs and the User LEDs U3 and U4 are integrated in the RJ45 sockets of
EtherCAT ports IN and OUT.
LED
Function
Colour
Indicator
State
Description
EtherCAT
Port
U3
User LED1
green
-
user defined via FPGA and driver
IN
L/A
Link/Activity
port IN
yellow
off
no Ethernet link
blinking
Ethernet link is established,
Ethernet Activity (Receiving Ethernet
data packages)
U4
User LED1
green
-
user defined via FPGA and driver
OUT
L/A
Link/Activity
port OUT
yellow
off
no Ethernet link
blinking
Ethernet link is established,
Ethernet Activity (Receiving Ethernet
data packages)
Table 3: Description of Link/Activity LEDs

Hardware Installation
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ECS-PCIe/FPGA
5 Hardware Installation
NOTICE
Read the safety instructions at the beginning of this document carefully before you
start with the hardware installation!
WARNING
Hazardous Voltage - Risk of electric shock due to unintentional contact with
uninsulated live parts with high voltages inside of the system into which the ECS-
PCIe/FPGA is to be integrated.
→
→
Disconnect all hazardous voltages (mains voltage) before opening the system.
Ensure the absence of voltage before starting any electrical work.
NOTICE
Electrostatic discharges may cause damage to electronic components.
→
→
To avoid this, please discharge the static electricity from your body by touching the
metal case of the system before you touch the ECS-PCIe/FPGA.
Furthermore, you should prevent your clothes from touching the ECS-PCIe/FPGA,
because your clothes might be electrostatically charged as well.
Procedure:
1.
Switch off your system and all connected peripheral devices (monitor, printer, etc.).
2.
Discharge your body as described above.
3.
Disconnect the system from the mains.
Make sure that no risk arises from the system into which the ECS-PCIe/FPGA shall be
inserted.
DANGER
Hazardous Voltage
Risk of electric shock due to unintentional contact with uninsulated live parts with
high voltages.
→
→
→
→
Disconnect all hazardous voltages (mains voltage) before opening the system.
If the system does not have a flexible mains cable, but is directly connected to
mains, disconnect the power supply via the safety fuse and make sure that the fuse
cannot switch on again unintentionally (with caution label e.g.).
Ensure the absence of voltage before starting any electrical work.
Cover or block off adjacent live parts.
4.
Open the case if necessary.
5.
Insert the ECS-PCIe/FPGA board into the selected PCI Express slot. Carefully push the board
down until it snaps into place. If applicable secure the front panel in place with the screw.
6.
Close the system's case again.
7.
Connect the EtherCAT interfaces via the connectors in the front panel of the ECS-PCIe/FPGA.
8.
Connect the system to mains again (mains connector or safety fuse).
9.
Switch on the system and the peripheral devices.
13.
End of hardware installation.
14.
Set the interface properties in your operating system. Refer to the documentation of the
operating system.

Technical Data
ECS-PCIe/FPGA
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6 Technical Data
6.1.1General Technical Data
Power supply
voltage
Nominal voltage: 3.3 V ±0.3% via PCIe
Nominal current: I3,3VTYPICAL = 500 mA, I3,3VMAX = 600 mA)
Power
consumption
PMAX = 3 W
Connectors
IN
OUT
X600
X601
(8 pin RJ45, X800) - EtherCAT port Input
(8 pin RJ45, X900) - EtherCAT port Output
(26-pin shrouded pin header, X600), 2x Sync, 2x Latch, 3,3 V,
LVTTL-IO;
a customized option, in which the I/Os are configured as LVDS
signals, is available on request
(26-pin shrouded pin header, X601) LVTTL-IO - For future use!
Only for test- and programming purposes:
JTAG
(5-pin JTAG pin header) programming, debugging interface
Temperature
range
Operation: 0...65 °C ambient temperature, passive cooling
Storage: -25...70 °C
Transport: -25...70 °C
Humidity
max. 90%, non-condensing
Protection
class
IP20 in mounted position
Dimensions
PCB: 120 mm x 68.9 mm x 14 mm without slot bracket
(length x width x height)
Slot bracket: width: 18.42 mm
height:
ECS-PCIe/FPGA: Full-height: 120mm
ECS-PCIe/FPGA-LP: Low-profile: 79,2mm
Weight
ECS-PCIe/FPGA: 80 g
ECS-PCIe/FPGA-LP: 75 g
Table 4: General data of the module
FPGA
Intel Cyclone V GX
Serial NOR FLASH
up to 16 Mbyte –for active serial Boot Option
Ethernet
2 x Micrel KSZ8081MNX
Serial I2C EEPROM
32 KBit
I2C Temperature Sensor
Texas Instruments TMP100
Table 5: Hardware components
6.2 Hardware Components

Technical Data
Page 20 of 28
Hardware Manual Doc.-Nr.: E.1106.21 /Rev. 1.1
ECS-PCIe/FPGA
Type
Intel Cyclone V GX, FPGA 484
IP-core
Beckhoff® IP-core
- contains 60 kByte ESC DPRAM
- supports 64-bit timestamps (for DC, Sync and Latch values)
- supports 8 EtherCAT SyncManagers
- supports 8 EtherCAT FMMUs
Table 6: FPGA
PCIe endpoint
FPGA
PCIe port
According to PCI Express Specification R1.0a
Lanes
One Lane PCI Express Link
Form factor
Standard and low-profile version available
Connectors
PCI Express card edge
Table 7: Data of PCI Express interface
Number
1
Standard
100BASE-TX, 100Mbit/s according to IEEE 802.3
Controller
EtherCAT Slave Controller Beckhoff IP Core integrated in FPGA
+ 2x MII Phy (Micrel KSZ8081MNX)
Electrical isolation
via transformer, integrated in connector
Ports
IN and OUT
Connector
2 x RJ45 socket with separate LEDs for status indication (see “LED
Indication”page 16)
Table 8: Data of the EtherCAT interface
Number
1
Type
Texas Instruments TMP100
Accuracy / Resolution
±2.0°C from -25°C to 85°C / 9Bit
Interface
I2C
Controller
Integrated in FPGA
Table 9: Data of the temperature sensor
6.3 FPGA
6.4 PCI Express Interface
6.5 Ethernet Interface
6.6 Temperature Sensor