ESD ECS-PCIe/FPGA User manual

ECS-PCIe/FPGA
Hardware Manual Doc.-Nr.: E.1106.21 /-Rev 1.1
Page 1 of 28
ECS-PCIe/FPGA
PCI Express® EtherCAT® Slave Interface
ESC-PCIe/FPGA-LP (E.1106.04)
Hardware Manual
to Products E.1106.02, E.1106.04

Page 2 of 28
Hardware Manual Doc.-Nr.: E.1106.21 /Rev. 1.1
ECS-PCIe/FPGA
This manual contains important information and instructions on safe and efficient
handling of the ECS-PCIe/FPGA. Carefully read this manual before commencing any
work and follow the instructions.
The manual is a product component, please retain it for future use.
Trademark Notices
Intel® is a registered trademark of Intel Corporation or its subsidiaries in the U.S. and/or other countries
PCI Express® is a registered trademark of PCI-SIG.
EtherCAT® is registered trademark and patented technology, licensed by Beckhoff Automation GmbH, Germany.
All other trademarks, product names, company names or company logos used in this manual are reserved by their
respective owners.
Notes
The information in this document has been carefully checked and is believed to be entirely reliable.
esd electronics makes no warranty of any kind with regard to the material in this document and
assumes no responsibility for any errors that may appear in this document. In particular descriptions
and technical data specified in this document may not be constituted to be guaranteed product
features in any legal sense.
esd electronics reserves the right to make changes without notice to this, or any of its products, to
improve reliability, performance or design.
All rights to this documentation are reserved by esd electronics. Distribution to third parties, and
reproduction of this document in any form, whole or in part, are subject to esd electronics' written
approval.
© 2021 esd electronics gmbh, Hannover
esd electronics gmbh
Vahrenwalder Str. 207
30165 Hannover
Germany
Tel.:
[phone]
Fax:
[phone]
E-Mail:
[email protected]
Internet:
www.esd.eu

ECS-PCIe/FPGA
Hardware Manual Doc.-Nr.: E.1106.21/ 1.1
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Document Information
Document file:
I:\Texte\Doku\MANUALS\EtherCAT\ECS-PCIeFPGA\ECS-PCIeFPGA_Hardware_en_11.docx
Date of print:
2021-03-02
Document-type
number:
DOC0800
Hardware version.:
1.0
Document History
The changes in the document listed below affect changes in the hardware as well as changes in the
description of the facts, only.
Rev.
Chapter
Changes versus previous version
Date
1.0
-
First English manual
2016-10-10
1.1
2.1, 6.10
Note on Busmaster DMA Support inserted
2021-03-02
6.2, 6.3
Description of FPGA Type changed/corrected (Intel)
7.3
Description of Pin Assignment of Connector X601 changed
8
New Declaration of Conformity
Technical details are subject to change without further notice.

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Hardware Manual Doc.-Nr.: E.1106.21 /Rev. 1.1
ECS-PCIe/FPGA
Classification of Warning Messages and Safety Instructions
This manual contains noticeable descriptions, warning messages and safety instructions, which you
must follow to avoid personal injuries or death and property damage.
This is the safety alert symbol.
It is used to alert you to potential personal injury hazards. Obey all safety messages
and instructions that follow this symbol to avoid possible injury or death.
DANGER, WARNING, CAUTION
Depending on the hazard level the signal words DANGER, WARNING or CAUTION are used to
highlight safety instructions and warning messages. These messages may also include a warning
relating to property damage.
DANGER
Danger statements indicate a hazardous situation which, if not avoided, will result in
death or serious injury.
WARNING.
Warning statements indicate a hazardous situation that, if not avoided, could result in
death or serious injury.
CAUTION
Caution statements indicate a hazardous situation that, if not avoided, could result in
minor or moderate injury.
NOTICE
Notice statements are used to notify people on hazards that could result in things other than personal
injury, like property damage.
NOTICE
This NOTICE statement indicates that the device contains components sensitive to
electrostatic discharge.
NOTICE
This NOTICE statement contains the general mandatory sign and gives information that
must be heeded and complied with for a safe use.
INFORMATION
INFORMATION
Notes to point out something important or useful.

ECS-PCIe/FPGA
Hardware Manual Doc.-Nr.: E.1106.21/ 1.1
Page 5 of 28
Safety Instructions
●
When working with the ECS-PCIe/FPGA follow the instructions below and read the manual
carefully to protect yourself from injury and the ECS-PCIe/FPGA from damage.
●
The device is a built-in component. It is essential to ensure that the device is mounted in a way
that cannot lead to endangering or injury of persons or damage to objects.
●
Do not use damaged or defective cables to connect the ECS-PCIe/FPGA.
●
In case of damages to the device, which might affect safety, appropriate and immediate
measures must be taken, that exclude an endangerment of persons and domestic animals and
property.
●
Current circuits which are connected to the device have to be sufficiently protected against
hazardous voltage (SELV according to EN 60950-1).
●
The ECS-PCIe/FPGA may only be driven by power supply current circuits, that are contact
protected. A power supply, that provides a safety extra-low voltage (SELV) according to EN
60950-1, complies with these conditions.
●
The device has to be securely installed in the control cabinet before commissioning.
●
Protect the ECS-PCIe/FPGA from dust, moisture and steam.
●
Protect the ECS-PCIe/FPGA from shocks and vibrations.
●
The ECS-PCIe/FPGA may become warm during normal use. Always allow adequate ventilation
around the ECS-PCIe/FPGA and use care when handling.
●
Do not operate the ECS-PCIe/FPGA adjacent to heat sources and do not expose it to
unnecessary thermal radiation. Ensure an ambient temperature as specified in the technical
data.
DANGER
Hazardous Voltage - Risk of electric shock due to unintentional contact with
uninsulated live parts with high voltages inside of the system into which the ECS-
PCIe/FPGA is to be integrated.
→ Disconnect all hazardous voltages (mains voltage) before opening the system.
→ Ensure the absence of voltage before starting any electrical work
NOTICE
Electrostatic discharges may cause damage to electronic components.
To avoid this, perform the steps described on page 18 before you touch the ECS-
PCIe/FPGA, in order to discharge the static electricity from your body
Qualified Personnel
This documentation is directed exclusively towards personnel qualified in control and automation
engineering. The installation and commissioning of the product may only be carried out by qualified
personnel, which is authorized to put devices, systems and electric circuits into operation according
to the applicable national standards of safety engineering.
Conformity
The ECS-PCIe/FPGA is an industrial product and meets the demands of the EU regulations and
EMC standards printed in the conformity declaration at the end of this manual.
Warning:
In a residential, commercial or light industrial environment the ECS-PCIe/FPGA may
cause radio interferences in which case the user may be required to take adequate
measures.
The ECS-PCIe/FPGA is a sub-assembly intended for incorporation into an apparatus. The
manufacturer of the final system must decide whether additional EMC or EMI protection
requirements are necessary.

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Hardware Manual Doc.-Nr.: E.1106.21 /Rev. 1.1
ECS-PCIe/FPGA
Data Safety
This device is equipped with an Ethernet or other interface which is suitable to establish a connection
to data networks. Depending on the software used on the device, these interfaces may allow
attackers to compromise normal function, get illegal access or cause damage.
esd does not take responsibility for any damage caused by the device if operated at any networks.
It is the responsibility of the device's user to take care that necessary safety precautions for the
device's network interface are in place.
Intended Use
The intended use of the ECS-PCIe/FPGA is the operation as PCI Express® EtherCAT® Slave
Interface. The guarantee given by esd does not cover damages which result from improper use,
usage not in accordance with regulations or disregard of safety instructions and warnings.
●
The ECS-PCIe/FPGA is intended for installation in PCI Express slots only.
●
The operation of the ECS-PCIe/FPGA in hazardous areas, or areas exposed to potentially
explosive materials is not permitted.
●
The operation of the ECS-PCIe/FPGA for medical purposes is prohibited.
Service Note
The ECS-PCIe/FPGA does not contain any parts that require maintenance by the user. The ECS-
PCIe/FPGA does not require any manual configuration of the hardware. Unauthorized intervention
in the device voids warranty claims
Disposal
Devices which have become defective in the long run have to be disposed in an appropriate way or
have to be returned to the manufacturer for proper disposal. Please, make a contribution to
environmental protection.
Typographical Conventions
Throughout this manual the following typographical conventions are used to distinguish technical terms.
Convention
Example
File and path names
/dev/null or <stdio.h>
Function names
open()
Programming constants
NULL
Programming data types
uint32_t
Variable names
Count
Number Representation
All numbers in this document are base 10 unless designated otherwise. Hexadecimal numbers have a prefix
of 0x. For example, 42 is represented as 0x2A in hexadecimal notation.
Abbreviations
API
Application Programming Interface
CAN
Controller Area Network
CPU
Central Processing Unit
CiA
CAN in Automation
HW
Hardware
I/O
Input/Output
LSB
Least Significant Bit
MSB
Most Significant Bit
n.a.
not applicable
OS
Operating System
SDK
Software Development Kit

ECS-PCIe/FPGA
Hardware Manual Doc.-Nr.: E.1106.21/ 1.1
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Table of Contents
Safety Instructions ..........................................................................................................................5
1Quick Start ..................................................................................................................................9
1.1 Requirements.......................................................................................................................9
1.2 Steps ...................................................................................................................................9
1.3 Driver Installation...............................................................................................................10
1.3.1 Windows..................................................................................................................10
1.3.2 Linux........................................................................................................................10
1.4 Sample Slave Application ..................................................................................................11
1.5 Testing the Sample App. with the Workbench....................................................................11
1.6 Further Steps.....................................................................................................................13
2Overview...................................................................................................................................14
2.1 2.1 Description...................................................................................................................14
3PCB View with Connectors........................................................................................................15
4LEDs.........................................................................................................................................16
4.1 Position of the LEDs...........................................................................................................16
4.2 LED Indication....................................................................................................................16
4.2.1 Status LEDs.............................................................................................................17
4.2.2 EtherCAT LEDs.......................................................................................................17
5Hardware Installation.................................................................................................................18
6Technical Data..........................................................................................................................19
6.1.1 General Technical Data...........................................................................................19
6.2 Hardware Components...................................................................................................... 19
6.3 FPGA................................................................................................................................. 20
6.4 PCI Express Interface........................................................................................................ 20
6.5 Ethernet Interface .............................................................................................................. 20
6.6 Temperature Sensor..........................................................................................................20
6.7 SYNC / LATCH Interface ...................................................................................................21
6.8 User-I/O on X600............................................................................................................... 21
6.9 User-I/O on X601............................................................................................................... 21
6.10Software Support...............................................................................................................22
7Connector Assignments ............................................................................................................23
7.1 Connector Assignment RJ45.............................................................................................. 23
7.2 X600 26 Pin Header...........................................................................................................24
7.2.1 X600 26 Pin Header configured for LVTTL I/O.........................................................24
7.2.2 X600 26 Pin Header configured for differential I/O...................................................25
7.3 X601 26 pin header for user I/O......................................................................................... 26
7.4 JTAG FPGA (X1300) .........................................................................................................26
8Declaration of Conformity.......................................................................................................... 27
9Order Information......................................................................................................................28

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Hardware Manual Doc.-Nr.: E.1106.21 /Rev. 1.1
ECS-PCIe/FPGA
List of Tables
Table 1: LED states (according to ETG.1300-documentation)......................................................16
Table 2: Description of Status LEDs.............................................................................................17
Table 3: Description of Link/Activity LEDs ....................................................................................17
Table 4: General data of the module ............................................................................................19
Table 5: Hardware components....................................................................................................19
Table 6: FPGA .............................................................................................................................20
Table 7: Data of PCI Express interface.........................................................................................20
Table 8: Data of the EtherCAT interface .......................................................................................20
Table 9: Data of the temperature sensor ......................................................................................20
Table 10: Data of SYNC/LATCH interface ....................................................................................21
Table 11: Data of User-I/O interface on X600...............................................................................21
Table 12: Data of User-I/O interface on X601...............................................................................21
Table 13: Order information hardware..........................................................................................28
Table 14: Available manuals ........................................................................................................28
List of Figures
Figure 1: Windows Device Manager.............................................................................................10
Figure 2: Update Driver Software.................................................................................................10
Figure 3: Installing ESI to EtherCAT Workbench (picture detail) ..................................................11
Figure 4: Scan result showing “Slave 1 (ECS-PCIe/FPGA)”, (picture detail) ................................11
Figure 5: Process data view with “Slave 1 (ECS-PCIe/FPGA)”, (picture detail) ............................12
Figure 6: Block circuit diagram.....................................................................................................14
Figure 7: PCB top view of ECS-PCIe/FPGA-LP...........................................................................15
Figure 8: Connectors and LEDs of ECS-PCIe/FPGA...................................................................16

Quick Start
ECS-PCIe/FPGA
Hardware Manual Doc.-Nr.: E.1106.21/ 1.1
Page 9 of 28
1 Quick Start
This chapter describes first steps with the ECS-PCIe/FPGA. It uses an esd EtherCAT Slave Stack
sample application and the esd EtherCAT Workbench to show the functionality of the ECS-
PCIe/FPGA.
•EtherCAT knowledge. The ETG (EtherCAT Technology Group, http://ethercat.org) has
several brochures/introductions that should be studied first
•Windows PC
◦with esd EtherCAT Workbench*
◦with network interface card (100 BASE-TX capable) dedicated to EtherCAT
◦with ANSI C compiler etc. (Makefile/Project for Microsoft Visual Studio and GCC
included)
•esd EtherCAT Slave Stack*
•Network cable to connect the ECS-PCIe/FPGA to the PC’s NIC (where the EtherCAT
Master will run)
* Demo version of the EtherCAT Workbench and full version of the EtherCAT Stack object for Windows and
Linux are included in delivery of ECS-PCIe/FPGA
Following steps have to be performed:
1. Install the ECS-PCIe/FPGA into your system, as described in chapter “Hardware
Installation”.
2. Install the esd EtherCAT Slave Stack according to its manual
(Usually this is just running its “setup.exe” etc.)
3. Install the ECS-PCIe/FPGA driver, see section 1.3 “Driver Installation”
(It is within the Stack installation’s “driver” folder)
4. Install the esd EtherCAT Workbench according to its manual
(Usually this is just running its “setup.exe” etc.)
5. Connect the EtherCAT port “IN” of the ECS-PCIe/FPGA to the NIC of the PC
6. Start the Sample Slave Application, see section 1.4 “Sample Slave Application “
7. Start the Workbench and run the tests, see section 1.5 “Testing the Sample App. with the
Workbench
1.1 Requirements
1.2 Steps

Quick Start
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Hardware Manual Doc.-Nr.: E.1106.21 /Rev. 1.1
ECS-PCIe/FPGA
1.3.1Windows
Open the Device Manager, select the device, and choose Update Driver Software as shown in
Figure 1:
Figure 1: Windows Device Manager
with esd EtherCAT card displayed as
“Network Controller” (picture detail)
When you are asked where to look for the driver files select “Browse my computer for driver
software”.
Select the folder that matches your operating system (e.g. “...\driver\ECS-...\win64\”
when using 64-bit Windows) and click Next:
Figure 2: Update Driver Software
1.3.2Linux
The Linux driver for the esd EtherCAT slave device (ECS-PCIe/FPGA) is usually delivered as
source code. Please refer to “.../driver/ECS-.../linux/README” from the extracted Slave
Stack Linux archive.
1.3 Driver Installation