Espressif Systems ESP32-S2 Instruction Manual

ESP32S2
Hardware Design Guidelines
Version 1.1
Espressif Systems
Copyright © 2020
www.espressif.com

About This Document
The guidelines outline recommended design practices when developing standalone or add-on systems based on
the ESP32-S2 series of products, including ESP32-S2 SoCs, ESP32-S2 modules and ESP32-S2 development
boards.
Document Updates
Please always refer to the latest version on https://www.espressif.com/en/support/download/documents.
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PROVIDED AS IS WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABIL-
ITY, NON-INFRINGEMENT, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE
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All trade names, trademarks and registered trademarks mentioned in this document are property of their respective
owners, and are hereby acknowledged.
Copyright © 2020 Espressif Systems (Shanghai) Co., Ltd. All rights reserved.

Contents
1 Overview 1
2 Schematic Checklist 2
2.1 Power Supply 3
2.1.1 Digital Power Supply 3
2.1.2 Analog Power Supply 4
2.2 Power-on Sequence and System Reset 5
2.2.1 Power-on Sequence 5
2.2.2 Reset 5
2.3 Flash (compulsory) and SRAM (optional) 5
2.4 Crystal Oscillator 6
2.4.1 External Clock Source (compulsory) 6
2.4.2 RTC (optional) 7
2.5 RF 8
2.6 UART 9
2.7 USB 9
2.8 ADC 9
2.9 Touch Sensor 9
3 PCB Layout Design 10
3.1 General Principles of PCB Layout 10
3.2 Positioning an ESP32-S2 Module on a Base Board 11
3.3 Power Supply 12
3.4 Crystal Oscillator 13
3.5 RF 14
3.6 Flash and PSRAM 15
3.7 UART 16
3.8 USB 16
3.9 Touch Sensor 16
3.10 Typical Layout Problems and Solutions 19
3.10.1 Q: The current ripple is not large, but the TX performance of RF is rather poor. 19
3.10.2 Q: The power ripple is small, but RF TX performance is poor. 19
3.10.3 Q: When ESP32-S2 sends data packages, the power value is much higher or lower than the
target power value, and the EVM is relatively poor. 20
3.10.4 Q: TX performance is not bad, but the RX sensitivity is low. 20
4 Hardware Development 21
4.1 ESP32-S2 Modules 21
4.2 ESP32-S2 Development Boards 21
Revision History 22

List of Figures
1 ESP32-S2 Schematic 2
2 ESP32-S2 Digital Power Supply Pins 3
3 ESP32-S2 Analog Power Supply Pins 4
4 ESP32-S2 Flash and SRAM 6
5 Schematic for ESP32-S2’s Crystal 7
6 Schematic for ESP32-S2’s Crystal Oscillator 7
7 Schematic for ESP32-S2’s External Crystal (RTC) 7
8 Schematic of External Oscillator 8
9 ESP32-S2 RF Matching Schematic 8
10 ESP32-S2 PCB Layout 10
11 ESP32-S2 Module Antenna Position on Base Board 11
12 Keepout Zone for ESP32-S2 Module’s Antenna on the Base Board 12
13 ESP32-S2 Power Traces in a Four-layer PCB Design 13
14 ESP32-S2 Crystal Oscillator Layout 14
15 ESP32-S2 RF Layout in a Four-layer PCB Design 15
16 ESP32-S2 PCB Stack-up Design 15
17 ESP32-S2 Flash and PSRAM Layout 16
18 A Typical Touch Sensor Application 17
19 Electrode Pattern Requirements 17
20 Sensor Track Routing Requirements 18
21 Shied Electrode and Protective Sensor 19

1. Overview
1. Overview
ESP32-S2 is a highly-integrated, low-power, 2.4 GHz Wi-Fi System-on-Chip (SoC) solution. With its state-of-the-
art power and RF performance, this SoC is an ideal choice for a wide variety of application scenarios relating to
Internet of Things (IoT), wearable electronics and smart home.
At the core of this chip is an Xtensa® 32-bit LX7 CPU that operates at up to 240 MHz. The chip supports application
development, without the need for a host MCU.
ESP32-S2 includes a Wi-Fi subsystem that integrates a Wi-Fi MAC, Wi-Fi radio and baseband, RF switch, RF balun,
power amplifier, low noise amplifier (LNA), etc. The chip is fully compliant with the IEEE 802.11b/g/n protocol and
offers a complete Wi-Fi solution.
ESP32-S2 also integrates advanced calibration circuitries that allow the solution to dynamically adjust itself to
remove external circuit imperfections or adjust to changes in external conditions. As such, the mass production
of ESP32-S2 solutions does not require expensive and specialized Wi-Fi test equipment.
For more information about ESP32-S2, please refer to ESP32-S2 Datasheet.
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2. Schematic Checklist
2. Schematic Checklist
ESP32-S2’s integrated circuitry requires only 20 resistors, capacitors and inductors, one crystal and one SPI flash
memory chip. ESP32-S2 integrates a Wi-Fi MAC, Wi-Fi radio and baseband, RF switch, RF balun, power amplifier,
low noise amplifier (LNA), and advanced calibration circuitries.
ESP32-S2’s high integration allows for simple peripheral circuit design. This chapter details ESP32-S2 schematics.
ESP32-S2 schematic is shown in Figure 1.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
The values of C11, L2 and C12
vary with the actual PCB oard.
The values of C1 and C4 vary with
the selection of the crystal.
The value of R4 varies with the actual
PCB oard.
NC: No component.
(Optional)
SPICLK
SPICS0
SPIHD
SPICS1
SPID
SPIWP
SPIQ
SPICLK
SPIHD
SPID
SPIWP
SPIQ
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO19 GPIO20 GPIO21
GPIO33
GPIO34
GPIO35
GPIO36
GPIO37
GPIO38
SPICS1GPIO26
SPICS0
LNA_INRF_ANT
GPIO39
GPIO40
GPIO41
GPIO42
U0RXD
GPIO45
GPIO46
CHIP_PU
U0TXD
SPICLK
GPIO18
SPID
SPIQ
SPIWP
SPIHD
VDD_SPI
VDD_SPI
GND
GND GND GND
VDD33
GND GND GND
GNDGND
GND
GND
VDD33
VDD33
GND
GNDGND
VDD33
GND
GNDGND
VDD33
GND
VDD_SPI
GND
GND
GND
GND
VDD33
R13 0
C11
TBD
C13
0.1uF
C12
TBD
C4
TBD
R3 499
R11 10K
C14
1uF
R8
10K(NC)
C9
TBD
R14 0
U1 ESP32-S2
VDDA
1
LNA_IN
2
VDD3P3
3
VDD3P3
4
GPIO0
5
GPIO1
6
GPIO2
7
GPIO3
8
GPIO4
9
GPIO5
10
GPIO6
11
GPIO7
12
GPIO10
15
GPIO11
16
GPIO12
17
GPIO13
18
GPIO14
19
XTAL_32K_P
21 VDD3P3_RTC 20
XTAL_32K_N
22
DAC_1
23
DAC_2
24
GPIO19
25
GPIO20
26
VDD_SPI 30
SPICS1 29
SPIWP 32
SPICS0 33
SPIQ 35
SPID 36
SPICLK 34
GPIO33 37
GND 57
GPIO34 38
GPIO35 39
MTCK 43
GPIO46 55
VDDA 51
XTAL_N 52
XTAL_P 53
MTMS 47 MTDO 44
U0TXD 48
VDD3P3_CPU 45
CHIP_PU 56
VDDA 54
MTDI 46
GPIO8
13
GPIO9
14
VDD3P3_RTC_IO
27
GPIO21
28
SPIHD 31
GPIO36 40
GPIO37 41
GPIO38 42
U0RXD 49
GPIO45 50
L1 2.0nH
C6
10uF
R15 0
C2
100pF
Y1
40MHz (±10ppm)
XIN
1
GND
2XOUT 3
GND 4
C10
0.1uF
U2
FLASH-3V3
/CS
1
DO 2
/WP 3
GND
4
DI 5
CLK
6
/HOLD
7
VCC 8
C7
1uF
L2 TBD
ANT2
PCB ANT
1
2
C1
TBD
U3
PSRAM-3V3
VDD 8
VSS
4
CS
1
SCLK
6
SIO3
7SIO2 3
SO/SIO1 2
SI/SIO0 5
R10 0
C16
0.1uF
C3
1uF
C15
0.1uF
R16 0
R4
0
C5
0.1uF
R9
10K(NC)
C8
0.1uF
Figure 1: ESP32S2 Schematic
Any basic ESP32-S2 circuit design may be broken down into nine major sections:
• Power supply
• Power-on sequence and system reset
• Flash and SRAM (optional)
• Crystal oscillator
• RF
• UART
• USB
• ADC
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2. Schematic Checklist
• Touch Sensor
2.1 Power Supply
For further details of using the power supply pins, please refer to Section Power Scheme in ESP32-S2 Datasheet.
2.1.1 Digital Power Supply
Pin27 and pin45 are the power supply pins for RTC IO and CPU IO, in a voltage range of 3.0 V ~3.6 V and 2.8 V ~
3.6 V, respectively. We recommend adding extra 0.1 µF capacitors close to each digital power supply pin.
VDD_SPI can work as the power supply for the external device at either 1.8 V (when GPIO45 is 1 during boot),
or 3.3 V (when GPIO45 is 0 and at default state during boot). We recommend adding extra 0.1 µF and 1 µF
capacitors close to VDD_SPI.
• When VDD_SPI operates at 1.8 V, it can be generated from ESP32-S2’s internal LDO. The maximum current
this LDO can offer is 40 mA, and the output voltage range is 1.8 V ~3.6 V.
• When VDD_SPI operates at 3.3 V, it is driven directly by VDD3P3_RTC_IO through a 5 Ωresistor, therefore,
there will be some voltage drop from VDD3P3_RTC_IO.
VDD_SPI can also be driven by an external power supply.
The schematic for ESP32-S2 digital power supply pins is shown in Figure 2.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
The values of C11, L2 and C12
vary with the actual PCB oard.
The values of C1 and C4 vary with
the selection of the crystal.
The value of R4 varies with the actual
PCB oard.
NC: No component.
(Optional)
SPICLK
SPICS0
SPIHD
SPICS1
SPID
SPIWP
SPIQ
SPICLK
SPIHD
SPID
SPIWP
SPIQ
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO19 GPIO20 GPIO21
GPIO33
GPIO34
GPIO35
GPIO36
GPIO37
GPIO38
SPICS1GPIO26
SPICS0
LNA_INRF_ANT
GPIO39
GPIO40
GPIO41
GPIO42
U0RXD
GPIO45
GPIO46
CHIP_PU
U0TXD
SPICLK
GPIO18
SPID
SPIQ
SPIWP
SPIHD
VDD_SPI
VDD_SPI
GND
GND GND GND
VDD33
GND GND GND
GNDGND
GND
GND
VDD33
VDD33
GND
GNDGND
VDD33
GND
GNDGND
VDD33
GND
VDD_SPI
GND
GND
GND
GND
VDD33
R13 0
C11
TBD
C13
0.1uF
C12
TBD
C4
TBD
R3 499
R11 10K
C14
1uF
R8
10K(NC)
C9
TBD
R14 0
U1 ESP32-S2
VDDA
1
LNA_IN
2
VDD3P3
3
VDD3P3
4
GPIO0
5
GPIO1
6
GPIO2
7
GPIO3
8
GPIO4
9
GPIO5
10
GPIO6
11
GPIO7
12
GPIO10
15
GPIO11
16
GPIO12
17
GPIO13
18
GPIO14
19
XTAL_32K_P
21 VDD3P3_RTC 20
XTAL_32K_N
22
DAC_1
23
DAC_2
24
GPIO19
25
GPIO20
26
VDD_SPI 30
SPICS1 29
SPIWP 32
SPICS0 33
SPIQ 35
SPID 36
SPICLK 34
GPIO33 37
GND 57
GPIO34 38
GPIO35 39
MTCK 43
GPIO46 55
VDDA 51
XTAL_N 52
XTAL_P 53
MTMS 47 MTDO 44
U0TXD 48
VDD3P3_CPU 45
CHIP_PU 56
VDDA 54
MTDI 46
GPIO8
13
GPIO9
14
VDD3P3_RTC_IO
27
GPIO21
28
SPIHD 31
GPIO36 40
GPIO37 41
GPIO38 42
U0RXD 49
GPIO45 50
L1 2.0nH
C6
10uF
R15 0
C2
100pF
Y1
40MHz (±10ppm)
XIN
1
GND
2XOUT 3
GND 4
C10
0.1uF
U2
FLASH-3V3
/CS
1
DO 2
/WP 3
GND
4
DI 5
CLK
6
/HOLD
7
VCC 8
C7
1uF
L2 TBD
ANT2
PCB ANT
1
2
C1
TBD
U3
PSRAM-3V3
VDD 8
VSS
4
CS
1
SCLK
6
SIO3
7SIO2 3
SO/SIO1 2
SI/SIO0 5
R10 0
C16
0.1uF
C3
1uF
C15
0.1uF
R16 0
R4
0
C5
0.1uF
R9
10K(NC)
C8
0.1uF
Figure 2: ESP32S2 Digital Power Supply Pins
Notice: When using VDD_SPI as the power supply pin for the external 3.3 V flash/PSRAM, the supply voltage should be
3.0 V or above, so as to meet the requirements of flash/PSRAM’s working voltage.
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2. Schematic Checklist
2.1.2 Analog Power Supply
Pin1, pin3, pin4, pin20, pin51, and pin54 are the analog power supply pins, working at 2.8 V ~3.6 V. It should be
noted that the sudden increase in current draw, when ESP32-S2 is in transmission mode, may cause a power rail
collapse. Therefore, it is highly recommended to add another 10 µF capacitor to the power trace, which can work
in conjunction with the 0.1 µF capacitor. In addition, a CLC filter circuit needs to be added near the power pins
(pin3 and pin4) so as to suppress high-frequency harmonics. The inductor’s rated current is preferably 500 mA or
above. Refer to Figure 3and place the appropriate decoupling capacitor near each analog power pin.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
The values of C11, L2 and C12
vary with the actual PCB oard.
The values of C1 and C4 vary with
the selection of the crystal.
The value of R4 varies with the actual
PCB oard.
NC: No component.
(Optional)
SPICLK
SPICS0
SPIHD
SPICS1
SPID
SPIWP
SPIQ
SPICLK
SPIHD
SPID
SPIWP
SPIQ
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO19 GPIO20 GPIO21
GPIO33
GPIO34
GPIO35
GPIO36
GPIO37
GPIO38
SPIHD
SPIWP
SPID
SPIQ
SPICS1GPIO26
SPICS0
LNA_INRF_ANT
GPIO39
GPIO40
GPIO41
GPIO42
U0RXD
GPIO45
GPIO46
CHIP_PU
U0TXD
SPICLK
GPIO18
VDD_SPI
VDD_SPI
GND
GND GND GND
VDD33
GND GND GND
GNDGND
GND
GND
VDD33
VDD33
GND
GNDGND
VDD33
GND
GNDGND
VDD33
GND
VDD_SPI
GND
GND
GND
GND
VDD33
C11
TBD
C12
TBD
C13
0.1uF
C4
TBD
R3 499
R11 10K
R8
10K(NC)
C14
1uFU1 ESP32-S2
VDDA
1
LNA_IN
2
VDD3P3
3
VDD3P3
4
GPIO0
5
GPIO1
6
GPIO2
7
GPIO3
8
GPIO4
9
GPIO5
10
GPIO6
11
GPIO7
12
GPIO10
15
GPIO11
16
GPIO12
17
GPIO13
18
GPIO14
19
XTAL_32K_P
21 VDD3P3_RTC 20
XTAL_32K_N
22
DAC_1
23
DAC_2
24
GPIO19
25
GPIO20
26
VDD_SPI 30
SPICS1 29
SPIWP 32
SPICS0 33
SPIQ 35
SPID 36
SPICLK 34
GPIO33 37
GND 57
GPIO34 38
GPIO35 39
MTCK 43
GPIO46 55
VDDA 51
XTAL_N 52
XTAL_P 53
MTMS 47 MTDO 44
U0TXD 48
VDD3P3_CPU 45
CHIP_PU 56
VDDA 54
MTDI 46
GPIO8
13
GPIO9
14
VDD3P3_RTC_IO
27
GPIO21
28
SPIHD 31
GPIO36 40
GPIO37 41
GPIO38 42
U0RXD 49
GPIO45 50
C9
TBD
C6
10uF
L1 2.0nH
U2
FLASH-3V3
/CS
1
DO 2
/WP 3
GND
4
DI 5
CLK
6
/HOLD
7
VCC 8
C10
0.1uF
Y1
40MHz (±10ppm)
XIN
1
GND
2XOUT 3
GND 4
C2
100pF
L2 TBD
C7
1uF
C1
TBD
ANT2
PCB ANT
1
2
R10 0
U3
PSRAM-3V3
VDD 8
VSS
4
CS
1
SCLK
6
SIO3
7SIO2 3
SO/SIO1 2
SI/SIO0 5
C3
1uF
C16
0.1uF
C15
0.1uF
R4
0
C8
0.1uF
R9
10K(NC)
C5
0.1uF
Figure 3: ESP32S2 Analog Power Supply Pins
Notice:
• The recommended voltage of the power supply for ESP32-S2 is 3.3 V, and its recommended output current is 500
mA or more.
• It is suggested that users add an ESD protection diode at the power entrance.
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2. Schematic Checklist
2.2 Poweron Sequence and System Reset
2.2.1 Poweron Sequence
ESP32-S2 uses a 3.3 V system power supply. The chip should be activated after the power rails have stabilized.
This is achieved by delaying the activation of CHIP_PU after the 3.3 V rails have been brought up. More details
can be found in Section Power Scheme in ESP32-S2 Datasheet.
Notice:
To ensure the power supply to the ESP32-S2 chip during power-up, it is advised to add an RC delay circuit at the
CHIP_PU pin. The recommended setting for the RC delay circuit is usually R = 10 kΩand C = 1 µF. However,
specific parameters should be adjusted based on the power-up timing of the power supply and the power-up and
reset sequence timing of the chip.
2.2.2 Reset
CHIP_PU serves as the reset pin of ESP32-S2. The reset voltage (VI L_nRST ) should meet the requirements speci-
fied in Section DC Characteristics in ESP32-S2 Datasheet. To avoid reboots caused by external interferences, route
the CHIP_PU trace as short as possible, and add a pull-up resistor as well as a capacitor to the ground whenever
possible.
Notice:
CHIP_PU pin must not be left floating.
2.3 Flash (compulsory) and SRAM (optional)
ESP32-S2 can support up to 1 GB external flash and 1 GB external SRAM. The ESP32-S2-WROVER module
uses a 4 MB SPI flash and 2 MB PSRAM, powered by VDD_SPI. Make sure to select the appropriate flash and
PSRAM according to the power voltage on VDD_SPI. We recommend reserving a serial resistor (a 0 Ωresistor
can be used initially) on the SPI communication line, to lower the driving current, reduce interference to RF, adjust
timing, and improve anti-interference ability.
The schematic for ESP32-S2 flash and SRAM is shown in Figure 4.
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2. Schematic Checklist
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
The values of C11, L2 and C12
vary with the actual PCB oard.
The values of C1 and C4 vary with
the selection of the crystal.
The value of R4 varies with the actual
PCB oard.
NC: No component.
(Optional)
SPICLK
SPICS0
SPIHD
SPICS1
SPID
SPIWP
SPIQ
SPICLK
SPIHD
SPID
SPIWP
SPIQ
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO19 GPIO20 GPIO21
GPIO33
GPIO34
GPIO35
GPIO36
GPIO37
GPIO38
SPICS1GPIO26
SPICS0
LNA_INRF_ANT
GPIO39
GPIO40
GPIO41
GPIO42
U0RXD
GPIO45
GPIO46
CHIP_PU
U0TXD
SPICLK
GPIO18
SPID
SPIQ
SPIWP
SPIHD
VDD_SPI
VDD_SPI
GND
GND GND GND
VDD33
GND GND GND
GNDGND
GND
GND
VDD33
VDD33
GND
GNDGND
VDD33
GND
GNDGND
VDD33
GND
VDD_SPI
GND
GND
GND
GND
VDD33
R13 0
C11
TBD
C13
0.1uF
C12
TBD
C4
TBD
R3 499
R11 10K
C14
1uF
R8
10K(NC)
C9
TBD
R14 0
U1 ESP32-S2
VDDA
1
LNA_IN
2
VDD3P3
3
VDD3P3
4
GPIO0
5
GPIO1
6
GPIO2
7
GPIO3
8
GPIO4
9
GPIO5
10
GPIO6
11
GPIO7
12
GPIO10
15
GPIO11
16
GPIO12
17
GPIO13
18
GPIO14
19
XTAL_32K_P
21 VDD3P3_RTC 20
XTAL_32K_N
22
DAC_1
23
DAC_2
24
GPIO19
25
GPIO20
26
VDD_SPI 30
SPICS1 29
SPIWP 32
SPICS0 33
SPIQ 35
SPID 36
SPICLK 34
GPIO33 37
GND 57
GPIO34 38
GPIO35 39
MTCK 43
GPIO46 55
VDDA 51
XTAL_N 52
XTAL_P 53
MTMS 47 MTDO 44
U0TXD 48
VDD3P3_CPU 45
CHIP_PU 56
VDDA 54
MTDI 46
GPIO8
13
GPIO9
14
VDD3P3_RTC_IO
27
GPIO21
28
SPIHD 31
GPIO36 40
GPIO37 41
GPIO38 42
U0RXD 49
GPIO45 50
L1 2.0nH
C6
10uF
R15 0
C2
100pF
Y1
40MHz (±10ppm)
XIN
1
GND
2XOUT 3
GND 4
C10
0.1uF
U2
FLASH-3V3
/CS
1
DO 2
/WP 3
GND
4
DI 5
CLK
6
/HOLD
7
VCC 8
C7
1uF
L2 TBD
ANT2
PCB ANT
1
2
C1
TBD
U3
PSRAM-3V3
VDD 8
VSS
4
CS
1
SCLK
6
SIO3
7SIO2 3
SO/SIO1 2
SI/SIO0 5
R10 0
C16
0.1uF
C3
1uF
C15
0.1uF
R16 0
R4
0
C5
0.1uF
R9
10K(NC)
C8
0.1uF
Figure 4: ESP32S2 Flash and SRAM
2.4 Crystal Oscillator
There are two clock sources for the ESP32-S2, that is, an external crystal oscillator clock source and an RTC clock
source.
2.4.1 External Clock Source (compulsory)
Currently, the ESP32-S2 firmware only supports 40 MHz crystal oscillator. The specific capacitive values of C1 and
C4 depend on further testing of, and adjustment to, the overall performance of the whole circuit. It is recommended
that users reserve a series resistor (a 0 Ωresistor can be used initially) on the XTAL_P clock trace to reduce the
drive strength of the crystal, as well as to minimize the impact of crystal harmonics on RF performance. Note that
the accuracy of the selected crystal is ±10 ppm.
Figure 5and Figure 6show the schematics for crystal and crystal oscillator in ESP32-S2.
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2. Schematic Checklist
Notice:
• If an oscillator is used, its output should be connected to XTAL_P on the chip through a DC blocking capacitor
(about 50 pF). XTAL_N can be floating. Please make sure that the oscillator output is stable and its accuracy is
within ±10 ppm. It is also recommended that the circuit design for the oscillator is compatible with the use of
crystal, in case that if there is a defect in the circuit design, users can still use the crystal.
• Defects in the craftsmanship of the crystal oscillators (for example, large frequency deviation of more than ±10 ppm,
unstable performance within operating temperature range, etc) may lead to the malfunction of ESP32-S2, resulting
in a decrease of the RF performance.
5 5
4 4
3 3
2 2
1 1
D D C C B B A A
The values of C11, L2 and C12 vary with the actual PCB oard.
The values of C1 and C4 vary with the selection of the crystal. The value of R4 varies with the actual PCB oard.
NC: No component.
(Optional)
SPICLK SPICS0 SPIHD SPICS1
SPID SPIWP SPIQ
SPICLK SPIHD
SPID SPIWP SPIQ
GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO19
GPIO20
GPIO21
GPIO33 GPIO34 GPIO35 GPIO36 GPIO37 GPIO38 SPIHD SPIWP SPID SPIQ SPICS1GPIO26 SPICS0
LAN_INRF_ANT
GPIO39 GPIO40 GPIO41 GPIO42 U0RXD GPIO45 GPIO46 CHIP_PU U0TXD SPICLK
GPIO18
VDD_SPI VDD_SPI
GND
GND GND GND
VDD33
GND GND GND
GNDGND
GND
GND
VDD33
VDD33
GND
GNDGND
VDD33
GND
GNDGND
VDD33
GND
VDD_SPI
GND GND
GND
GND
VDD33
C11 TBD
C13 0.1uF
C12
TBD
C4 TBD
R3 499
R11 10K
C14
1uF
R8
10K(NC)
C9 TBD
U1 ESP32-S2
VDDA
1
LNA_IN
2
VDD3P3
3
VDD3P3
4
GPIO0
5
GPIO1
6
GPIO2
7
GPIO3
8
GPIO4
9
GPIO5
10
GPIO6
11
GPIO7
12
GPIO10
15
GPIO11
16
GPIO12
17
GPIO13
18
GPIO14
19
XTAL_32K_P
21 VDD3P3_RTC
20
XTAL_32K_N
22
DAC_1
23
DAC_2
24
GPIO19
25
GPIO20
26
VDD_SPI 30
SPICS1 29
SPIWP 32
SPICS0 33
SPIQ 35
SPID 36
SPICLK 34
GPIO33 37
GND 57
GPIO34 38 GPIO35 39
MTCK 43
GPIO46 55
VDDA 51
XTAL_N 52
XTAL_P 53
MTMS 47
MTDO 44
U0TXD 48
VDD3P3_CPU 45
CHIP_PU 56
VDDA 54
MTDI 46
GPIO8
13
GPIO9
14
VDD3P3_RTC_IO
27
GPIO21
28
SPIHD 31
GPIO36 40 GPIO37 41 GPIO38 42
U0RXD 49
GPIO45 50
L1 2.0nH
C6 10uF
C2 100pF
Y1
40MHz (±10ppm)
XIN
1
GND
2XOUT 3
GND 4
C10 0.1uF
U2
FLASH-3V3
/CS
1
DO 2
/WP 3
GND
4
DI 5
CLK
6
/HOLD
7
VCC 8
C7
1uF
L2 TBD
ANT2
PCB ANT
1 2
C1
TBD
U3
PSRAM-3V3
VDD 8 VSS
4
CS
1
SCLK
6
SIO3
7SIO2 3
SO/SIO1 2
SI/SIO0 5
R10 0
C16 0.1uF
C3
1uF
C15
0.1uF
R4 0
C5 0.1uF
R9
10K(NC)
C8 0.1uF
Figure 5: Schematic for ESP32S2’s Crystal
XTAL_P
GND
VDD33
GND
R4 0
C1
10nF
R5 0C4 TBD
Y1
40MHz(±10ppm)
VCC
4
NC
1GND 2
OUT 3
Figure 6: Schematic for ESP32S2’s Crystal Oscillator
2.4.2 RTC (optional)
ESP32-S2 supports an external 32.768 kHz crystal or an external signal (e.g., an oscillator) to act as the RTC sleep
clock.
Figure 7shows the schematic for the external 32.768 kHz crystal.
5 5
4 4
3 3
2 2
1 1
D D C C B B A A
The values of C11, L2 and C12 vary with the actual selection of a PCB oard.
The values of C1 and C4 vary with the actual selection of a Crystal.
(Optional)
SPICLK SPICS0 SPIHD
SPID SPIWP SPIQGPIO0
GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9
GPIO33 GPIO34 GPIO35 GPIO36 GPIO37 GPIO38 SPIHD SPIWP SPID SPIQ SPICS1GPIO26 SPICS0
LAN_INRF_ANT
GPIO39 GPIO40 GPIO41 GPIO42 U0RXD GPIO45 GPIO46 CHIP_PU U0TXD SPICLK
SPICS1 SPICLK SPIHD
SPID SPIWP SPIQ
GPIO10 GPIO11 GPIO12
GPIO21
GPIO15
GPIO16
XTAL_P
GPIO15
CLK_32K
VDD_SPI
GND
GND GND GND
VDD33
GND GND GND
GNDGND
GND
GND
VDD33
VDD33
GND
GNDGND
VDD33
GND
GNDGND
VDD33
GND
VDD_SPI
GND
GND
GND
VDD33
GND
VDD_SPI
GND
VDD33
GND
GND GND
U3 PSRAM-3V3
VDD 8 VSS
4
CS
1
SCLK
6
SIO3
7SIO2 3
SO/SIO1 2
SI/SIO0 5
C11 TBD
R4 0
C12
TBD
C13 0.1uF
C17 TBD
C4 TBD
R8
10K(NC)
C1
10nF
R3 499R
R12 TBD
C14
1uF
U1 ESP32-S2
VDDA
1
LNA_IN
2
VDD3P3
3
VDD3P3
4
GPIO0
5
GPIO1
6
GPIO2
7
GPIO3
8
GPIO4
9
GPIO5
10
GPIO6
11
GPIO7
12
GPIO10
15
GPIO11
16
GPIO12
17
GPIO13
18
GPIO14
19
XTAL_32K_P
21 VDD3P3_RTC
20
XTAL_32K_N
22
DAC_1
23
DAC_2
24
GPIO19
25
GPIO20
26
VDD_SPI 30
SPICS1 29
SPIWP 32
SPICS0 33
SPIQ 35
SPID 36
SPICLK 34
GPIO33 37
GND 57
GPIO34 38 GPIO35 39
MTCK 43
GPIO46 55
VDDA 51
XTAL_N 52
XTAL_P 53
MTMS 47
MTDO 44
U0TXD 48
VDD3P3_CPU 45
CHIP_PU 56
VDDA 54
MTDI 46
GPIO8
13
GPIO9
14
VDD3P3_RTC_IO
27
GPIO21
28
SPIHD 31
GPIO36 40 GPIO37 41 GPIO38 42
U0RXD 49
GPIO45 50
C9 TBD
X1
32.768kHz
1 2
C6 10uF
L1 TBD
U2 FLASH-3V3
/CS
1
DO 2
/WP 3
GND
4
DI 5
CLK
6
/HOLD
7
VCC 8
C10 0.1uF
Y1
40MHz+/-10ppm
XIN
1
GND
2XOUT 3
GND 4
C2
100pF
R4 0
C18 TBD
L2 TBD
C7
1uF
C4 TBD
C1
TBD
ANT1
PCB ANT
1 2
C17 TBD
R10 0R
C3
1uF
C16 0.1uF
Y1
40MHz(±10ppm)
VCC
4
NC
1GND 2
OUT 3
C15
0.1uF
R9
10K(NC)
C8 0.1uF
C5 0.1uF
Figure 7: Schematic for ESP32S2’s External Crystal (RTC)
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2. Schematic Checklist
Notice:
• Please note the requirements for the 32.768 kHz crystal.
–Equivalent series resistance (ESR) ⩽70 kΩ.
–Load capacitance at both ends should be configured according to the crystal’s specification.
• The parallel resistor R12 is used for biasing the crystal circuit (5 MΩ< R12 ⩽10 MΩ). In general, users do not need
to populate R12.
• If the RTC source is not required, then pin21 (XTAL_32K_P) and pin22 (XTAL_32K_N) can be used as general
GPIOs.
Figure 8shows the schematic of the external signal.
GPIO15
CLK_32K C17 TBD
GPIO13
18
GPIO14
19
XTAL_32K_P
21 VDD3P3_RTC
20
XTAL_32K_N
22
DAC_1
23
DAC_2
24
25
Figure 8: Schematic of External Oscillator
The external signal can be input to XTAL_32K_P through a DC blocking capacitor (about 20 pF). XTAL_32K_N can
be floating. The signal should meet the following requirements:
XTAL_32K_P input Amplitude (Vpp, unit: V)
Sine wave or square wave 0.6 < Vpp < VDD
2.5 RF
The impedance matching point for the RF pin (pin2) of ESP32-S2 is (34+j5) Ω. A π-type matching network is
essential for antenna matching in the circuit design. CLC structure is recommended for the matching network.
Figure 9shows the RF matching schematic.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
The values of C11, L2 and C12
vary with the actual PCB oard.
The values of C1 and C4 vary with
the selection of the crystal.
The value of R4 varies with the actual
PCB oard.
NC: No component.
(Optional)
SPICLK
SPICS0
SPIHD
SPICS1
SPID
SPIWP
SPIQ
SPICLK
SPIHD
SPID
SPIWP
SPIQ
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO19 GPIO20 GPIO21
GPIO33
GPIO34
GPIO35
GPIO36
GPIO37
GPIO38
SPIHD
SPIWP
SPID
SPIQ
SPICS1GPIO26
SPICS0
LNA_INRF_ANT
GPIO39
GPIO40
GPIO41
GPIO42
U0RXD
GPIO45
GPIO46
CHIP_PU
U0TXD
SPICLK
GPIO18
VDD_SPI
VDD_SPI
GND
GND GND GND
VDD33
GND GND GND
GNDGND
GND
GND
VDD33
VDD33
GND
GNDGND
VDD33
GND
GNDGND
VDD33
GND
VDD_SPI
GND
GND
GND
GND
VDD33
C11
TBD
C12
TBD
C13
0.1uF
C4
TBD
R3 499
R11 10K
R8
10K(NC)
C14
1uFU1 ESP32-S2
VDDA
1
LNA_IN
2
VDD3P3
3
VDD3P3
4
GPIO0
5
GPIO1
6
GPIO2
7
GPIO3
8
GPIO4
9
GPIO5
10
GPIO6
11
GPIO7
12
GPIO10
15
GPIO11
16
GPIO12
17
GPIO13
18
GPIO14
19
XTAL_32K_P
21 VDD3P3_RTC 20
XTAL_32K_N
22
DAC_1
23
DAC_2
24
GPIO19
25
GPIO20
26
VDD_SPI 30
SPICS1 29
SPIWP 32
SPICS0 33
SPIQ 35
SPID 36
SPICLK 34
GPIO33 37
GND 57
GPIO34 38
GPIO35 39
MTCK 43
GPIO46 55
VDDA 51
XTAL_N 52
XTAL_P 53
MTMS 47 MTDO 44
U0TXD 48
VDD3P3_CPU 45
CHIP_PU 56
VDDA 54
MTDI 46
GPIO8
13
GPIO9
14
VDD3P3_RTC_IO
27
GPIO21
28
SPIHD 31
GPIO36 40
GPIO37 41
GPIO38 42
U0RXD 49
GPIO45 50
C9
TBD
C6
10uF
L1 2.0nH
U2
FLASH-3V3
/CS
1
DO 2
/WP 3
GND
4
DI 5
CLK
6
/HOLD
7
VCC 8
C10
0.1uF
Y1
40MHz (±10ppm)
XIN
1
GND
2XOUT 3
GND 4
C2
100pF
L2 TBD
C7
1uF
C1
TBD
ANT2
PCB ANT
1
2
R10 0
U3
PSRAM-3V3
VDD 8
VSS
4
CS
1
SCLK
6
SIO3
7SIO2 3
SO/SIO1 2
SI/SIO0 5
C3
1uF
C16
0.1uF
C15
0.1uF
R4
0
C8
0.1uF
R9
10K(NC)
C5
0.1uF
Figure 9: ESP32S2 RF Matching Schematic
Note:
The parameters of the components in the matching network are subject to the actual antenna and PCB layout.
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2.6 UART
Users need to connect a 499 Ωresistor to the U0TXD line in order to suppress the 80 MHz harmonics. GPIO18
works as U1RXD and is in an uncertain state when the chip is powered on, which may affect the chip’s entry into
download boot mode. To solve this issue, add an external pull-up resistor.
2.7 USB
The ESP32-S2 has a full-speed USB OTG peripheral with integrated transceivers and is compliant with the USB
1.1 specification. GPIO19 and GPIO20 can be used as D- and D + of USB respectively. It is recommended to
reserve series resistor and capacitor to the ground on each line, and place them close to the chip side.
2.8 ADC
It is recommended that users add a 0.1 µF filter capacitor to a pad when using the ADC function.
2.9 Touch Sensor
When using the touch function, it is recommended to reserve a series resistor at the chip side to reduce the coupling
noise and interference on the line, and to strengthen the ESD protection. The recommended resistance is from
470 Ωto 2 kΩ, preferably 510 Ω. The specific value also depends on the actual test results of the product.
The ESP32-S2 touch sensor adopts a waterproof design. Note that only GPIO14 (TOUCH14) can drive the shield
electrode.
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3. PCB Layout Design
3. PCB Layout Design
This chapter introduces the key points of designing ESP32-S2 PCB layout with the example of ESP32-S2 mod-
ule.
While the high level of integration makes the PCB design and layout process simple, the performance of the system
strongly depends on system design aspects. To achieve the best overall system performance, please follow the
guidelines specified in this document for circuit design and PCB layout. All the common rules associated with
good PCB design still apply and this document is not an exhaustive list of good design practices.
The ESP32-S2 PCB layout design is shown in Figure 10.
Figure 10: ESP32S2 PCB Layout
3.1 General Principles of PCB Layout
We recommend a four-layer PCB design.
• The first layer is the TOP layer for signal traces and components.
• The second layer is the GND layer without signal traces being routed so as to ensure a complete GND plane.
• The third layer is the POWER layer where a GND plane should be applied to better isolate the RF and crystal
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3. PCB Layout Design
oscillator part. It is acceptable to route signal traces on this layer, provided that there is a complete GND
plane under the RF and crystal oscillator.
• The fourth layer is the BOTTOM layer, where power traces are routed. Placing any components on this layer
is not recommended.
Below are the suggestions for a two-layer PCB design.
• The first layer is the TOP layer for traces and components.
• The second layer is the BOTTOM layer. Please do not place any components on this layer and keep traces
to a minimum. Ideally, it should be a complete GND plane.
3.2 Positioning an ESP32S2 Module on a Base Board
If users adopt module-on-board design, they should pay attention to the layout of the module on the base board.
The interference of the base board on the module’s antenna performance should be minimized.
The module should be placed as close to the edge of the base board as possible. The PCB antenna area should
be placed outside the base board whenever possible. In addition, the feed point of the antenna should be closest
to the board, as Figure 11 shows.
Base Board
1 2 3
45
✅
✅
Figure 11: ESP32S2 Module Antenna Position on Base Board
Note:
As is shown in Figure 11, the recommended position of ESP32-S2 module on the base board should be:
• Position 3, 4: Highly recommended;
• Position 1, 2, 5: Not recommended.
If the positions recommended are not feasible, please make sure that the module is not covered by any metal shell.
Besides, the antenna area of the module and the area 15 mm outside the antenna should be kept clean, (namely
no copper, routing, components on it) as shown in Figure 12.
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Base Board
15 mm
Clearance
15 mm
15 mm
Figure 12: Keepout Zone for ESP32S2 Module’s Antenna on the Base Board
If there is base board under the antenna area, it is recommended to cut it off to minimize its impact on the antenna.
When designing an end product, pay attention to the impact of enclosure on the antenna.
3.3 Power Supply
• Four-layer PCB design is recommended over two-layer design. Route the power traces on the fourth (bottom)
layer whenever possible. Vias are required for the power traces to go through the layers and get connected
to the pins on the top layer. There should be at least two vias if the main power traces need to cross layers.
The drill diameter on other power traces should be no smaller than the width of the power traces.
• The 3.3 V power traces, highlighted in yellow, are routed as shown in Figure 13. The width of the main power
traces should be at least 25 mil. The width of the power traces for pin3 and pin4 should be at least 20 mil.
The width of other power traces is preferably 10 mil.
• As shown in Figure 13, an ESD protection diode is placed close to the power port (marked in red circle). A
10 µF capacitor is required before the power trace connects the ESP32-S2 chip, to be used in conjunction
with a 0.1 µF capacitor. Then the power traces are divided into two ways from here and form a star-shape
topology, thus reducing the coupling between different power pins. Note that all decoupling capacitors
should be placed close to the power pin, and ground vias should be added adjacent to the ground pin for
the decoupling capacitors to ensure a short return path.
• The power supply for the PA is provided by pin3 and pin4. It is required to add GND isolation between this
power trace and the GPIO traces on the left, and place ground vias as much as possible.
• The ground pad at the bottom of the chip should be connected to the ground plane through at least nine
ground vias.
Note:
If you need to add a thermal pad EPAD under the chip on the bottom of the module, it is recommended to employ a
nine-grid on the EPAD, cover the gaps with ink, and place ground vias in the gaps, as shown in Figure 13. This can avoid
tin leakage when soldering the module EPAD to the substrate.
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Figure 13: ESP32S2 Power Traces in a Fourlayer PCB Design
3.4 Crystal Oscillator
Figure 14 shows the reference design of the crystal oscillator. In addition, the following should be noted:
• The crystal oscillator should be placed far from the clock pin to avoid the interference on the chip. The gap
should be at least 2.0 mm. It is good practice to add high-density ground via stitching around the clock
trace for better isolation.
• There should be no vias for the clock input and output traces, which means the traces cannot cross layers.
• The external regulating capacitor should be placed on the near left or right side of the crystal oscillator, and
at the end of the clock trace whenever possible, to make sure the ground pad of the capacitor is close to
that of the crystal oscillator.
• Do not route high-frequency digital signal traces under the crystal oscillator. It is best not to route any signal
trace under the crystal oscillator. The vias on the power traces on both sides of the crystal clock trace
should be placed as far away from the clock trace as possible, and the two sides of the clock trace should
be surrounded by grounding copper.
• As the crystal oscillator is a sensitive component, do not place any magnetic components nearby that may
cause interference, for example large inductance component, and ensure that there is a clean large-area
ground plane around the crystal oscillator.
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Figure 14: ESP32S2 Crystal Oscillator Layout
3.5 RF
In a four-layer PCB design, the RF trace is routed as shown highlighted in pink in Figure 15.
• The RF trace should have 50 Ωsingle-ended characteristic impedance. The reference plane is the second
layer. A π-type matching circuitry should be reserved on the RF trace and placed close to the chip.
• Make sure to keep the width of the RF trace consistent, and do not branch the trace. The RF trace should
be as short as possible with dense ground via stitching around it for isolation.
• The RF trace should be routed on the outer layer without vias, i.e., should not cross layers. The RF trace
should be routed at a 135° angle, or with circular arcs if trace bends are required.
• The ground plane on the adjacent layer needs to be complete. Do not route any traces under the RF trace
whenever possible.
• There should be no high-frequency signal traces routed close to the RF trace. The RF antenna should be
placed away from high-frequency transmitting devices, such as crystal oscillators, DDR, and clocks, etc.
In addition, the USB port, USB-to-UART chip, UART signal lines (including traces, vias, test points, header
pins, etc.) must be as far away from the antenna as possible. It is good practice to add ground vias around
the UART signal line.
• When doing 50 Ωsingle-ended impedance control for the RF trace, please refer to the PCB stack-up design
shown in Figure 16.
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Figure 15: ESP32S2 RF Layout in a Fourlayer PCB Design
0.33
4
4
0.4
0.4
0.8
0.8
4.39
4.43
4.39
Core
1
1
0.33
Stack up
Core
PP
L1_Top
L2_Gnd
L3_Power
PP
L4_Bottom
SM
SM
1.2
8
8
1.2
Material
Base copper
(oz)
7628 TG150 RC50%
7628 TG150 RC50%
Adjustable
Thickness
(mil)
DK
Gap (mil) Gap (mil) Width (mil) Impedance (Ohm) Thickness (mm)
12.2 12.6 12.2 - 50
Finished copper 1 oz
Finished copper 1 oz
Figure 16: ESP32S2 PCB Stackup Design
3.6 Flash and PSRAM
Place the reserved serial resistor on the SPI communication line close to the chip side. Route the SPI traces on
the inner layer (e.g., the third layer) whenever possible. Add ground vias around the clock and data traces of SPI
separately. The layout of the flash and PSRAM on ESP32-S2 is shown in Figure 17.
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Figure 17: ESP32S2 Flash and PSRAM Layout
3.7 UART
The series resistor on the U0TXD line needs to be placed as close to the chip and far from the crystal oscillator as
possible. The U0TXD and U0RXD traces on the top layer should be as short as possible. Employ vias around the
traces for isolation.
3.8 USB
Place the RC circuit reserved on the USB lines close to the chip. Route the USB traces on the inner layer (third
layer) whenever possible. Please use differential routing and make each trace the same length. Make sure there is
a complete reference ground plane. Note to surround the USB traces with ground copper.
3.9 Touch Sensor
ESP32-S2 offers up to 14 capacitive IOs that detect changes in capacitance on touch sensors due to finger contact
or proximity. The chip’s internal capacitance detection circuit features low noise and high sensitivity. It allows users
to use touch pads with smaller area to implement the touch detection function. Users can also use the touch panel
array to detect a larger area or more test points. Figure 18 depicts a typical touch sensor application.
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