WinSystems PPM-LX800-G User manual

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OPERATIONS MANUAL
PPM-LX800-G
NOTE: This manual has been designed and created for use as part of WinSystems website. Web
access is required.
WinSystems reserves the right to make changes in the circuitry
and specications in the documentation at any time without notice.
Copyright 2010 by WinSystems. All Rights Reserved.

REVISION HISTORY
P/N 400-0359-000
Date Code Rev Level ECO Number
101019 B 10-64
090609 B

Table of Contents
Visual Index – Quick Reference i
Top View i
Bottom View ii
Top View - LEDs iii
Introduction 1
Features 1
Functional Capability 3
System Processor 3
Memory 3
Interrupt Routing 3
Interrupt Status Register 3
Power and Reset Interface 4
Power Fail Reset 4
Real-Time Clock/Calendar 5
Battery Backup 5
Rotational Disk Support 5
CompactFlash 6
Serial Interface 6
Serial Connector Summary 7
Video Interface 8
Ethernet Controller 9
Status LED 9
Digital I/O 10
Audio Interface 13
Speaker 13
Beep Codes 13
Line Printer Port 14
Keyboard 14
Mouse Interface 14
USB 14
Multi-I/O Interface 15
Watchdog Timer 16
PC/104 Bus Interface 17
PC/104-Plus Bus Interface 18

BIOS Supplemental 20
BIOS Settings Storage Options 33
Serial Console Reference 35
I/O Port Map 39
Interrupt Map 40
Cables 41
Software Drivers & Examples 42
Mechanical Drawing 43
Jumper Reference 44
Specications 46
Warranty Information 47

101019 OPERATIONS MANUAL PPM-LX800-G i
Visual Index – Quick Reference
Top View
NOTE: The reference line to each component part has been drawn to Pin 1, and is also highlighted with
a square, where applicable.
J11
Multi-I/O
Connector
J10
Power
SP1
Speaker
J6
PC/104-Plus
J3
CompactFlash
Socket
J1
CompactFlash
Master/Slave;
EEPROM Access;
Battery Enable;
DIO Power
J5
PC/104
Connector
J7
PC/104
Connector
J8
External
Battery

101019 OPERATIONS MANUAL PPM-LX800-G ii
Visual Index – Quick Reference
Bottom View
NOTE: The reference line to each component part has been drawn to Pin 1, and is also highlighted with
a square, where applicable.
J103
USB
Connector
J101
Flat Panel
Connector
J104
CRT Connector
J102
Audio
Connector
J105
Flat Panel
Options
J106
Backlight
Power
J107
SODIMM
Socket
J108 IDE;
Digital I/O
Connector

101019 OPERATIONS MANUAL PPM-LX800-G iii
Visual Index – Quick Reference
Top View - LEDs
D14
IDE Activity
LED
D15
Status LED
D13
Ethernet Activity
D12
Ethernet Link
Integrity
D11
Ethernet Speed

101019 OPERATIONS MANUAL PPM-LX800-G 1
This manual is intended to provide the necessary information regarding conguration and usage
of the PPM-LX800-G board. WinSystems maintains a Technical Support Group to help answer
questions not adequately addressed in this manual. Contact Technical Support at [phone],
Monday through Friday, between 8 AM and 5 PM Central Standard Time (CST).
Processor
• AMD GeodeTM LX800
Compatible Operating Systems
• Windows XP Embedded, Linux, DOS, Windows XP, x86 RTOS
Memory
• Up to 1028 MB of 200-pin SODIMM PC2700 DDR SDRAM (Socketed)
Video
• CRT or Flat Panel operation (simultaneous operation supported)
• Up to 1920x1440 CRT resolution
• Up to 1600x1200 Flat Panel resolution
• Up to 18-bits/pixel color panel support
Ethernet
• Intel 82551ER 10/100 Mbps controller
Digital I/O
• 16-bit bidirectional TTL lines capable of event sense and interrupt generation
Serial I/O
• Four (4) serial ports (Two (2) RS-232, Two (2) RS-232/422/485)
Line Printer Port
• Bidirectional (SPP)
USB
• Two (2) USB 2.0 ports
Interrupts
• Two (2) interrupt controllers
Watchdog Timer
• Up to 255 minute reset
CompactFlash
• Types I & II supported
IDE
• One (1) Ultra DMA IDE port supports up to two (2) devices
Features
Introduction

101019 OPERATIONS MANUAL PPM-LX800-G 2
Power
• +5V required, 1.2A typical
Industrial Operating Temperature Range
• -40°C to 85°C
Form Factor
• PC/104-Plus-compliant
• 3.60” x 3.80” (90 mm x 96 mm)
Additional Features
• RoHS compliant
• PC/104 and PC/104-Plus expansion connectors
• Insyde BIOS
• Backlight power supported
• Custom splash screen on start up
• Real-time clock
• Activity status LEDs on-board
• AC97 Support
• PS/2 Keyboard Supported
• PS/2 Mouse Supported

101019 OPERATIONS MANUAL PPM-LX800-G 3
The PPM-LX800-G board is based upon a 533 MHz AMD Geode™ LX800 and the
CS5536 companion chip. These devices incorporate the CPU, 128 KB of cache,
FPU, DDR SDRAM controller, Flash/ROM controller, an integrated display controller,
audio controller, PCI controller and the RTC/CMOS RAM.
Functional Capability
System Processor
Memory
The PPM-LX800-G can support a maximum of 1 GB of RAM with the SODIMM
socket located on the back of the board at J107.
Qualied SODIMMS are available directly from WinSystems.
The RAM can be user supplied, but must meet the following criteria:
200-Pin SODIMM PC2700 DDR SDRAM with gold ngers (up to 1 GB)
WinSystems cannot guarantee the operation of systems using nonqualied
SODIMM modules.
Installation is accomplished by inserting the module into the connector at
approximately a 30 degree angle. Press rmly to fully seat the module into the
connector and then press the module downward to snap it into the retaining
clamps.
Removal is accomplished by gently pulling outward on the retaining clamps until
the module springs up to the appropriate removal angle.
Interrupt Routing
Two 82C59A-compatible interrupt controllers accept inputs from the on-board
peripherals and the PC/104 Bus connectors. The conguration of interrupt inputs
is achieved in the BIOS CMOS setup discussed in the BIOS Supplemental later in
this manual.
Interrupt Status Register
One of the unique features of the PPM-LX800-G is the Interrupt Status Register
located at 1ECH. This read-only register allows all COM channels to share
interrupts and thus frees interrupts for other peripherals. If more than one COM
port is congured in the BIOS to use the same interrupt, the Interrupt Status
Register can be read to determine which port generates an interrupt. Once a
pending interrupt is serviced, the status register should be read again to see if
another interrupt is pending before exiting the routine.
Visual
Index
Interrupt Status Register - 1ECH
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
N/A N/A N/A N/A COM4 COM3 COM2 COM1
Note: A 1 will be read for the device(s) with an interrupt pending.
WinSystems does not provide software support for implementing the
Interrupt Status Register to share interrupts. Some operating systems,
such as Windows XP and Linux, have support for sharing serial port
interrupts and examples are available. The user will need to implement
the appropriate software to share interrupts for the other devices.

101019 OPERATIONS MANUAL PPM-LX800-G 4
Power and Reset Interface
An optional reset button can be connected between pin 8 and ground. Momentary
contact between pin 8 and ground will cause the PPM-LX800-G to reset. There is also
a reset push-button supplied on the CBL-251-G-1-1.5 Multi-I/O cable.
Power is supplied to the PPM-LX800-G through the 8-pin Molex connector at J10. The
denitions for J10 are:
Power Fail Reset
A precision voltage comparator monitors the +5V status. Upon detection of an
out-of-tolerance condition, the board is reset. This action is critically important in
the event of brown-out or power fail conditions. The reset circuit also ensures that
the power is nominal before releasing reset. A reset condition occurs when VCC
drops between 4.6V and 4.75V for more than 130 ms.
Visual
Index
8 7 6 5 4 3 2 1
o o o o o o o o
RESET GND GND GND +5V +5V +12V -12V
J10

101019 OPERATIONS MANUAL PPM-LX800-G 5
Rotational Disk Support
An industry standard 16-bit IDE interface is provided to support up to two hard
disks. An IDE activity LED, D14, provides visual status during IDE data transfers.
The IDE interface is provided via connector J108, which is an 80-pin high
density connector. WinSystems offers the cable CBL-352-G-1-1.5 to simplify the
connection. The pinout for the connector and cable is listed in detail in the cable
drawing.
Visual
Index
Real-Time Clock/Calendar
A real-time clock is used as the AT-compatible clock/calendar. It supports a number of
features including periodic and alarm interrupt capabilities. In addition to the time and
date keeping functions, the system conguration is kept in CMOS RAM contained within
the clock section.
Battery Backup
An optional external battery, connected at J8, supplies the PPM-LX800-G board with
standby power for the real-time clock and CMOS setup RAM. An extended temperature
lithium battery capable of backing up the PPM-LX800-G is available from WinSystems,
part number BAT-LTC-E-36-27-1 (or BAT-LTC-E-36-16-1 if applicable). Contact your
WinSystems’ Application Engineer for additional information.
A power supervisory circuit contains the voltage sensing circuit and an internal power
switch to route the battery or standby voltage to the circuits selected for backup. The
battery automatically switches ON when VCC drops below the battery voltage and back
OFF again when VCC returns to normal.
Visual
Index
Enables Battery (default) 5-6
Disables Battery 5 6
J1
WARNING: BAT-LTC-E-36-27-1 (or BAT-LTC-E-36-16-1 if applicable)
must be connected at J8. Improper connection may result in
explosive failure. It is possible for the battery to violently explode if
installed incorrectly. Please be careful to note correct connection at
location J8.
7 5 3 1
o o o o
o o o o
8 6 4 2

101019 OPERATIONS MANUAL PPM-LX800-G 6
Four independent, asynchronous serial channels are on-board. Interface is provided
at connector J11, which is an 80-pin high-density connector. WinSystems offers the
cable CBL-251-G-1-1.5 to simplify the connection. Conguration options for RS-232,
RS-422 and RS-485 are listed on the following page.
All serial channels are congured as Data Terminal Equipment (DTE). Both the send
and receive registers of each channel have a 16-byte FIFO. All serial ports have
16C550-compatible UARTs.
Independent control of transmit, receive, line status and data set interrupts are on all
channels. Each channel is setup to provide internal diagnostics such as loopback and
echo mode on the data stream. An independent, software programmable baud rate
generator is selectable from 50 through 115.2 kbps. Individual modem handshake
control signals are supported for all channels.
RS-232 interface levels are supported on all four serial ports. The RS-232 drivers
have a charge pump to generate the plus and minus voltages so that the PPM-LX800-
G only requires +5V to operate.
All COM ports support RS-232 and can be enabled in the BIOS. COM1 and COM2
also have RS-422/RS-485 support. RS-422/485 provides separate balanced transmit
and receive signal pairs. For RS-485 multidrop lines, one signal pair can be used for
“party line” network structures.
Serial Interface
Visual
Index
Optionally, a USB FLASH drive can be connected in addition to, or instead of the
CompactFlash device. Legacy USB operation is supported by the system BIOS.
CompactFlash
The PPM-LX800-G supports solid state CompactFlash storage devices for
applications where the environment is too harsh for mechanical hard disks or
oppy drives.
NOTE: The CompactFlash is an IDE device. Use of a CompactFlash device
therefore reduces the number of available hard disks to one.
The CompactFlash socket at J3 supports modules with TrueIDE support.
WinSystems offers industrial grade CompactFlash modules that provide high
performance and extended temperature operation (-40ºC to +85ºC). An IDE
activity LED is present at D14.
When using a CompactFlash device, Master/Slave selection is made using jumper
eld J1.
7 5 3 1
o o o o
o o o o
8 6 4 2
J1
CompactFlash Master 1-2
CompactFlash Slave (default) 1 2
Visual
Index

101019 OPERATIONS MANUAL PPM-LX800-G 7
Serial Connector Summary
COM3 and COM4 Conguration Options
Please see the BIOS Supplemental for further details.
Visual
Index
RS-232 Mode
1. DCD
2. RX
3. TX
4. DTR
5. GND
6. DSR
7. RTS
8. CTS
9. RI
RS-422 Mode
1. N/A
2. TX+
3. TX-
4. N/A
5. GND
6. RX+
7. RX-
8. N/A
9. N/A
RS-485 Mode
1. N/A
2. TX/RX+
3. TX/RX-
4. N/A
5. GND
6. N/A
7. N/A
8. N/A
9. N/A
1 2 3 4 5
o o o o o
o o o o
6 7 8 9
DB9 Male
COM1 and COM2 Conguration Options
1. RS-232 Mode
2. RS-422 Mode with RTS transmitter enable
3. RS-422 Mode with auto transmitter enable
4. RS-485 Mode with RTS transmitter enable
5. RS-485 Mode with RTS transmitter enable and echo back
6. RS-485 Mode with auto transmitter enable
7. RS-485 Mode with auto transmitter enable and echo back
Modes 2, 4 and 5 require the RTS bit (MCR Bit 1) be set in order to transmit.
Mode 4 requires that RTS (MCR Bit 1) be de-asserted in order to receive.
If termination is required, then terminating resistors will need to be external
to the board. Delta termination is required if using auto terminating modes
(described above). Optional on-board terminating resistors are available in
OEM quantities. Contact your WinSystems Applications Engineer for more
assistance.

101019 OPERATIONS MANUAL PPM-LX800-G 8
Video Interface
Visual
Index
HAZARD WARNING: LCD panels can require a high voltage for the
panel backlight. This high-frequency voltage can exceed 1000 volts
and can present a shock hazard. Care should be taken when wiring
and handling the inverter output. To avoid the danger of shock and
to avoid the panel, make all connection changes with the power
removed.
The PPM-LX800-G has an integrated display controller that interfaces to both CRT
and at panel displays. The video output mode is selected in the CMOS setup.
Simultaneous at panel and CRT mode is also supported. The CRT connector is
located at J104. The direct digital at panel interface is located at J101. The mode
is selected in the BIOS. The backlight power connector is located at J106.
Contact your WinSystems’ Applications Engineer for information about available
cable kits and supported panels. This manual does not attempt to provide any
information about how to connect to specic LCDs.
J104
1 o o 2
3 o o 4
5 o o 6
7 o o 8
9 o o 10
11 o o 12
13 o o 14
RED
GREEN
BLUE
HSYNC
VSYNC
DDCDATA
DDCCLK
GND
GND
GND
GND
GND
GND
VCC
1 2 3 4 5
o o o o o
VCC ENABLE (Low) ENABLE (High) GND +12V
J106
NOTE: J105 must be jumpered to match the display panel and backlight
inverter. Incorrect jumpering can damage the panel and SBC. Extreme care
should be exercised to avoid damaging or destroying the display and/or the
SBC. More detailed information is located in the Jumper Referencesection in
the back of this manual.
1 GND
3 FPHS
5 GND
7 R1
9 R3
11 R5
13 G0
15 G2
17 G4
19 GND
21 B1
23 B3
25 B5
27 FPDE
29 SWVDD
31 S1
2 FPCLK
4 FPVS
6 R0
8 R2
10 R4
12 GND
14 G1
16 G3
18 G5
20 B0
22 B2
24 B4
26 GND
28 SWVDD
30 S0
J101
Avoid Simultaneous Jumpering of pins 1-2 and 3-4.
Misjumpering panel power could cause damage to the
board and/or the Flat Panel.
2 4 6 8
o o o o
o o o o
1 3 5 7
Panel Power 5V
3.3V (default)
1-2, 3 4
1 2, 3-4
Panel
Options
S0 Low
S0 High
5-6
5 6
S1 Low
S1 High
7-8
7 8
J105

101019 OPERATIONS MANUAL PPM-LX800-G 9
An Intel 82551ER 32-bit PCI Ethernet controller chip is used for high-speed data
transfer. It has auto-negotiation capability for speed, duplex and ow control. It
supports IEEE 802.3 10Base-T and 100Base-T in either full- or half-duplex mode at
both 10 and 100 Mbps. In full-duplex mode, it adheres to the IEEE 802.x Flow Control
Specication.
The Ethernet interface is provided at Multi-I/O connector J11, which is an 80-pin
high density connector. WinSystems offers the cable CBL-251-G-1-1.5 to simplify
the connection. The pinout for the connector and cable is listed in detail in the cable
drawing.
There are three light emitting diodes (LEDs) on the PPM-LX800-G to provide a visual
indication of the link status, network activity and network speed. The yellow Link
Integrity LED is lit when a valid connection is detected. The green Activity LED blinks on
and off when activity is detected on the wire. The red LED is on if a 100Base-T link is
detected and off if a 10Base-T link is detected.
Ethernet activity signals are also provided at connector J11 to allow optional status
LEDs to be mounted off-board. The Ethernet activity signals are active low and require
an external resistor to limit current to 12-16 mA.
Ethernet Controller
Visual
Index
D12 LED 0 (YELLOW) LINK INTEGRITY
D13 LED1 (GREEN) ACTIVITY
D11 LED2 (RED) SPEED
D15 LED3 (GREEN) STATUS
NOTE: WinSystems cannot provide technical support for direct programming of the
82551ER controller. We suggest utilizing a TCP/IP stack or Network OS that allows the use
of preexisting 82551ER drivers.
J11
Status LED
A red status LED is populated on the board at D15 which can be used for any
application specic purpose. The LED can be turned on in software by writing a 1to
I/O port 1EDH. The LED can be turned off by writing a 0 to 1EDH.
Visual
Index

101019 OPERATIONS MANUAL PPM-LX800-G 10
Digital I/O
Visual
Index
The PPM-LX800-G has 16 open collector digital I/O bits with 10K pullup with a default
base address of 120H. These 16 lines are capable of fully latched event sensing with
sense polarity being software programmable. A 50-pin connector allows for easy mating
with industry standard I/O racks. J4, shown below, is the digital I/O connector on the
CBL-352-G-1-1.5 cable.
J4
1 o o 2
3 o o 4
5 o o 6
7 o o 8
9 o o 10
11 o o 12
13 o o 14
15 o o 16
17 o o 18
19 o o 20
21 o o 22
23 o o 24
25 o o 26
27 o o 28
29 o o 30
31 o o 32
33 o o 34
35 o o 36
37 o o 38
39 o o 40
41 o o 42
43 o o 44
45 o o 46
47 o o 48
49 o o 50
NC
NC
NC
NC
NC
NC
NC
NC
Port 1 Bit 7
Port 1 Bit 6
Port 1 Bit 5
Port 1 Bit 4
Port 1 Bit 3
Port 1 Bit 2
Port 1 Bit 1
Port 1 Bit 0
Port 0 Bit 7
Port 0 Bit 6
Port 0 Bit 5
Port 0 Bit 4
Port 0 Bit 3
Port 0 Bit 2
Port 0 Bit 1
Port 0 Bit 0
+5V
NC
NC
NC
NC
NC
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Digital I/O VCC Enable
The I/O connectors can provide +5V to an I/O rack or for miscellaneous purposes by jumpering
J1. When J1 is jumpered (7-8), +5V is provided at pin 49 of J4. It is the user’s responsibility to
limit current to a safe value (less than 400 mA) to avoid damaging the CPU board.
7 5 3 1
o o o o
o o o o
8 6 4 2
J1
+5V is provided at pin 49 of J4 7-8
No Power at Pin 49 of J4 (default) 7 8

101019 OPERATIONS MANUAL PPM-LX800-G 11
WS16C48 Compatible Digital I/O
This device provides 16 lines of digital I/O. The following table summarized the registers and the
text that follows provides details on each of the internal registers.
Register Details
Port 0 through 1 I/O – Each I/O bit in each of the six ports can be individually programmed
for input or output. Writing a 0to a bit position causes the corresponding output pin to go to a
high-impedance state (pulled high by external 10 KΩ resistors). This allows it to be used as an
input. When used in the input mode, a read reects the inverted state of the I/O pin, such that
a high on the pin will read as a 0 in the register. Writing a 1to a bit position causes that output
pin to sink current (up to 12 mA), effectively pulling it low.
INT_PENDING – This read-only register reects the combined state of the INT_ID0 through
INT_ID2 registers. When any of the lower three bits are set, it indicates that an interrupt is
pending on the I/O port corresponding to the bit position(s) that are set. Reading this register
allows an Interrupt Service Routine to quickly determine if any interrupts are pending and which
I/O port has a pending interrupt.
PAGE/LOCK – This register serves two purposes. The upper two bits select the register page in
use as shown here:
Bits 5-0 allow for locking the I/O ports. A 1 written to the I/O port position will prohibit further
writes to the corresponding I/O port.
I/O Address
Offset Page 0 Page 1 Page 2 Page 3
00H Port 0 I/O Port 0 I/O Port 0 I/O Port 0 I/O
01H Port 1 I/O Port 1 I/O Port 1 I/O Port 1 I/O
02H RESERVED RESERVED RESERVED RESERVED
03H RESERVED RESERVED RESERVED RESERVED
04H RESERVED RESERVED RESERVED RESERVED
05H RESERVED RESERVED RESERVED RESERVED
06H Int_ Pending Int_ Pending Int_ Pending Int_ Pending
07H Page/Lock Page/Lock Page/Lock Page/Lock
08H N/A Pol_0 Enab_0 Int_ID0
09H N/A Pol_1 Enab_1 Int_ID1
0AH N/A Pol_2 Enab_2 Int_ID2
D7 D6 Page
0 0 Page 0
0 1 Page 1
1 0 Page 2
1 1 Page 3

101019 OPERATIONS MANUAL PPM-LX800-G 12
POL0 - POL2 – These registers are accessible when Page 1 is selected. They allow interrupt
polarity selection on a port–by–port and bit-by-bit basis. Writing a 1 to a bit position selects the
rising edge detection interrupts while writing a 0 to a bit position selects falling edge detection
interrupts.
ENAB0 - ENAB2 – These registers are accessible when Page 2 is selected. They allow for port-by-
port and bit-by-bit enabling of the edge detection interrupts. When set to a 1the edge detection
interrupt is enabled for the corresponding port and bit. When cleared to 0, the bit’s edge detection
interrupt is disabled. Note that this register can be used to individually clear a pending interrupt
by disabling and re-enabling the pending interrupt.
INT_ID0 – INT_ID2 – These registers are accessible when Page 3 is selected. They are used to
identify currently pending edge interrupts. A bit when read as a 1 indicates that an edge of the
polarity programmed into the corresponding polarity register has been recognized. Note that a
write to this register (value ignored) clears ALL of the pending interrupts in this register.