Eurotech CPU-1450 User manual

Rev. 1.0 - Feb 2006
A
n
006
5
CPU-1450: Soft Power Management

Table of Contents 2
Disclaimer
The information in this manual has been carefully checked and is believed to be accurate. Eurotech
assumes no responsibility for any infringements of patents or other rights of third parties, which may result
from its use.
Eurotech assumes no responsibility for any inaccuracies that may be contained in this document. Eurotech
makes no commitment to update or keep current the information contained in this manual.
Eurotech reserves the right to make improvements to this document and/or product at any time and without
notice.
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owners.
© 2007 Eurotech Spa
Eurotech S.p.A.
A member of the Eurotech Group
Via Fratelli Solari, 3/a
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ITALY
An0065. CPU-1450 Soft Power Management

3 Table of Contents
Conventions
The following table lists conventions used throughout this guide.
Warnings and Important Notices:
Warning:
Information to alert you to potential damage to a program, system or device or potential
personal injury
Information note:
Indicates important features or instructions to observe
An0065. CPU-1450 Soft Power Management

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Table of Contents
Conventions ................................................................................................................................................... 3
Table of Contents ............................................................................................................................................ 5
Chapter 1 The Soft Power Management.................................................................................................... 7
Chapter 2 CPU-1450 SPM block diagram architecture ............................................................................ 9
Intel 82801 ICH2 and System Power States......................................................................................... 11
System Power Planes ........................................................................................................................... 12
Power Management interface signals ................................................................................................... 12
Event Input Signals and Their Usage.................................................................................................... 13
Chapter 3 CPU-1450 Power management connections......................................................................... 15
Ethernet........................................................................................................................................................ 16
The Eurotech Ethernet Transceiver ...................................................................................................... 16
Serial 1 & Serial 2 ........................................................................................................................................ 17
Auxiliary Power Connector........................................................................................................................... 18
Electrical connections .................................................................................................................................. 19
Development Kit connections ...................................................................................................................... 20
Chapter 4 SPM Management .................................................................................................................... 21
Entering Low Power mode........................................................................................................................... 22
ATX Power Button................................................................................................................................. 22
External Power Button........................................................................................................................... 22
Software ................................................................................................................................................ 22
Wake-up events ........................................................................................................................................... 23
Serial port Ring Indicator....................................................................................................................... 23
Ethernet ................................................................................................................................................. 23
External Power Button PWRBTN#........................................................................................................ 24
Wake on RTC ........................................................................................................................................ 24
Chapter 5 Soft Power Management Registers........................................................................................ 25
Intel® 82801BA I/O Controller Hub 2 (ICH2) ............................................................................................... 26
PM1_STS Power Management 1 Status Register ................................................................................ 27
PM1_EN—Power Management 1 Enable Register .............................................................................. 28
PM1_CNT—Power Management 1 Control Register............................................................................ 29
GPE0_EN—General Purpose Event 0 Enables Register ..................................................................... 30
SuperIO National PC87364 ......................................................................................................................... 31
Super I/O Configuration D Register (SIOCFD) .....................................................................................32
Chapter 6 Software examples .................................................................................................................. 33
Wake on RTC alarm..................................................................................................................................... 34
Wake on Ring Indicator Pulse...................................................................................................................... 36
Wake on LAN (Ethernet).............................................................................................................................. 37
Chapter 7 CPU power consumption ........................................................................................................ 39
Chapter 8 Appendix................................................................................................................................... 41
Related Software.......................................................................................................................................... 43
Related Documents...................................................................................................................................... 43

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Chapter 1 The Soft Power Management
Soft Power Management (SPM) is a technique that allows users to put the CPU module into a low power
mode (therefore decreasing power consumption) while keeping the capacity to restart work as soon as
something happens.
When the CPU-1450 module is powered off with SPM, just a little part of the board remains supplied. This
part monitors the system inputs, looking for wake-up events.
The low power mode can be activated via software or via a power button, whereas can be deactivated by
either the power button or from one of a number of wake-up events (i.e. receiving packets from network line,
or an alarm at a predetermined time).
Figure 1. Power Management System

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Chapter 2 CPU-1450 SPM block diagram architecture
The CPU-1450 is a PC/104-Plus module realized with a mezzanine architecture approach and comprises of
two modules:
 Celeron Processor Module
 PIII Carrier
For better understanding of the Power Management functionality of the CPU-1450 we have shown the
following block logic architecture that focuses on the chipset that manages the power saving functions. In the
diagram the dotted lines show the previous block differences.
Consider that the Celeron Processor Module is fully ACPI compatible but the PIII Carrier has been
developed with the support for APM-based legacy power management for non-ACPI implementations. In
conclusion the complete CPU-1450 assembly is only APM-based legacy power management compliant.
The core of the CPU-1450 soft power management is based on the Intel 82801 ICH2 chipset.

CPU-1450 SPM block diagram architecture 10
PWRBTN#
Low Voltage
Intel Celeron Processor
Intel 82815
GMCH
Intel 82801
ICH2
PC133 SDRAM
On Board 256MB
PCI
LPC
National Instrument
PC87364
Super IO
+3V 3SB
+5V SB
PCI to ISA
bridge ISA
LTC1536
PWRBTN#
JPR2
Default 1-2
PS ON#
J9
Keyboard
Mouse
Parallel
Port
Serial 1
and 2
VGA
Ethernet
10/100Mb
AC97
USB
4 port
IDE
Ultra ATA
SLP_S3#
SLP_S5#
PWROK
+
RTC
PWBTOUT
+5V SB
PWRBTN #
+
Processor
Module
Celeron
Carrier PIII
+5V
+5V
+5V
3V3
3V3
Figure 2. CPU-1450 Block Diagram
The colours used in the previous diagram show the different power lines used to supply peripherals during
different power states. The chipset can easily understand the wake-up source.
A good point of start, to better understand the Power Management capabilities, is to refer directly to the
chipset datasheet; consider that the CPU-1450 architecture is developed with the support for APM-based
legacy power management for non ACPI implementations, it is not possible to refer exactly to the previous
chipsets data sheets without considering some restrictions based on the hardware choices made.
An0065. CPU-1450 Soft Power Management
The following section is intended to describe some restrictions the user needs to understand regarding the
CPU-1450.

11 CPU-1450 SPM block diagram architecture
Intel 82801 ICH2 and System Power States
Table 1 shows the power states defined for ICH2-based platforms, the state names generally match the
corresponding ACPI states, the hardware implementation of the CPU-1450 assembly does not support the
greyed areas listed in the following table:
State/Sub-states Legacy Name / Description
G0/S0/C0
Full On: Processor operating. Individual devices may be shut down to save power. The different processor
operating levels are defined by Cx states, as shown in Table 4: Transitions Rules for ICH2 Within the C0 state, the
ICH2 can throttle the STPCLK# signal to reduce power consumption.
G0/S0/C1 Auto-Halt: The processor has executed an Auto-Halt instruction and is not executing code. The processor snoops
the bus and maintains cache coherency.
G0/S0/C2
Stop-Grant: The STPCLK# signal goes active to the processor. The processor performs a Stop-Grant cycle, halts
its instruction stream, and remains in that state until the STPCLK# signal goes inactive. In the Stop-Grant state,
the processor snoops the bus and maintains cache coherency.
G1/S1 Stop-Grant: Similar to G0/S0/C2 state. The ICH2 also has the option to assert the CPUSLP# signal to further
reduce processor power consumption.
G1/S3 Suspend-To-RAM (STR): The system context is maintained in system DRAM, but power is shut off to non-critical
circuits. Memory is retained and refreshes continue. All clocks stop except RTC clock.
G1/S4
Suspend-To-Disk (STD)1: The context of the system is maintained on the disk. All power is then shut off to the
system except for the logic required to resume. Externally appears same as S5, but may have different wake
events.
G2/S5 Soft Off (SOFF): System context is not maintained. All power is shut off except for the logic required to restart. A
full boot is required when waking.
G3
Mechanical OFF (MOFF): System context not maintained. All power is shut off except for the RTC. No “Wake”
events are possible, because the system does not have any power. This state occurs if the user removes the
batteries, turns off a mechanical switch, or if the system power supply is at a level that is insufficient to power the
“waking” logic. When system power returns, transition depends on the state just prior to the entry to G3 and the
AFTERG3 bit in the GEN_PMCON3 register (D31:F0, offset A4).
Table 1. General Power States for Systems using ICH2
This table gives useful information, limited to the scope of this application note. For a more detailed
description refer to 82801 ICH2 Datasheet from Intel.
An0065. CPU-1450 Soft Power Management
1Considering that the standard O.S. management usually needs an ACPI hardware platform to manage the Suspend to
Disk functionality, also if the hardware allows the user to enter this mode, specific SW management, not provided by
Eurotech S.p.A., needs to be developed to fulfil this mode.

CPU-1450 SPM block diagram architecture 12
System Power Planes
The system has several independent power planes, as described in the following table.
Note that when a particular power plane is shut off, it should go to a 0V level.
Plane Controlled by Description
MAIN SLP_S3# signal
When SLP_S3# goes active (low), power is shut off to any circuit not required to wake the
system. Since the ACPI standard S3 state requires that the memory context be preserved,
power should be retained to the main memory. However the CPU-1450 does not support the
Suspend-to-Ram, so the main memory is shutdown together with the main plane.
The processor, main memory, devices on the PCI bus, LPC interface, downstream hub
interface and AGP will typically be shut off when the Main power plane is shut, although
there may be small subsections powered.
RESUME Always present
In this plane there are the ICH2 resume logic, Ethernet controller and others individual
subsystems used for power management. This plane is powered from +5VSB OR +3V3SB.
Please refer Error! Reference source not found. for more information.
Table 2. System power planes
Power Management interface signals
The power management may be entered or exited depending on some specific signals listed in Table 3:
Name Type Description
SLP_S3# Internal Power plane control. This signal is used to shut off power to all non-critical systems when in S3
(Suspend To RAM), S4 (Suspend to Disk) or S5 (Soft Off) states
PWRBTN# Input
The Power Button will cause SMI# or SCI to indicate a system request to go to a sleep state. If the
system is already in a sleep state, this signal will cause a wake event.
If PWRBTN# is pressed for more than 4 seconds, this will cause an unconditional transition (power
button override) to the S5 state with only the PWRBTN# available as a wake event. Override will
occur even if the system is in the S1-S4 states. This signal has an internal pull-up resistor.
RI# Input From the modem interface. This signal can be enabled as a wake event; this is preserved across
power failures.
PSON# or ATX_ON Output Power-On command to ATX Power supply. When PSON# is low the ATX power supply is turned on.
VDD Input Main power from the ATX Power supply. It can be shut off from power management controller.
+5VSB Input +5 Volts-Always from the ATX Power supply. It is never shut off unless the user turns off a
mechanical switch.
Table 3. Power management for interface signals
An0065. CPU-1450 Soft Power Management
In the rest of this document we will analyse the signals considering the related programming activities.

13 CPU-1450 SPM block diagram architecture
Event Input Signals and Their Usage
Transitions rules for ICH2:
Present State Transition Trigger Next State
G0/S0/C0
Processor halt instruction
Level 2 Read
Level 3 Read
SLP_EN bit set
Power Button Override
Mechanical Off / Power Failure
G0/S0/C1
G0/S0/C2
G0/S0/C3
G1/Sx or G2/S5state
G2/S5
G3
G0/S0/C1
Any Enabled Break Event
STPCLK# goes active
Power Button Override
Power Failure
G0/S0/C0
G0/S0/C2
G2/S5
G3
G0/S0/C2
Any Enabled Break Event
STPCLK# goes inactive and previously in C1
Power Button Override
Power Failure
G0/S0/C0
G0/S0/C1
G2/S5
G3
G0/S0/C3
(ICH2-M only)
Any Enabled Break Event
STPCLK# goes inactive and previously in C1
Power Button Override
Power Failure
G0/S0/C0
G0/S0/C1
G2/S5
G3
G1/S1,
G1/S3, or
G1/S4
Any Enabled Wake Event
Power Button Override
Power Failure
G0/S0/C0 (For ICH2-M, see note 2)
G2/S5
G3
G2/S5 Any Enabled Wake Event
Power Failure
G0/S0/C0 (For ICH2-M, see note 2)
G3
G3
Power Returns Optional to go to S0/C0 (reboot) or G2/S5 (stay off until power
button pressed or other wake event). (For ICH2 and ICH2-M,
see Note 1) (For ICH2-M, see note 2)
Table 4. Transitions Rules for ICH2
An0065. CPU-1450 Soft Power Management

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Chapter 3 CPU-1450 Power management connections
To access the Soft Power Management capabilities of the CPU-1450, specific connections need to be made;
this chapter is intended to document the connections versus the wake-up devices and to supply the CPU-
1450 in a Power Management compliant mode.
Considering that we support the following external wake-up capabilities:
 Wake-On-LAN
 Serial Ring Indicator
 Power Button
We will document the connections related to the previous functions and the power connections to supply the
CPU, we recommend following the instructions using a CPU-1450 development system to simplify the power
management testing processes.

CPU-1450 Power management connections 16
Ethernet
The CPU-1450 J12 connector is used for the Ethernet connection during the Wake on LAN events.
J12
Ethernet
Figure 3. J12Connector Layout
Table 5. J12 Connector pin out
Pin # Signal
1 +3.3VSB
2 ACTIVITY LED
3 RX+
4 RX-
5 LINK LED
6 GND
7 TX+
8 TX-
The Eurotech Ethernet Transceiver
An0065. CPU-1450 Soft Power Management
To establish an Ethernet connection an Ethernet Transceiver must be used. Eurotech supplies a Transceiver
that can be placed between the J12 of the CPU module and the RJ45 network cable.

17 CPU-1450 Power management connections
Serial 1 & Serial 2
The CPU-1450 J8 connector is used for the Parallel, Serial 1 and Serial 2 ports. In the soft power
management the Ring Indicator signal on the Serial sections can be used as a wake-up event.
The signal level applied to the RI pins should be greater than 3V because this signal is applied to a GATE of
a transistor that drives the RI pin of the ICH2. Furthermore, the high level must be applied using a current
limiting resistor. The limiting resistor should be 1-kOhm for each volt applied, limiting the current below 1mA.
Parallel
Serial1, Serial2
Figure 4. J8 Connector Layout
Serial 1
Pin # Description Pin # Description
23 DCD1 24 DSR1
25 RX1 26 RTS1
27 TX1 28 CTS1
29 DTR1 30 RI1
Serial 2
Pin # Description Pin # Description
31 GND 32 DCD2
33 DSR2 34 RX2
35 RTS2 36 TX2
37 CTS2 38 DTR2
39 RI2 40 GND
An0065. CPU-1450 Soft Power Management
Table 6. J8 Connector pin out

CPU-1450 Power management connections 18
Auxiliary Power Connector
The CPU-1450 connector J9 is a 12-Pin (6x2) 2.54mm pitch connector and is used to power the module as
an alternative to the PC/104-Plus bus, this connector also carries signals for power management
Auxiliary
Power
J9
Figure 5. J9 Connector layout
Pin # Signal Pin # Signal
1 GND 2 VDD
3 N.C. 4 +12v
5 -5V 6 -12V
7 GND 8 VDD
9 N.C. 10 PWRBTN# (3)
11 +5VSB (1) 12 PSON# (2)
(1) +5VSB: +5 Volts-Always from the ATX Power supply
(2) PSON#: Power-On command to ATX Power supply
(3) PWRBTN or Power button :If the soft power management is enabled, a low signal in this pin turns the
system on or off.
Notes:
The +5VSB (Volt Stand-By) voltage is useful for Power management applications only.
The +12VDC and -5VDC voltages are neither used nor generated by the CPU-1450
module: they are only conveyed on the PC/104-Plus bus (connector J1) and can be
used by other devices or modules that are stacked onto the CPU module.
Warning:
Improper connection of the power supply will result in serious damage to the module.
An0065. CPU-1450 Soft Power Management

19 CPU-1450 Power management connections
Electrical connections
In general if you want to supply the CPU-1450 with an ATX power supply here the connections you've to
realize:
J9 Aux PWR ATX
Pin Signal Description Pin Wire Colour
1 GND Ground 5 Black
2 VDD (+5VDC) +5V DC signal 4 Red
3 N.C. Not connected -- N.C.
4 +12VDC +12 VDC signal 10 Yellow
5 N.C. Not connected -- N.C.
6 -12VDC -12 VDC signal 12 Blue
7 GND Ground 15 Black
8 VDD (+5VDC) +5 VDC signal 6 Red
9 N.C. Not connected -- N.C.
10 PWR_BTN Power Button -- N.C.
11 +5VSB Always high (ATX only) 9 Purple
12 ATX ON ATX Power on signal 14 Green
Table 7. CPU-1450 to ATX cable connections
Note:
The +12VDC and -12VDC voltages are neither used nor generated by the CPU-1450
module: they are only conveyed on the PC/104Plus bus (connector J1) and can be used
by other devices or modules that are stacked onto the CPU module.
Warning:
Improper connection of the power supply will result in serious damage for the module.
Table 8 shows the pinout of the Standard ATX female connector with the suggested 18AWG wire colour.
Pin Signal Pin Signal
11 +3.3 VDC - Orange (22AWG) 1 +3.3 VDC - Orange
11 3.3V sense - Brown (22AWG) 1 +3.3 VDC - Orange
12 -12 VDC Blue 2 +3.3 VDC - Orange
13 Black COM 3 COM - Black
14 Green PS-ON 4 +5 VDC - Red
15 Black COM 5 COM - Black
16 Black COM 6 +5 VDC - Red
17 Black COM 7 COM - Black
18 White -5 VDC 8 POK - Gray
19 Red +5 VDC 9 +5VSB - Purple
20 Red +5 VDC 10 +12 VDC - Yellow
An0065. CPU-1450 Soft Power Management
Table 8. ATX Power Connections

CPU-1450 Power management connections 20
Development Kit connections
A good platform to experiment with the power saving capabilities is the Eurotech development kit; using this
system you can minimize the number of power connections wired in a safe way over the motherboard.
We suggest using the same reference colours listed in Table 8 with AWG18 wire.
The connections you need to realize are limited and shown in the following image:
J23 DTK-1450 J9 CPU-1450
Figure 6. DTK Power Saving Connections
In this application note we assume that you are using a development system where a CPU-1450 is installed
with the connections described on Figure 6.
Warning:
Handle the module with care, considering that the board remains supplied even when it
is not operating. Remove the mains supply from the system when you need to work on
the development kit.
An0065. CPU-1450 Soft Power Management
PWRBTN#
Pin 1 PSON#
Pin 2 GND
Pin 3 Not Connected
Pin 4 +5VSB
Pin 12 PSON#
Pin 11 +5VSB
Pin 10 PWRBTN#
Pin 7 GND