Facit 1123 User manual

Contents

Section Page

Title & Contents (this page) 1

Notes & Signal Names 2

Block Diagram 3

Timing 4

Keyboard and OP Flag 5

Control (part 1) 6

Control (part 2) 7

Registers 8

Decimal Point Register & Q Flag 9

Arithmetic 10

Display Latch & Display 11

Power Supply 12

Timing Diagram 13

IC Pinouts & Physical Layout 14

Connectors 15

Facit 1123

Calculator

Facit 1123 Calculator

Section: Title and Contents

Page: 1 Rendition: 2014 Mar 6

This schematic has been derived through the reverse

engineering of a Facit 1123 calculator.

This is not the manufacter’s schematic, nor is it

based on the manufacturer’s schematic.

Notes

♦IC numbering: IC

brc

where

b

=board,

r

=row,

c

=column. Board is 1,2 or 3 starting from the top. Row and column are counted

from top left corner of board while holding board with parts up and connector on the right. See Physical Layout page.

♦Gate symbols and signal names are presented in accordance with:

logic 0 = GND

logic 1 = Vcc

♦The symol

N

bpp

denotes a physical connector pin, where

b

=1 to 3 for the PC board connectors starting from the top, K for the

keyboard connector and R for the test/remote connector underneath the chassis, and

pp

=pin. Solid black end is the male side

of the connector. White end is the female side of the connector.

♦

connection between different sections.

connection within same section.

Arrows indicate direction of signal or energy flow.

♦The symbol denotes Vcc.

♦Capacitance in microfarads unless otherwise indicated.

♦These drawings based on unit with Serial No.: 302.500.

♦Drawn by bhilpert. See www.cs.ubc.ca/~hilpert/eec for additional information.

Change Log

♦July 1996: Initial creation.

♦31 Oct 2004: Manual control notes added. N4 and N5 renamed to NK and NR.

OP-Cycles and Manual Control of Operations

A switch can be plugged into the remote connector (NR) to provide the ability to single-step through the major state cycles of an

operation. See the Keyboard & OP page for wiring of the switch.

An OP-cycle is a full number cycle during which processing occurs and is indicated by the OP signal. Major state transitions

occur at the end of an OP-cycle. Simple user operations such as numeral entry generate a single OP-cycle without sending P0 to

0. More complex operations requiring multiple number cyclesgenerate a first OP-cycle and send P0 to 0. Multiple OP-cycles are

subsequently generated until the operation is complete, at which time P0 returns to 1.

Enabling the MANUAL switch disables the automatic generation of OP-cycles for multi-cycle operations. In this mode, once a

multi-cycle operation has been initiated, each press of the CLE key generates a single OP-cycle, so the operation can be stepped

through one OP-cycle at a time.

Signal Names

Section Signal Description

Timing Ø… Master timing.

ØMaster clock from which all timing is derived. This is the basic bit rate.

ØB… Bit timing.

ØD0…ØD15 Digit Timing. 16 digit intervals, ØD2–ØD15 are the displayed digit time periods;

Registers do not cycle during ØD0.

Keyboard K

…

various (unlatched) indications from the keyboard.

A1=Add, 0=subtract.

C1=calculation is multiply or divide, 0=add or subtract.

M1=Multiply

D1=Divide

N1=Normal mode, 0=use the Z register, also associated with the decimal point.

OP OP… Operation cycle.

Control P0 state 0 of the 2-bit P state register: 1=idle, 0=calculating.

P1 – P3 the other 3 states of the P register indicating some aspect of calculation.

R0 – R3 the 4 states of the 2-bit R state register.

S

<p><r>

shorthand for states of the P and R register: S

<p><r>

= P

<p>

• R

<r>

.

DISP 1=displaying, 0=calculating , same as P0 but with additional control from

connector N5.

CY… Outputs from control to the Y register.

CX… “the X register.

CZ… “the Z register.

CA… “select the source for the A input of arithmetic.

CB… “select the source for the B input of arithmetic.

CS… “select the arithmetic function.

CD… “the decimal point register.

CQ… “ the Q flag.

X Register X… The operand being displayed.

X1,X2,X4,X8 BCD numerals on their way to the display.

Y Register Y… The second operand.

Y

YP1

Z Register ZThe user memory.

DP Register DP… The decimal point register.

Arithmetic ASUM16 The raw digit sum from the serial adder, base 16.

ASUM10 The normalized digit sum after correcting for values between 10 and 15 inclusive.

Q Flag QThe 1-bit Q flag for catching data conditions.

Display Latch DL… Latch for numerals during the digit display interval, also used for transferring from

the DP register to the Y register.

♦A lowercase “n” in a symbol name indicates the logical NOT operation.

♦The character “ • ” in a symbol name indicates the logical AND operation.

♦The character “+” in a symbol name indicates the logical OR operation.

Algorithm Notes

♦During multiply and divide, a hex ‘F’is placed after the LSD of one of the operands. The operand is shifted up to

the upper end of the register and the F is used to indicate where arithmetic will begin during the number cycle.

♦During multiply and divide, the uppermost digit of the Y register is used as a digit counter to limit the multiply/divide

loop.

Facit 1123 Calculator

Section: Notes & Signal Names

Page: 2 Rendition: 2014 Mar 6

OP•Ø…

ASUM16

ASUM10

DPR In

DPR

DPR1, DPR2, DPR4, DPR8

DP0 – DP6

DPNE, DPGT, DP>6, DP<8

Q

CQ…

CA…, CB…, CS…

CX…

CY…

S23

X1, X2, X4, X8

X, X1, X2, X4, X8

Y4, Y8,

YP1

Y

DL1, DL2, DL4, DL8

DL1, DL2, DL4

K1, K2, K4, K8

K…

P0, R0+R1

KCLR, KP

P0

DISP

Q-bit

CZ…

Z

Z Register

(56 bits)

X Register

(60 bits)

Arithmetic

Control

14 Nixie Displays

Keyboard

43210987654321.

Y Register

(60 bits)

Decimal Point

Register

(4 bits)

(decoder)

Ø

Øp

ØB

x

bit timing

ØD

x

digit timing

Timing

OP

clock rate

selection

Display Latch

(4 bits)

VCC

logic supply

display supplies

V+26

V+70

V+180

Power Supply

P State Register

(2 bits)

R State Register

(2 bits)

Facit 1123 Calculator

Section: Block Diagram

Page: 3 Rendition: 2014 Mar 6

A flag

(1 bit)

C flag

(1 bit)

N flag

(1 bit)

M/D flag

(1 bit)

A

M

D

C

N

P0

P1

P2

P3

R0

R1

R2

R3

5

6

IC248

4

12

11

IC248

13

ØB18

ØB12

nØB1

ØB1

5

6

4

IC229

3

2

IC229

1

nØD0

Ø

ØnD0•Ø

1K

5K

2K

5K

2K

10K

50K

30K

500pF

300pF

200pF

100pF

8

9

10

5

6

4

2

3

1

20K

N130

N132

nØ

to display

IC111

2SC641

300pF

5

6

2

4

3

9

13

12

10

11

5

6

IC162

4

3

2

9

13

IC162

10

11

12

2

6

IC151

4

3

5

9

13

IC131

11

12

10

2

6

IC141

3

4

5

12

13

IC141

11

10

9

2

6

IC131

3

4

5

12

13

IC151

11

10

9

2

6

IC132

3

4

5

12

13

IC132

11

10

9

12

13

IC161

9

10

11

2

6

3

5

4

12

13

11

9

10

N110

nØD2

nØD3

nØD4

nØD5

nØD6

nØD7

nØD8

nØD9

nØD10

nØD11

nØD12

nØD13

N120

nØD14

N118

nØD15

2

6

IC161

5

4

3

N108

nØD0

n1

n2

n4

n8

1

n2

n4

n8

n1

2

n4

n8

1

2

n4

n8

n1

n2

4

n8

1

n2

4

n8

n1

2

4

n8

1

2

4

n8

n1

n2

n4

8

1

n2

n4

8

n1

2

n4

8

1

2

n4

8

n1

n2

4

8

1

n2

4

8

n1

2

4

8

1

2

4

8

9

12

4

5

3

2

1

n1

2

n2

N117

IC152

IC121

IC122

8

10

N231

N229

N218

N207

nØD1

N209

N219

N217

N318

9

5

4

IC249

13

11

8

10

12

2

3

IC249

ØB48

ØB12

ØB24

ØB18

Ø

Øp

6

13

11

Ø

ØB48

9

12

4

5

3

2

4

n4

8

n8

IC142

8

10

13

11

2

3

IC247

1

11

12

IC247

13

Øp

ØB1p

ØB1

2

3

1

4

IC237

5

6

4

IC247

11

12

13

IC229

n(ØD0•B2)

ØD0•B2

ØD0

2

3

IC248

9

8

IC248

10

ØB18

ØB48

nØB8

ØB8

9

10

IC229

N244

8

ØD1

N254

ØB12

ØB24

ØD0

DISP

N116

N353

N252

N127

N351

N344

1

6

J

K

Q

nQ

nC

J

K

Q

nQ

J

K

Q

nQ

J

K

Q

nQ

8

9

10

IC370

ØD15

1

J

K

Q

nQ

J

K

Q

nQ

6

1

42K

Facit 1123 Calculator

Section: Timing

Page: 4 Rendition: 2014 Mar 6

nC

NR44

NR45

3

×

÷

N328

N325

2.2K

10K

CE

DP

×

÷

=

–

N211

CL

N335

0

1

2

3

4

5

6

7

8

9

RC

N306

N307

N308

N309

N310

N311

N312

N313

N303

N305

N329

N333

N319

N330

N332

N321

N331

11 of

20K

12

13

IC329

11

10

9

5

6

4

IC318

8

9

10

IC318

9

IC319

11

10

12

5

IC319

4

3

2

3

1

IC318

n1

n3

n5

n7

n9

n2

n3

n6

n7

n4

n5

n6

n7

n8

n9

6

13

n0

n1

n2

n3

n4

n5

n6

n7

n8

n9

2.2K

10K

12

11

13

8

9

10

IC327

8

9

10

IC328

5

6

4

IC328

N326

N324

N322

N320

12

IC310

11

6

5

8

1

2

4

3

n6

n8

n9

n0

n2

n4

N227

N225

N223

N221

K1

K2

K4

K8

5

IC326

4

2

3

8

1

12

11

6

11

12

13

IC317

nCE

nRC

nA

nS

nCE

nKCLR

11

12

13

IC318

4

IC329

5

2

3

nA

nS

nZA

nZS

6

nKMD

N323

N327

nZR

nZC

N315

N317

nZA

nZS

nZR

KF

M

KN

nKN

DISP

11

12

13

IC328

3

2

1

IC324

13

10

12

11

IC323

C

nC

M

D

C

D

nKCLR

1

2

3

4

IC323

KF

OP•ØD0•B4p

R1

9

5

8

6

IC316

1

2

4

3

IC316

A

nS

nA

nZA

5

6

4

IC354

9

8

IC354

10

nZA

nZS

OP•ØD0•B4p

4

IC314

3

2

8

11

12

1

3

4

2

IC359

nS

nA

nCE

N

nN

2

1

IC328

R0+R1

N213

N314

1

KP

to OP

nD

nM

nD

nM

nRC

nZC

nZR

nKRC

nKZC

nKZR

OP•ØD0•B1p

5

6

9

8

10

IC325

S11•nQ

nKCLR

nD

nZS

nRC

nZC

nM

to

X Register

NK10

NK36

NK43

NK45

nP0

NK18

M+

M–

MR

MC

12

IC246

9

10

11

ØB24

ØB48

12

11

IC245

13

Øp

5

6

IC236

4

9

8

IC236

10

2

3

1

IC236

11

12

IC236

13

N249

OP

ØB1p

ØD0

5

6

4

IC232

8

6

9

5

IC237

5

6

9

8

3

2

IC253

N203

20K

IC242

12

11

13

5

2

3

IC238

4

IC238

8

10

9

8

9

10

IC239

2

3

1

5

6

4

IC239

12

11

IC239

13

OP

ØD0•B2

8

9

IC257

10

6

N246

nOP

3

5

4

IC266

M5962

6

3

5

4

IC256

M5962

ØD0•B2

N263

nØD14

OP

N215

nOP

nP

DISP

to Display Latch

Øp

ØD1

N304

DISP

to Timing (clock rate)

DISP

to Keyboard

N137

N205

1

N256

Øp

ØD0•B2

OP•ØD0•B4p

OP•ØD0•B1p

n(OP•ØD0•B2p)

nKCLR

1

6

J

K

Q

nQ

J

K

Q

nQ

N316

N366

N365

N360

N342

nP0

nOP•ØD14p

11

12

13

IC355

OP

KP

NR17

NK01

NK02

NK03

NK04

NK05

NK06

NK07

NK08

NK09

NK30

NK37

NK35

NK31

NK32

NK33

NK34

NK38

NK39

NK??

Facit 1123 Calculator

Section: Keyboard & OP Flag

Page: 5 Rendition: 2014 Mar 6

11 of

20K

nC

MANUAL

NORMAL

Controller / Monitor Unit

(see Notes page)

NR29

nMANUAL

NR27

NR10

NR01

NR02

NR03

NR04

NR05

NR06

NR07

NR08

NR09

NR30

NR37

NR35

NR33

NR34

NR31

NR32

NR38

NR39

NR??

NR36

620

BUSY

NR18

nP0

Use high efficiency

LED run at low

current (~ 3mA) to

minimise drain on

source.

NR44

Ø

NR45

nØD0

NR27

nOP

NR19

X

NR43

XØENB

NR42

ASUM16

TEST

POINTS

12

11

6

5

4

IC362

P1

Q

n(P1•Q)

(2)

4

9

8

10

6

5

4

IC317

IC313

5

6

IC317

C

KF

R0

n(C•R0•KF)

(2)

9

8

10

IC313

R2

12

11

13

IC313

R3

n(C•KF)

(3)

8

9

IC343

10

n(A•P1•nR2•nQ)

n(P1•nR2•nQ)

(4)

P1

13

12

11

10

IC353

nR2

nQ

8

9

IC324

10

A

P2

13

10

11

12

IC341

R2

Q

n(S22•Q)

(2)

CYSSØ

1

5

6

4

2

3

1

IC327

IC325

2

3

IC327

KN

R0+R1

6

5

4

IC325

C

R1+R3

n((R0+R1)•KN)

(2)

9

8

10

IC334

n(P1•nR2•nQ)

d

CXS16

N338

N237

1

2

4

3

IC335

n(C•R0•KF)

2

3

IC355

1

nKZR

e

(4)

3

6

IC358

2

4

5

n(S20•Q)

n(S33•M•Q)

n(S32•D)

f

CYSS

N336

N235

2

6

IC375

3

5

4

e

b

CXD

CDS10

n(S11•nN•nQ)

n((R0+R1)•KN)

1

IC383

11

2

3

8

4

12

5

6

n((R0+R1)•KN)

CXØn15

n(S31•Q)

n(S32•M•Q)

d

e

b

n(P1•nR2•nQ)

5

IC336

3

6

1

8

4

12

2

11

n(S32•M)

CXØFNC

n(S31•Q)

n(S33•M•nQ)

a

nØD15

n(S33•D•nQ)

12

IC376

4

11

1

8

3

5

2

6

n((R2+R3)•KN)

CXS10

n(P1•Q)

n(S13•nQ)

n(S22•nQ)

nS20

n(S11•N•nQ)

d

IC316

2

IC374

11

12

4

8

1

3

5

6

n(S30•Q)

CA15

n(S22•M•Q)

c

KN

13

11

12

10

R2+R3

nN

n(S32•M•Q)

5

IC364

2

1

6

8

3

12

11

4

n(S32•M)

CDD

n(S13•nQ)

n(S33•M•nQ)

n(S33•D•nQ)

n(S30•Q)

n(S11•N•nQ)

a

d

n(S23•M)

11

IC365

6

4

5

8

3

2

1

12

CSCC

n(S30•Q)

n(S31•nQ)

n(S33•M•Q)

n(S32•M•Q)

n(S33•D•Q)

n(S31•Q)

N340

N239

11

13

IC375

10

12

9

e

b

nKCLR

CYS16

N339

N241

N269

N368

N266

10

5

6

4

IC372

8

9

IC372

P2

R0

CQXYD

nS20

(2)

3

2

1

IC373

Q

n(S20•Q)

(4)

5

6

4

IC373

nQ

n(S20•nQ)

(2)

IC373

n(S32•M•nQ)

13

N372

12

11

13

IC325

KF

nC

n(nC•KF)

(2)

3

2

1

IC317

KN

R2+R3

n((R2+R3)•KN)

(2)

CXO1

1

5

6

4

12

11

13

IC371

IC381

2

3

IC371

P1

nQ

R0

n(S10•nQ)

8

9

10

IC381

R1

CAX

3

2

1

IC381

R2

n(S12•nQ)

(2)

6

5

4

IC381

R3

n(S13•nQ)

(4)

4

5

6

IC382

9

8

10

IC373

N

n(S11•N•nQ)

(3)

9

8

10

IC382

nN

n(S11•nN•nQ)

(3)

2

3

IC382

1

n(S22•nQ)

(2)

P2

1

4

3

2

IC341

R2

nQ

CQX

n(S20•Q)

12

13

IC315

9

10

11

n(S32•D)

n(S33•M•Q)

n(S33•D•Q)

5

6

IC343

4

CAY

5

6

4

IC355

8

9

IC355

10

n(S32•M•nQ)

n(S33•D•Q)

f

(2)

3

2

1

IC343

11

12

IC343

13

n(S31•nQ)

d

(5)

10

13

IC342

9

11

12

n(P1•Q)

n(S31•Q)

n(S20•nQ)

n(S22•nQ)

c

(2)

11

12

IC354

13

5

6

IC333

2

4

3

nKRC

n(S12•nQ)

n(S22•Q)

5

6

IC334

4

b

(4)

11

13

IC333

10

12

9

nKZC

n(nC•KF)

n(S30•nQ)

2

3

IC334

1

a

(2)

2

3

IC354

1

CBY

nS23

1

3

2

4

IC353

n(S30•Q)

n(S32•M•Q)

CXO3

CXO2

CDY

CSTC

S11•nQ

to N-bit

Facit 1123 Calculator

Section: Control (part 1)

Page: 6 Rendition: 2014 Mar 6

2

3

IC362

1

n(S32•M)

(3)

P3

13

10

11

12

IC361

R2

M

8

9

IC362

10

CQDGT

n(S31•nQ)

(3)

P3

9

8

5

6

IC361

nQ

R1

n(S32•D)

(3)

P3

1

4

3

2

IC361

R2

D

11

12

IC362

13

P3

9

5

6

8

IC351

R3

D

P3

1

4

3

2

IC351

R0

nQ

n(S30•nQ)

(3)

P3

13

10

11

12

IC351

R0

Q

n(S30•Q)

(5)

10

13

IC352

9

12

11

P3

R3

nQ

M

CQXNZ

11

12

IC382

13

n(S33•M•nQ)

(3)

4

6

IC352

5

3

2

P3

R3

Q

M

n(S33•M•Q)

(3)

12

11

IC363

13

nQ

2

3

IC363

1

Q

n(S32•M•nQ)

(3)

n(S32•M•Q)

(4)

9

8

IC363

10

nQ

5

6

IC363

4

Q

n(S33•D•nQ)

(2)

n(S33•D•Q)

(3)

CQXB1

N361

N259

4

6

IC342

3

5

2

P2

R2

M

Q

n(S22•M•Q)

(1)

P3

9

5

6

8

IC341

R1

Q

n(S31•Q)

(4)

13

11

12

IC334

n(S30•nQ)

n(S32•M•nQ)

CQY

M

12

11

13

IC371

3

1

IC313

8

9

IC371

10

P1

n(S11•N•nQ)

CQDNE

d

9

6

5

8

IC335

e

b

CBX

c

13

12

11

10

IC335

n(S20•Q)

n((R2+R3)•KN)

CBD

10

8

9

IC367

n(C•R0•KF)

n(S11•nN•nQ)

CDX

3

2

1

IC372

11

12

IC372

13

P2

R3

n(S23•M)

(1)

nS23

(2)

10

13

1

n2

IC311

12

11

13

3

2

3

2

1

11

12

13

IC332

6

IC311

9

10

8

4

5

1

nKCLR

OP•ØD0•B1p

5

6

4

9

8

10

IC332

5

6

IC331

4

2

3

IC331

1

11

12

IC331

13

8

9

IC331

10

1

n1

2

n1

n2

1

n2

n1

2

1

2

n2

IC312

12

11

13

3

2

9

8

3

2

IC322

6

IC312

9

10

8

4

5

1

6

5

4

12

11

IC322

11

12

IC321

13

2

3

IC321

1

8

9

IC321

10

5

6

IC321

4

1

n1

2

n1

n2

1

n2

n1

2

1

2

1

2

n2

nKMD

OP•ØD0•B1p

5

6

IC324

4

N302

P0

P1

P2

P3

R0

R1

R2

R3

nR2

nR1

R1+R3

R2+R3

R0+R1

3

6

IC386

4

2

5

nKCLR

n(S12•nQ)

f

3

IC384

4

1

2

8

11

12

5

6

nKZR

nS20

n(P1•nR2•nQ)

n(nC•KF)

n(S22•Q)

n(S30•nQ)

n(C•KF)

n(S31•nQ)

J

K

Q

nQ

J

K

Q

nQ

J

K

Q

nQ

J

K

Q

nQ

1

IC337

6

12

2

8

3

5

11

4

nKZR

n(C•KF)

n(S32•M)

nKCLR

n(S32•D)

n(S20•Q)

1

IC385

2

3

5

8

11

12

6

4

nKRC

nS23

n(S13•nQ)

n(S33•D)

11

IC357

12

5

6

8

1

4

3

2

nKN

nKZR

n(C•KF)

nKRC

n(S30•Q)

n(S20•nQ)

n(P1•nR2•nQ)

n(S33•M•nQ)

n(nR1•nMD•N•KF)

N202

nP0

to OP

13

11

12

IC324

nR1

N

KF

9

5

8

6

IC323

nC

4

6

IC315

5

3

2

nR1

N

nC

KF

CYDL

to X Reg

to C-bit

to KB

R0+R1 t

o KB

CS10S1

S23

to Display Latch

N369

N267

CDDn15

N265

nKZC

9

8

5

6

IC353

n(S11•nN•nQ)

N370

4

5

6

IC367

n(S13•nQ)

N345

N224

CBZ

CZØ

P Register

R Register

Note: S

pr

= P

p

• R

r

CDS16

CZS10

CAD15

Facit 1123 Calculator

Section: Control (part 2)

Page: 7 Rendition: 2014 Mar 6

NK15

CA54

nC

nKCLR

nC

NR18

NR15

3

IC281

IC282

IC283

IC284

IC285

IC286

IC287

13

9

N233

N258

X

12

IC271

6

1

13

11

4

IC271

3

2

IC272

6

1

10

8

9

5

IC272

12

13

11

4

5

3

2

10

8

9

5

6

4

IC278

8

9

IC275

10

2

3

IC278

1

N250

5

6

IC259

4

9

8

IC259

10

11

12

IC259

13

3

2

IC259

1

ØnD0•Ø

N357

B0

OP•ØD0•B4p

K1

K2

K4

K8

K

J

nQ

Q

K

J

nQ

Q

K

J

nQ

Q

K

J

nQ

Q

N257

N356

N334

N348

13

11

12

13

11

12

13

11

12

13

11

12

13

11

12

13

11

12

11

12

1

2

3

4

IC377

2

1

IC370

6

5

4

IC370

1

3

4

2

IC378

9

6

8

5

IC377

13

11

12

10

IC377

OP

X

CXD

13

10

11

12

IC380

OP

CXS16

ASUM16

9

8

6

5

IC359

OP

CXØFNC

N243

N341

11

12

IC360

13

ØD15

CXØn15

3

2

IC367

1

ØD1

10

IC386

11

12

9

CXO1

CXO2

OP

CXO3

13

CXS10

nOP

nX2

ASUM10

DPR

nX4

nX8

nX1

X1

P0

X4

nDL1

13

12

1

3

11

2

11

12

13

IC232

2

3

IC232

5

6

IC221

4

3

2

IC221

1

11

12

IC221

13

9

8

IC247

10

9

11

12

IC269

13

8

IC269

10

11

12

IC228

IC227

IC226

IC225

IC224

IC223

IC222

13

9

12

11

1

nDL2

nDL4

OP

nØD15

ØnD0•Ø

3

2

4

IC258

OP

1

2

13

IC268

5962

8

10

9

IC268

5962

6

5

4

IC268

5962

12

11

13

IC257

OP•ØD0•B4p

ASUM16

12

IC211

6

1

13

11

4

IC211

3

2

IC212

6

1

10

8

9

5

IC212

12

13

11

4

5

3

10

8

9

K

J

Q

nQ

nC

K

J

Q

nQ

nC

K

J

Q

nQ

nC

K

J

Q

nQ

nC

N251

N350

13

11

12

13

11

12

13

11

12

13

11

12

13

11

12

CYDL

CYSSØ

CYS16

CYDL

Y4

Y8

Y1

YP1

13

11

12

IC213

IC214

IC215

IC216

IC217

IC218

IC219

13

9

11

12

ASUM10

13

11

12

13

11

12

13

11

12

13

11

12

13

11

12

Z Register

13

12

11

10

IC237

OP

ØnD0•Ø

CZS10

CZØ

X8

X2

Y Register

X Register

Z

Facit 1123 Calculator

Section: X, Y & Z Registers

Page: 8 Rendition: 2014 Mar 6

13

2

3

1

5

6

4

IC277

11

12

IC277

13

8

9

IC277

10

9

IC258

5

6

8

IC258

11

12

10

N253

n(ØD0•B2)

nØD14

ØB1

N349

CYSS

Y1

YP1

Y

nC

NR43

XØENB

NR19

8

9

IC278

10

ØnD0•Ø

12

IC233

11

13

5

IC233

2

3

IC234

8

10

9

4

IC234

12

11

13

5

4

2

3

8

10

9

11

12

13

IC244

N248

11

12

13

IC278

13

1

3

2

IC235

1

12

11

IC235

13

9

8

IC235

10

N222

2

3

4

12

11

10

IC243

4

n8

n4

n8

8

9

10

IC232

2

3

1

IC244

13

1

2

3

4

12

11

10

IC242

n1

n2

4

13

1

2

4

3

8

6

12

11

10

9

5

2

n2

1

n2

1

4

3

2

5

8

9

6

2

1

n8

n1

n2

6

5

4

IC244

8

9

IC221

10

1

n1

2

n2

4

n4

n8

n1

n2

4

n8

N264

2

3

1

IC276

N204

N212

N228

N216

nDP0

N210

N272

N206

N208

N214

nDP6

nDP5

IC243

IC242

IC241

IC231

n1

nDP2

nDP1

nDP4

nDP3

5

6

IC235

2

1

4

8

9

IC244

10

N270

OP

DP<8

DP>6

DPR8

DPR4

DPR2

DPR1

to Display Latch

2

3

4

0

6

–

N367

nDP0

nDP2

nDP3

nDP4

nDP6

2

3

4

0

6

–

N363

DP>2

DP>3

DP>4

DP>6

DP>4

DP>3

DP>2

DP>6

6

J

K

Q

nQ

nC

1

J

K

Q

nQ

6

J

K

Q

nQ

1

J

K

Q

nQ

N362

nDP2

nDP3

nDP4

nDP5

nDP6

nDP0

nDP1

to

Display

decimal

points

N347

N105

N107

N109

N115

N113

N111

N103

DPNE

to Q Flag

DPGT

to Q Flag

DPR

to X Register & Arithmetic

nDP2

nDP3

nDP4

nDP5

nDP6

nDP0

nDP1

NK13

NK12

NK20

IC387

4

5

3

2

6

12

11

IC367

13

IC387

13

1

10

9

8

1

IC388

2

3

13

11

12

6

IC388

8

5

4

10

9

12

11

nØD15

X

CDDnØD15

CDX

CDY

CDS16

CDS10

CDD

Y

ASUM16

ASUM10

Facit 1123 Calculator

Section: Decimal Point Register & Q Flag

Page: 9 Rendition: 2014 Mar 6

N104

12

1

OP

13

12

10

11

8

9

10

IC245

IC231

DP>6

DP<8

3

IC246

2

4

5

6

2

13

IC266

M5962

ØB1p

N255

N355

2

6

IC273

5

4

3

N261

N364

CQXYD

IC379

9

10

13

1

8

YP1

1

2

3

IC389

IC379

3

2

4

5

6

9

8

6

5

IC378

13

10

12

11

IC378

X

CQX

CQY

OP•ØD0•B4p

nOP•ØD14p

n(OP•ØD0•B2p)

1

2

3

4

IC380

13

11

12

IC389

10

8

9

IC389

4

6

5

IC389

CQXNZ

DPNE

CQDNE

DPGT

CQDGT

Q

nQ

9

5

6

8

IC380

ØB1

CQXB1

11

IC358

12

10

9

13

11

12

IC370

X

nOP•ØD14p

ØB8

CQXB1

Y4

Y8

nX1

nX2

nX4

nX8

OP

13

nX=0

Q Flag

Decimal Point Register

nC

NR12

NR13

NR20

NR21

NR28

NR22

NR23

NK21

NK27

NK22

NK23

NK24

NK11

NK25

NK26

NR24

NR11

NR25

NR26

tens carry

IC254

11

1

N262

10

IC273

12

11

9

13

6

5

IC275

4

ØnD0•Ø

IC267

8

10

9

5

4

3

2

IC265

6

5

4

IC265

12

IC265

13

8

9

IC265

10

3

2

IC257

1

8

10

11

9

IC266

M5962

ØB8

8

9

IC254

10

6

5

4

IC245

nØB1

11

12

13

2

3

1

IC254

nØB8

6

5

4

ØB1p

12

1

13

2

IC256

M5962

8

11

10

9

IC256

M5962

6

5

IC257

4

n(ØD0•B2)

9

8

IC276

10

12

11

IC276

13

ØD1

N260

ASUM16

to X, Y & DP

Registers

6

J

K

Q

nQ

nC

2

3

1

IC245

N358

N359

IC369

4

5

2

3

6

IC369

1

13

10

9

8

3

IC368

13

2

1

11

12

4

IC368

6

5

8

10

9

12

11

ØD1

ØB1

ØD15

N352

ØD15

13

10

11

12

IC359

N343

N245

1

2

3

IC360

4

5

6

IC360

N346

N247

10

9

8

IC360

X

CAD15

CS10S1

CAX

CBY

CAY

CSCC

CSTC

CBX

CBD

CA15

nX1

ASUM10

to X, Z & DP

Registers

nX4

nX8

CSCC

nX1

1

10

9

IC264

5

4

3

2

6

IC264

10

1

13

8

12

11

IC275

13

2

3

IC275

1

13

11

12

IC255

8

9

IC255

2

3

IC255

4

5

6

IC255

1

IC274

13

10

9

8

5

6

IC276

4

Z

11

5

6

IC263

12

IC263

13

nX1

nX2

X4

nX8

3

2

IC263

4

1

N268

N354

X>4

ØnD0•Ø

IC267

13

11

12

2

3

nØB1

1

J

K

Q

X1

3

IC274

2

4

5

6

IC245-4

Normalization

Adder

Operand Adder

“6” Generator

Y

ASUM16

DPR

8

9

10

IC263

N238

N337

CBZ

NK14

5/4

Facit 1123 Calculator

Section: Arithmetic

Page: 10 Rendition: 2014 Mar 6

CA54

grounded if switch

not present

nQ

nC

NR42

NR14

nDL1

20K

8

V+a2

3K

0.1

250V

V+a

2SA429

DIGIT 14

(MSD)

n2

n4

110K

V+a2

20K

2K

2

3

1

2K

5K

1K

2K

110K

n4

n8

2

n4

n2

4

2

4

5

6

4

n8

11

12

13

8

n2

2

2K

nØ

nØD1

2SC857

0

1

2

3

4

5

6

7

8

9

.

2K

V+a

200K

V+a3

0

1

2

3

4

5

6

7

8

9

.

2K

DIGIT 1

(LSD)

1K

2SC857

70K

IC112

2SC641

2SC857

nØD15

nDL2

nDP0

nDP1

nDP2

nDP3

nDP4

nDP5

nDP6

ØB1

V+a2

Facit 1123 Calculator

Section: Display Latch & Display

Page: 11 Rendition: 2014 Mar 6

nDL4

6

5

11

12

13

N119

20K

IC111

100pF

N220

8

9

10

11

12

13

IC251

6

5

4

3

2

1

IC251

IC252

9

10

13

1

8

IC252

5

4

3

2

6

IC262

5

4

3

2

6

2

3

IC269

1

IC269

4

5

6

IC253

4

11

12

IC253

13

9

8

IC253

10

ØB1p

X1

X4

X8

S23

DISP

ØB8

8

9

10

11

12

13

IC261

OP•ØD0•B4p

N133

N234

N135

N236

N141

N242

N240

N139

IC262

9

10

13

1

8

X2

6

5

4

3

2

1

IC261

N131

N129

N230

N232

DPR1

DPR4

DPR8

DPR2

DISP

to

Y Register

DIGIT 7

Hitachi

CD81

nØD14

nØD13

nØD12

nØD11

nØD10

nØD9

nØD8

nØD7

nØD6

nØD5

nØD4

nØD3

nØD2

Facit 1123 Calculator

Section: Power Supply

Page: 12 Rendition: 2014 Mar 6

1

150V

50K

V+a2

18K?

50K

V+a3

N124

N123

N102

N101

Vcc

N144

N143

V+a

2 AMP.

117VAC

24W

POWER

black

white

5000

16V

50

2 AMP.

0.1

red

black

2 AMP.

100

25V

3.3K

56K

2K

820

500

510

2SC641

2SC826

2SD80

N201

N301

N371

N271

100

300V

yellow

+5V

+180V

+70V

+26V

10

NK28

NK29

8

9

10

IC112

5

8

6

IC243

9

Unused Gates

M5310

M5320

7

14

M5304

7

14

310

314

326

336

337

357

364

365

374

376

383

384

385

121

122

131

132

141

151

161

162

246

273

315

319

329

333

342

352

358

375

386

368

388

M5330

7

14

231

237

241

242

243

258

316

323

335

341

351

353

359

361

377

378

380

M5340

7

14

111

112

221

229

232

235

236

239

244

245

247

248

251

253

254

255

257

259

261

263

265

269

275

276

277

278

M5352

7

14

252

262

264

274

369

379

387

7

M5373

7

14

142

152

211

212

233

234

238

249

267

271

272

311

312

M5391

7

14

213

214

215

216

217

218

219

222

223

224

225

226

227

228

281

282

283

284

285

286

287

M5962

7

14

256

266

268

313

317

318

321

322

324

325

327

328

331

332

334

343

354

355

360

362

363

367

370

371

372

373

381

382

389

NR29

Øp lags Ø by

approx. 1µS

Øp

DISP: 10 KHz

nDISP: 25 KHz

ØB1

ØB8

ØB1p

with

00000987654321.

in the display.

ØD1

ØD15

ØnD0•Ø

OP•ØD0•B4p

n(OP•ØD0•B2p)

0µS

40

600

Facit 1123 Calculator

Section: Timing Diagram

Page: 13 Rendition: 2014 Mar 6

80

120

160

200

240

280

320

360

400

440

480

520

560

600

640 / 0µS

ØD

n

DISP: 40 KHz

nDISP: 100 KHz

Ø

DISP: 625 Hz

nDISP: 1563 Hz

ØD0

15

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

one full number cycle

in registers

Digit held in display latch

after ØB1p

14

–

1

2

3

4

5

6

7

8

9

10

11

12

13

14

nOP•ØD14p

X

ØD0•B2

OP•ØD0•B1p

0µS

100

1500

200

300

400

500

600

700

800

900

1000

1100

1200

1300

1400

1500

1600

nDISP:

DISP:

Clock Rates (as measured)

DISP=1 (displaying): 43KHz, 23µS

DISP=0 (calculating): 111KHz, 9µS

registers

idle

0

–

Facit 1123 Calculator

Section: IC Pinouts & Physical Layout

Page: 14 Rendition: 2014 Mar 6

Component

Side

N

b

01

Boards 2 and 3

(component side view)

b

1

c

b

2

c

b

3

c

b

4

c

b

5

c

b

6

c

b

7

c

b

8

c

br

1

br

2

br

3

br

4

br

5

br

6

br

7

br

8

br

9

br

0

Solder

Side

N

b

02

Component

Side

N144

N102 N101

Board 1

(component side view)

1r

1

1r

2

Solder

Side

N143

11

c

12

c

13

c

14

c

15

c

16

c

N

b

71 N

b

72

N

b

35 N

b

36

N

b

33 N

b

34

E

C

B

Vcc

+5V

0V

GND

M5962

Vcc

+5V

0V

GND

M5330

M5340

Vcc

+5V

0V

GND

M5320

M5310

M5373

J

K

J

nQ

Q

nQ

nC

Vcc

+5V

0V

GND

M5304

M5352

M5391

Vcc

+5V

0V

GND

Vcc

+5V

0V

GND

Vcc

+5V

0V

GND

Vcc

+5V

0V

GND

Vcc

+5V

0V

GND

D

Q

14

13

12

11

10

9

8

1

2

3

4

5

6

7

14

13

12

11

10

9

8

1

2

3

4

5

6

7

14

13

12

11

10

9

8

1

2

3

4

5

6

7

14

13

12

11

10

9

8

1

2

3

4

5

6

7

14

13

12

11

10

9

8

1

2

3

4

5

6

7

14

13

12

11

10

9

8

1

2

3

4

5

6

7

14

13

12

11

10

9

8

1

2

3

4

5

6

7

14

13

12

11

10

9

8

1

2

3

4

5

6

7

14

13

12

11

10

9

8

1

2

3

4

5

6

7

♦IC pinouts are derived from the implementation and may

not include all connections.

♦M5962s are reversed in their orientation on the board

relative to all other ICs.

N3

N2

N1

NK (keyboard)

Vcc 1 2 nP0 Vcc 1 2 nP0 Vcc 1 2 Vcc 1

key 1

17

–

30

key DP

key 8

3 4 DISP nMANUAL 3 4 nDP0 nDP0 3 4 — 2

key 2

31

key *

key 9

5 6

key 0

DISP 5 6 nDP6 nDP6 5 6 — 3

key 3

18 nP0 32

key /

key 1

7 8

key 2

nØD0 7 8 nDP5 nDP5 7 8 nØD0 4

key 4

19

–

33

key =

key 3

910

key 4

nØD1 910 nDP4 nDP4 9 10 nØD1 5

key 5

20 nDP0 34

key –

key 5

11 12

key 6

nKCLR 11 12 nDP1 nDP1 11 12 — 6

key 6

21 nDP2 35

key RC

key 7

13 14 KP nKP 13 14 nDP2 nDP2 13 14 — 7

key 7

22 nDP4 36 nKCLR

key M+

15 16 nOP nOP 15 16 nDP3 nDP3 15 16 ØB1 8

key 8

23 nDP6 37

key CE

key M–

17 18 nØD15 nØD15 17 18 ØB48 ØB48 17 18 nØD15 9

key 9

24 DP>2 38

key M+

key ÷

19 20 K8 nØD14 19 20

D Latch IC253-11

nØB8p 19 20 nØD14 10

key 0

25 DP>4 39

key M–

key DP

21 22 K4 K8 21 22 DP>4 —21 22 —11 DP>3 26 DP>6 40

key MR/C

key Z1

23 24 K2 K4 23 24 CZS10 V+a 23 24 V+a 12 DPNE 27 nDP3 41

key MC/R

lamp *

25 26 K1 K2 25 26 — — 25 26 —13 DPGT 28 Vcc 42

–

key Z2

27 28

lamp ÷

K1 27 28 DP>3 ØB8 27 28 —14

switch 5/4

43

lamp *

key RC

29 30

key =

Ø29 30 nDL2 nDL2 29 30 Ø15 CA54 29 GND 44

–

key CE

31 32

key –

Øp 31 32 DL2 DL2 31 32 Øp 16

–

45

lamp /

key *

33 34

X Reg IC378-1 X Reg IC281-11

33 34 DL1 DL1 33 34 —

nDL1 35 36 —

nKCLR 35 36 CYP CYP 35 36 nDL1 DISP 37 38 —

Z37 38 CSTC CSTC 37 38 ZnDL8 39 40 —

CYS16 39 40 CSCC CSCC 39 40 nDL8 nDL4 41 42 —

NR (remote)

XØENB 41 42 nOP•ØD14p CYS16 41 42 nDL4 GND 43 44 GND 1

key 1

17 nMANUAL 30

key DP

Arith IC359-13

43 44 ØD1 XØENB 43 44 ØD1 2

key 2

31

key *

CZS10 45 46

Arith IC360-1 Arith XOR1-b

45 46 nOP•ØD14p 3

key 3

18 nP0 32

key /

DPR In

47 48

X Reg IC370-1 Arith IC265-6

47 48

DPR In

4

key 4

19 X33

key =

Arith IC369-10

49 50 nYP1 OP•ØD0•B1p 49 50

X Reg IC272-10

5

key 5

20 nDP0 34

key –

ØB8 51 52

switch 5/4

nYP1 51 52 ØB8 6

key 6

21 nDP2 35

key RC

ØB1 53 54

Arith IC368-4 Arith IC277-13

53 54 ØB1 7

key 7

22 nDP4 36 nKCLR

Q-bit IC378-8

55 56 X

Q-bit IC246-6

55 56 OP•ØD0•B4p 8

key 8

23 nDP6 37

key CE

X1 57 58 ASUM10 X1 57 58 X9

key 9

24 DP>2 38

key M+

ASUM16 59 60 OP•ØD0•B1p CYDL 59 60 ASUM10 10

key 0

25 DP>4 39

key M–

CYDL, CA54 61 62 DPR nX=0 61 62 ASUM16 11 DP>3 26 DP>6 40

key MR/C

DPGT 63 64 nX=0 n(OP•ØD0•B2p) 63 64 DPR 12 DPNE 27 nOP 41

key MC/R

n(OP•ØD0•B2p) 65 66 OP•ØD0•B4p CZØ 65 66 CQXYD 13 DPGT 28 nDP3 42 ASUM16

DPNE 67 68 CQXYD CS10S1,S23 67 68

Arith IC263-1

14

switch 5/4

43 XØENB

CS10S1,S23 69 70 CZØ CYØYP 69 70 DP>2 15 CA54 29 GND 44 Ø

GND 71 72 CYØYP GND 71 72 DP>6 16 —45 nØD0

• Italicised expressions are connections with no signal name in the schematic.

• Bold-faced expressions are signal sources.

• See preceding page for connector orientation.

Facit 1123 Calculator

Section: Connectors

Page: 15 Rendition: 2014 Mar 6

Facit 1123 User manual

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