Fluke 9000A-Z80QT User manual

9000A-Z8OQT
INTERFACEPOD
Instruction Manual
P/ N859447
March 1989
©1989. John Fluke Mfg. Co.. Inc. FLU KE
All rights reserved. Litho in U.S.A.

WARRANTY
COVERAGE
Fluke warrants this interface pod to be free from defects in material and workmanship
under normal use and service for a period of one (1) year from the date of shipment.
This warranty extends only to the original purchaser and does not apply to any
product that has been misused, altered, or has been subjected to abnormal conditions
of operation.
Fluke’s obligations under this warranty are limited to repair or replacement of a
product that is returned to an authorized Service Center within the warranty period,
provided that we determine that the product is defective. If we determine that the
failure has been caused by misuse, alteration,or abnormal conditions of operation,or
if the warranty period has expired, we will repair the pod and bill you for reasonable
repair cost.
SERVICE
If afailure occurs, send the product, postage prepaid, to the closest Service Center
with a description of the difficulty. Repairs will be made or the product replaced, and it
will be returned, transportation prepaid. FlukeassumesNO risk for damage in transit.
DISCLAIMER
THE FOREGOING WARRANTY IS EXCLUSIVE AND IN LIEU OF ALL OTHER
WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO ANY
IMPLIEDWARRANTYOF MERCHANTABILITY,FITNESS, OR ADEQUACY FOR ANY
PARTICULAR PURPOSE OR USE. FLUKE SHALL NOT BE LIABLE FOR ANY
SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES,WHETHER IN CONTRACT,
TORT, OR OTHERWISE.
GETTING ANSWERS AND ADVICE
To enhanceyour use of this pod, Fluke will be happy to answer your questions about
its applications and use. Address all correspondence to: JOHN FLUKE MFG. CO.,
INC., P.O. BOX 09090, EVERETT, WASHINGTON, 98206, ATTN: Sales Department.
JOHN FLUKE MFG. CO., INC., PO. BOX 09090, EVERETT, WASHINGTON 98206

ZBOQT
Table of Contents
SECTION TITLE PAGE
1INTRODUCTION ................................... 1-1
1-1. PURPOSE OF INTERFACEPOD ................ 1-1
1-2, DESCRIPTIONOF INTERFACEPOD ............ 1-1
1-3. SPECIFICATIONS ............................ 1-2
2INSTALLATION ..................................... 2-1
2-1. INSTALLING THE Z80QT DATABASE
(9100 SERIES ONLY) .......................... 2-1
2-2. MAKING CONNECTIONS ...................... 2-1
2-3. POWER CONNECTIONS ....................... 2-2
3POD SIGNALS AND FUNCTIONS ...................... 3-1
3-1. INTRODUCTION ............................. 3-1
3-2. 280 SIGNALS ................................ 3-1
3-3. STATUS/CONTROL LINES AND ADDRESS
SPACE ASSIGNMENT ........................ 3—4
3—4. Introduction ................................ 3-4
3-5. Bit Assignment —Status Lines .................. 3-4
3-6. User-Writable Control Lines .................... 3—4
3-7. Bit Assignment AControl Lines ................. 3-5
3-8. Address Space Assignment ..................... 3—5
3-9. FORCING AND INTERRUPT LINES ............. 3-6
3-10. LINES ENABLED DURING MAINFRAMESETUP .3-7
3-11. NON—DETECTABLE280 SIGNALS ............... 3-7
3—12.‘ QUICK-LOOPING READ AND WRITE FUNCTIONS 3—7
3-13. Using the 9000 Series for Quick-Looping
Read and Write .............................. 3-8
34—14. Using the 9100 Series for Quick-Looping
Read and Write .............................. 3-8
3—l5. QUICK MEMORY TESTS ...................... 3-9
3-16. Quick RAM Test Description ................... 3-9
347. Quick ROM Test Description ................... 3-10
1' (vomimzed on page ii)

Z8OQT
TABLE OF CONTENTS, (continued)
SECTION TITLE PAGE
3-18. Using the 9000 Series for Quick RAM Testing ....... 3-10
3-19. Using the 9000 Series for Quick ROM Testing ....... 3—13
3—20. Using the 9100 Series for Quick RAM Testing ....... 3-15
3—21. Using the 9100 Series for Quick ROM Testing ....... 3-15
3—22. QUICK FILL AND VERIFY ..................... 3-16
3—23. Using the 9000 Series for Quick Fill and Verify ...... 3-16
3-24. Using the 9100 Series for Quick Fill and Verify ...... 3-17
3-25. MARGINALOUT PROBLEMS .................. 3-19
3—26 Introduction ................................ 3—19
3-27. UUT Operating Speed and Memory Access ........ 3-19
3—28. UUT Noise Levels ............................ 3—19
3—29. Bus Loading ................................ 3-19
3-30. Clock Loading .............................. 3-20
3-31. POD DRIVE CAPABILITY ..................... 3-20
3-32. POWER FAILURE DETECTIONLIMITS ......... 3—20
THEORY OF OPERATION ............................ 4-1
4-]. INTRODUCTION ............................. 4-1
4-2. GENERALPOD OPERATION ................... 4-1
4—3. Processor Section ............................ 4-1
4-3. Processor Section ............................ 4-1
4-4. UUT Interface Section ........................ 4-4
4-5. Timing Section .............................. 4-4
4-6. UUT Power Sensing .......................... 4-5
4-7. DETAILED BLOCK DIAGRAM DESCRIPTION . . . . 4-5
4—8. ProcessorSection ............................ 4-5
4—9. UUT Interface Section 7General ................ 4—8
4-10. UUT Interface Section 7Data Lines ............. 4—9
4-11. UUT Interface Section —Address Lines ........... 4-12
4-12. UUT Interface Section 7Status and Control Lines ..4—12
4-13. Timing Section .............................. 4-13
MAINTENANCE .................................... 5—1
5—1. INTRODUCTION ............................. 5—l
5—2. SELF TEST .................................. 5-1
5-3. REPAIR PRECAUTIONS ...................... 5—4
5—4. TROUBLESHOOTING ......................... 5-4
5-5. Introduction ................................ 5—4
5—6. Pod Defective or Inoperative? ................... 5—5
5—7. Selecting aUUT for Pod Testing ................. 5-7
5—8. Troubleshooting aDefective Pod ................. 5—8
5-13. Troubleshooting an Inoperative Pod .............. 5-14
5-l4. DISASSEMBLY .............................. 5-19
ii (continued on page iii)

Z8OQT
TABLE OF CONTENTS,(continued)
SECTION TITLE PAGE
6LIST OF REPLACEABLE PARTS ....................... 6-1
6-1. INTRODUCTION ............................. 6-1
6-2. HOW TO OBTAIN PARTS ...................... 6—1
7SCHEMATIC DIAGRAMS ............................. 7-1
APPENDIX A
USING THE Z8OQT POD FROM TL/l PROGRAMS A-1
iii /iv

ZSOQT
List of Tables
TABLE TITLE PAGE
1.[_ Z80QT Interface Pod Specifications ....................... 1-4
3-l. Z80 Signals ............................................ 3-1
3-2_ Status and Control Lines Bit Assignments .................. 3-6
3-3. Quick—LoopingRead and Write Test Addresses .............. 3-8
3-4, Quick RAM Test Addresses and Status Codes ............... 3-12
3-5. Quick ROM Test Addresses and Status Codes ............... 3-14
3-6, Quick Fill and Verify Addresses and Status Code ............ 3-18
5-l. Self Test Failure Codes ................................... 5-3
5-2. Required Test Equipment ................................ 5-5
5-3. Recreating Self Test Routines .......................... 5-9
5-4. ZSOQT Pod‘Memory and 1/ O Addresses ................... 5-l7
5—5l ZSOQT Interface Pod Quick ROM Checksum ............. 5—17

Z8OQT
List of Illustrations
FIGURE
1—1.
2—1.
2-2.
2-3.
3-1.
4—1.
c2.
4—3.
44.
5—1.
5-2.
5-3.
TITLE PAGE
Relationship of Interface Pod ............................. 1-3
Connection of Interface Pod to 9000 Series ................ 2-3
Connection of Interface Pod to 9100 Series ................ 2-3
Connection of Interface Pod to UUT ....................... 2-4
280 Pin Assignments ..................................... 3-3
General Block Diagram .................................. 4-2
Detailed Block Diagram .................................. 4-6
HandshakingSignals ..................................... 4-10
UUT ON Signal and Latch Times ......................... 4-11
Interface PCB, Non—Component Side ...................... 5-6
TroubleshootingaDefective Pod .......................... 5-”
Troubleshootingan Inoperative Pod ....................... 5—16
vi

ZBOQT
Section 1
Introduction
1-1. PURPOSE OF INTERFACE POD
The 9000A-280QT Interface Pod (hereafter referred to as the pod) interfaces
any 9000 Series or 9100 Series tester (hereafter referred to as the mainframe) to a
piece of equipment that uses aZ80 microprocessor.
The 9000 Series Digital Troubleshooters and 9100 Series Digital Test Systems
are designed to test and service printed circuit boards,instruments,and systems
that use bus-oriented microprocessors. The interface pod adapts the general
purpose architecture of the mainframe to aspecific microprocessoror micro-
processor family. The interface pod adapts the mainframe to microprocessor-
specific functions such as pin layout, status/control functions, interrupt
handling, timing, size of memory space, and size of I/ 0space.
AppendixAcontains informationaboutusing this pod with 9100 Series Digital
Test Systems in TL/l programs.
1-2. DESCRIPTION OF INTERFACE POD
The pod consists of apair of printed circuit board assemblies mountedin asmall
break-resistantcase. Ashielded 24-conductor cable connects the printed circuit
boards to the mainframe; aribbon cable and connector provide connection to
the unit under test, hereafter referred to as the UUT.
Figure 1—1 shows the relationship of the pod to the mainframe and to the UUT.
Connection from the pod to the mainframe is via afront-mounted 25—pin
connector. Connection to the UUT is made by plugging the ribbon cable plug
directly into the microprocessor socket. The UUT microprocessorsocket gives
the mainframe direct access to all system components which normally communi-
cate with the microprocessor.
1-1

ZBOQT
The pod contains a280 microprocessorand supportinghardware and control
software required to do the following:
Perform handshakingwith the mainframe
Receive and execute commands from the mainframe
Report UUT status to the mainframe
Emulate the UUT microprocessor
The pod is powered by the mainframe, but is clocked by the UUT clock signal.
Using the UUT clock signal allows the mainframe and pod to operate at the
designed operating speed of the UUT.
Logic level detection circuits are provided on each line to the UUT. These
circuits allow detection of bus shorts, stuck-high or stuck-low conditions, and
any bus drive conflict (two or more drivers attempting to drive the same bus
line).
Over-voltage protection circuits are also provided on each line to the UUT.
These circuits guard against pod damage which could result from:
OIncorrectly inserting the ribbon cable plug in the UUT microprocessor
socket.
OUUT faults that place potentially damaging voltages on the UUT
microprocessorsocket.
The over-voltage protection circuits guard against voltages of+12 to -7V on any
one pin. Multiple faults, especially of long duration, may cause pod damage.
Apower level sensing circuit constantly monitors the voltage level of the UUT
power supply (+5V). If UUT power rises above or drops below an acceptable
level, the pod notifies the mainframe of the power fail condition.
A self test socket provided on the pod enables the mainframe to check pod
operation. The self test socket is a 40-pin zero-insertion force type connector.
The ribbon cable plug must be connected to the self test socket during self test
operation. The ribbon cable plug should also be inserted into this socket when
the pod is not in use to provide protection for the plug.
1-3. SPECIFICATIONS
Specifications for the 9000A-Z80QT Interface Pod are listed in Table 1-1.
1-2