Fluke 9000A-Z80QT User manual

9000A-Z8OQT
INTERFACEPOD
Instruction Manual
P/ N859447
March 1989
©1989. John Fluke Mfg. Co.. Inc. FLU KE
All rights reserved. Litho in U.S.A.

WARRANTY
COVERAGE
Fluke warrants this interface pod to be free from defects in material and workmanship
under normal use and service for a period of one (1) year from the date of shipment.
This warranty extends only to the original purchaser and does not apply to any
product that has been misused, altered, or has been subjected to abnormal conditions
of operation.
Fluke’s obligations under this warranty are limited to repair or replacement of a
product that is returned to an authorized Service Center within the warranty period,
provided that we determine that the product is defective. If we determine that the
failure has been caused by misuse, alteration,or abnormal conditions of operation,or
if the warranty period has expired, we will repair the pod and bill you for reasonable
repair cost.
SERVICE
If afailure occurs, send the product, postage prepaid, to the closest Service Center
with a description of the difficulty. Repairs will be made or the product replaced, and it
will be returned, transportation prepaid. FlukeassumesNO risk for damage in transit.
DISCLAIMER
THE FOREGOING WARRANTY IS EXCLUSIVE AND IN LIEU OF ALL OTHER
WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO ANY
IMPLIEDWARRANTYOF MERCHANTABILITY,FITNESS, OR ADEQUACY FOR ANY
PARTICULAR PURPOSE OR USE. FLUKE SHALL NOT BE LIABLE FOR ANY
SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES,WHETHER IN CONTRACT,
TORT, OR OTHERWISE.
GETTING ANSWERS AND ADVICE
To enhanceyour use of this pod, Fluke will be happy to answer your questions about
its applications and use. Address all correspondence to: JOHN FLUKE MFG. CO.,
INC., P.O. BOX 09090, EVERETT, WASHINGTON, 98206, ATTN: Sales Department.
JOHN FLUKE MFG. CO., INC., PO. BOX 09090, EVERETT, WASHINGTON 98206

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Table of Contents
SECTION TITLE PAGE
1INTRODUCTION ................................... 1-1
1-1. PURPOSE OF INTERFACEPOD ................ 1-1
1-2, DESCRIPTIONOF INTERFACEPOD ............ 1-1
1-3. SPECIFICATIONS ............................ 1-2
2INSTALLATION ..................................... 2-1
2-1. INSTALLING THE Z80QT DATABASE
(9100 SERIES ONLY) .......................... 2-1
2-2. MAKING CONNECTIONS ...................... 2-1
2-3. POWER CONNECTIONS ....................... 2-2
3POD SIGNALS AND FUNCTIONS ...................... 3-1
3-1. INTRODUCTION ............................. 3-1
3-2. 280 SIGNALS ................................ 3-1
3-3. STATUS/CONTROL LINES AND ADDRESS
SPACE ASSIGNMENT ........................ 3—4
3—4. Introduction ................................ 3-4
3-5. Bit Assignment —Status Lines .................. 3-4
3-6. User-Writable Control Lines .................... 3—4
3-7. Bit Assignment AControl Lines ................. 3-5
3-8. Address Space Assignment ..................... 3—5
3-9. FORCING AND INTERRUPT LINES ............. 3-6
3-10. LINES ENABLED DURING MAINFRAMESETUP .3-7
3-11. NON—DETECTABLE280 SIGNALS ............... 3-7
3—12.‘ QUICK-LOOPING READ AND WRITE FUNCTIONS 3—7
3-13. Using the 9000 Series for Quick-Looping
Read and Write .............................. 3-8
34—14. Using the 9100 Series for Quick-Looping
Read and Write .............................. 3-8
3—l5. QUICK MEMORY TESTS ...................... 3-9
3-16. Quick RAM Test Description ................... 3-9
347. Quick ROM Test Description ................... 3-10
1' (vomimzed on page ii)

Z8OQT
TABLE OF CONTENTS, (continued)
SECTION TITLE PAGE
3-18. Using the 9000 Series for Quick RAM Testing ....... 3-10
3-19. Using the 9000 Series for Quick ROM Testing ....... 3—13
3—20. Using the 9100 Series for Quick RAM Testing ....... 3-15
3—21. Using the 9100 Series for Quick ROM Testing ....... 3-15
3—22. QUICK FILL AND VERIFY ..................... 3-16
3—23. Using the 9000 Series for Quick Fill and Verify ...... 3-16
3-24. Using the 9100 Series for Quick Fill and Verify ...... 3-17
3-25. MARGINALOUT PROBLEMS .................. 3-19
3—26 Introduction ................................ 3—19
3-27. UUT Operating Speed and Memory Access ........ 3-19
3—28. UUT Noise Levels ............................ 3—19
3—29. Bus Loading ................................ 3-19
3-30. Clock Loading .............................. 3-20
3-31. POD DRIVE CAPABILITY ..................... 3-20
3-32. POWER FAILURE DETECTIONLIMITS ......... 3—20
THEORY OF OPERATION ............................ 4-1
4-]. INTRODUCTION ............................. 4-1
4-2. GENERALPOD OPERATION ................... 4-1
4—3. Processor Section ............................ 4-1
4-3. Processor Section ............................ 4-1
4-4. UUT Interface Section ........................ 4-4
4-5. Timing Section .............................. 4-4
4-6. UUT Power Sensing .......................... 4-5
4-7. DETAILED BLOCK DIAGRAM DESCRIPTION . . . . 4-5
4—8. ProcessorSection ............................ 4-5
4—9. UUT Interface Section 7General ................ 4—8
4-10. UUT Interface Section 7Data Lines ............. 4—9
4-11. UUT Interface Section —Address Lines ........... 4-12
4-12. UUT Interface Section 7Status and Control Lines ..4—12
4-13. Timing Section .............................. 4-13
MAINTENANCE .................................... 5—1
5—1. INTRODUCTION ............................. 5—l
5—2. SELF TEST .................................. 5-1
5-3. REPAIR PRECAUTIONS ...................... 5—4
5—4. TROUBLESHOOTING ......................... 5-4
5-5. Introduction ................................ 5—4
5—6. Pod Defective or Inoperative? ................... 5—5
5—7. Selecting aUUT for Pod Testing ................. 5-7
5—8. Troubleshooting aDefective Pod ................. 5—8
5-13. Troubleshooting an Inoperative Pod .............. 5-14
5-l4. DISASSEMBLY .............................. 5-19
ii (continued on page iii)

Z8OQT
TABLE OF CONTENTS,(continued)
SECTION TITLE PAGE
6LIST OF REPLACEABLE PARTS ....................... 6-1
6-1. INTRODUCTION ............................. 6-1
6-2. HOW TO OBTAIN PARTS ...................... 6—1
7SCHEMATIC DIAGRAMS ............................. 7-1
APPENDIX A
USING THE Z8OQT POD FROM TL/l PROGRAMS A-1
iii /iv

ZSOQT
List of Tables
TABLE TITLE PAGE
1.[_ Z80QT Interface Pod Specifications ....................... 1-4
3-l. Z80 Signals ............................................ 3-1
3-2_ Status and Control Lines Bit Assignments .................. 3-6
3-3. Quick—LoopingRead and Write Test Addresses .............. 3-8
3-4, Quick RAM Test Addresses and Status Codes ............... 3-12
3-5. Quick ROM Test Addresses and Status Codes ............... 3-14
3-6, Quick Fill and Verify Addresses and Status Code ............ 3-18
5-l. Self Test Failure Codes ................................... 5-3
5-2. Required Test Equipment ................................ 5-5
5-3. Recreating Self Test Routines .......................... 5-9
5-4. ZSOQT Pod‘Memory and 1/ O Addresses ................... 5-l7
5—5l ZSOQT Interface Pod Quick ROM Checksum ............. 5—17

Z8OQT
List of Illustrations
FIGURE
1—1.
2—1.
2-2.
2-3.
3-1.
4—1.
c2.
4—3.
44.
5—1.
5-2.
5-3.
TITLE PAGE
Relationship of Interface Pod ............................. 1-3
Connection of Interface Pod to 9000 Series ................ 2-3
Connection of Interface Pod to 9100 Series ................ 2-3
Connection of Interface Pod to UUT ....................... 2-4
280 Pin Assignments ..................................... 3-3
General Block Diagram .................................. 4-2
Detailed Block Diagram .................................. 4-6
HandshakingSignals ..................................... 4-10
UUT ON Signal and Latch Times ......................... 4-11
Interface PCB, Non—Component Side ...................... 5-6
TroubleshootingaDefective Pod .......................... 5-”
Troubleshootingan Inoperative Pod ....................... 5—16
vi

ZBOQT
Section 1
Introduction
1-1. PURPOSE OF INTERFACE POD
The 9000A-280QT Interface Pod (hereafter referred to as the pod) interfaces
any 9000 Series or 9100 Series tester (hereafter referred to as the mainframe) to a
piece of equipment that uses aZ80 microprocessor.
The 9000 Series Digital Troubleshooters and 9100 Series Digital Test Systems
are designed to test and service printed circuit boards,instruments,and systems
that use bus-oriented microprocessors. The interface pod adapts the general
purpose architecture of the mainframe to aspecific microprocessoror micro-
processor family. The interface pod adapts the mainframe to microprocessor-
specific functions such as pin layout, status/control functions, interrupt
handling, timing, size of memory space, and size of I/ 0space.
AppendixAcontains informationaboutusing this pod with 9100 Series Digital
Test Systems in TL/l programs.
1-2. DESCRIPTION OF INTERFACE POD
The pod consists of apair of printed circuit board assemblies mountedin asmall
break-resistantcase. Ashielded 24-conductor cable connects the printed circuit
boards to the mainframe; aribbon cable and connector provide connection to
the unit under test, hereafter referred to as the UUT.
Figure 1—1 shows the relationship of the pod to the mainframe and to the UUT.
Connection from the pod to the mainframe is via afront-mounted 25—pin
connector. Connection to the UUT is made by plugging the ribbon cable plug
directly into the microprocessor socket. The UUT microprocessorsocket gives
the mainframe direct access to all system components which normally communi-
cate with the microprocessor.
1-1

ZBOQT
The pod contains a280 microprocessorand supportinghardware and control
software required to do the following:
Perform handshakingwith the mainframe
Receive and execute commands from the mainframe
Report UUT status to the mainframe
Emulate the UUT microprocessor
The pod is powered by the mainframe, but is clocked by the UUT clock signal.
Using the UUT clock signal allows the mainframe and pod to operate at the
designed operating speed of the UUT.
Logic level detection circuits are provided on each line to the UUT. These
circuits allow detection of bus shorts, stuck-high or stuck-low conditions, and
any bus drive conflict (two or more drivers attempting to drive the same bus
line).
Over-voltage protection circuits are also provided on each line to the UUT.
These circuits guard against pod damage which could result from:
OIncorrectly inserting the ribbon cable plug in the UUT microprocessor
socket.
OUUT faults that place potentially damaging voltages on the UUT
microprocessorsocket.
The over-voltage protection circuits guard against voltages of+12 to -7V on any
one pin. Multiple faults, especially of long duration, may cause pod damage.
Apower level sensing circuit constantly monitors the voltage level of the UUT
power supply (+5V). If UUT power rises above or drops below an acceptable
level, the pod notifies the mainframe of the power fail condition.
A self test socket provided on the pod enables the mainframe to check pod
operation. The self test socket is a 40-pin zero-insertion force type connector.
The ribbon cable plug must be connected to the self test socket during self test
operation. The ribbon cable plug should also be inserted into this socket when
the pod is not in use to provide protection for the plug.
1-3. SPECIFICATIONS
Specifications for the 9000A-Z80QT Interface Pod are listed in Table 1-1.
1-2

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m0<umwkz_
O:
m0<mmm._.2_
O\_
2<m
5.0m
mmOmn.
Fwy—00m
mOmmwOOmaOm—QE
w§<mu2_<_2
memw
005
m0
Doom
mXDJE
Flgure 1-1. Relationship of Interface Pod
1-3

ZSOQT
Table 1-1. ZSOQT Intertace Pod Specifications
ELECTRICAL PERFORMANCE
Power Dissipation .......... 3.0 watts maximum
Electrical Protection ........ -7 to +12V may be applied between ground
and any single ribbon cable plug pin contin—
uously as long as the pod is powered by the
mainframe.
MICROPROCESSOR SIGNALS
Clock Input Low ............ 0V min., +0.45V max.
Clock Input High ........... +4.4V min., +5.0V max.
Input Low Voltage .......... 0V min., +0.8V max.
Input High Voltage ......... +2.0V min., +5.0V max.
Output Low Voltage ........ +0.4V max. with lol :1.8 mA
Output High Voltage ........ +2.4V min. with Ioh =—250 pA
Trlstate Output Leakage
Current .................... $20 ,uA
High Level Input Current 20 ,uA typ. with Vih =+2.7V
Low Level Input Current—
BUSRQ, WAIT, RESET, NMI —400 pA max. with Vil :+0.4V
ALL OTHER INPUT LINES. —20 #A typ. with Vil 2+0.4v
TIMING CHARACTERISTICS
Maximum Clock Frequency ..8.0 MHz typ.
Added Delays to 280 Signals
LOW-TO-HIGH
TRANSITIONS ........... 20 ns typ.
HIGH—TO—LOW
TRANSITIONS ........... 24 ns typ.
UUT POWER DETECTION
Detection of Low Vcc Fault .. Vcc <+4.5V detected
Detection of High Vcc Fault. .Vcc >+5.5V detected

ZBOQT
Table 1-1. ZBOQT Interface Pod Specifications (cont)
GENERAL
Size ........................ 3.3 cm Highx10.2 cm Widex18.550m Deep
(1.3 in High x4.0 in Wide x7.4 in Deep)
Weight ..................... 0.68 kg (1.5 lbs)
Environmenl
STORAGE ................ —40° to +70°C, RH <95%
OPERATlNG .............. 0° to +25°C, RH <95%
+25° to +40°C, RH <75%
+40° to +50°C, RH <45%
Protecllon Class 3........... Relates solely to insulation or grounding
properties defined in IE0 348.
1-5/1-6

ZBOQT
Section 2
Installation
2-1. INSTALLING THE ZBOOT DATABASE (9100 SERIES ONLY)
The Z80QT database for the 9100—Series mainframe is contained on one 3.5-inch
floppy disk supplied with the 9000A-Z80QT Pod.
To install the databaseon amainframe with ahard drive, insert the disk into the
mainframe floppy drive. Press MAIN MENU on the keypad, press SOFT
KEYS, then select COPY DISK FROM DRl TO HDR. and press ENTER.
The database only needs to be installed once. Once the database is installed on
the mainframe, place the original floppy disk in asafe place in case it is needed.
To use the database on amainframe with two floppy drives, first copy the
database disk to abackup disk using the mainframe COPqunction. Remove
the original from the floppy drive and insert the copy into the system
USERDISK. Each time the mainframe is reset, the database is read from the
floppy disk. Place the original floppy disk in asafe place in case it is needed.
2-2. MAKING CONNECTIONS
Before a9000 Series or 9100 Series tester (mainframe) can be used to perform a
test or isolate afault, it must be connected to the UUT. Connectionis made by
means of the pod, which is equipped with two cable assemblies, one shielded-type
and one ribbon-type. Procedures for installing and connecting the pod are given
next.
Before making any connections to the UUT, read the following precautions:
WARNING
TO PREVENT POSSIBLE HAZARDSTO THE OPERATOR OR DAMAGE
TO THE UUT, DISCONNECT ALL HIGH-VOLTAGE
POWER SUPPLIES,
THERMAL ELEMENTS, MOTORS, OR MECHANICAL ACTUATORS
WHICH ARE CONTROLLED OR PROGRAMMED BY THE UUT MICRO-
PROCESSOR BEFORE CONNECTING POD.

ZBOQT
Be sure to install the ribbon cable plug correctly in the UUT micro-
processor socket.
The self test socket is intended for use with the ribboncable plug only. Do
not insert any microprocessorremoved from aUUT, or any other device
into this socket.
Connect the pod between the mainframe and the UUT as follows:
2-3.
1. Remove power from the UUT. Remove power from the mainframe.
2. Using the round shielded cable, connect the pod to the mainframe as
shown in Figure 2-1 (for 9000 Series) or Figure 2-2 (for 9100 Series).
Secure the connector using the sliding collar.
3. Apply power to the mainframe.
4. Performaself—testofthe pod as described in Section 5ofthis manual.
5. With UUT power off, unplug the microprocessor from the UUT.
6. On the pod, turn the self test socket thumbwheel to release the plug
from the self test socket.
7. Align the ribbon-cablewith the microprocessor socket on the UUT so
that the notched corner ofthe ribbon cable plug aligns with pin 1of the
socket. Insert the plug into the socket as shown in Figure 2-3.
8. Electrically reassemble the UUT. Use extender boards if necessary.
CAUTION
Make suremainframe power is on before turning UUT power on
in order to activate pod protection circuits.
9. Apply power to the mainframe and the UUT.
POWER CONNECTIONS
The pod receives +5 volts, -5 volts, and +12 volts from the mainframe. No
external power connections are required.
2—2

Z8OQT
Figure 2-1. Conneclion oi Interface Pod to 9000 Series
POD CONNECTS HERE
Figure 2-2. Connection oi lnterlace Pod to 9100 Series

ZBOQT
Figure 2-3. Connection 0! Interface Pod to UUT

3-1. INTRODUCTION
ZBOQT
Section 3
Pod Signals and Functions
This section is areference source for Z80QT pod—specific and 280 microprocessor
information. Information in this section includes descriptions of Z80 signals,
explanations of status/control lines and address space assignment, effects the
pod may have on normal UUT operation,pod capabilities and limitations, and
other pod characteristics.
3-2. Z80 SIGNALS
For reference, Table 3-1 lists all of the Z80 signals and provides abrief
description of each. Figure 3-1 shows the pin assignment of Z80 signals.
Table 3-1. 280 Slgnals
SIGNAL NAME DESCRIPTION
Address Lines
A0 -A15
Data lines
DO -D7
The 16 address lines are designated A0 throughA15.
The address lines are tri-state outputs and may be
logic high, logic low, or floated by the Z80 to ahigh
impedance state. The Z80 places the addresslines in
the high impedance stateto allow devices otherthan
the 280 to control the address bus during DMA
(Direct Memory Access) operations. See BUSRQ.
The 8data lines are designated DO through D7. The
data lines are tri-state bi-directional lines, which are
placed in the high impedance state during DMA
operations. See BUSRQ.
The Wline is acontrol line which identifies the Z80
instruction-fetch cycle. The 280 places Wat logic
low during the instruction-fetch cycle. Also, when
the 280 acknowledges an interrupt, both Wand
lORQ are driven low.
3—1

ZBOQT
Table 3-1. 280 Signals (cont)
SIGNAL NAME DESCRIPTION
MREQ Line
W—Fl Line
RFSH Line
HALT Line
AIT Line
WT and N
Lines 3
The MREQ output identifies amemory access
operation in progress. The 280 places MREQ at
logic low during any memory access operation. In
addition, MREQ is placed in ahigh impedance state
during DMA operations. See BUSRQ.
The IOFlQ output identifies any l/O operation in
progress. When lORQ is low, address lines A0 -A15
contain avalid l/O port address. The IORQ line is also
used in conjunction with the Wline as an interrupt
acknowledge. When the 280 acknowledges an inter-
rupt, both lines are driven low.
low.
The 725 output is pulled low to indicatethatthe 280
is ready to read data via the data lines from either
memory or an l/O device, as identified by the MREQ
or IORQ line. In addition, Fl_D is placed in a high
impedance state during DMA' operations. See
BUSRQ.
The Woutput is pulled low to indicate that the 280
is ready to write data via the data lines to either
memory or an l/O device, asflantified by the MREQ
or IORQ line. ln addition, WR is placed in ahigh
impedance state during DMA operations. See
BUSRQ.
The RFSH output is acontrol signal which may be
used in conjunction with the MREQ line to refresh
dynamic memories. When RFSH is pulled low the
MREQ signal and address lines A0 -A7 may be used to
refresh dynamic memories.
The HALT output is pulled low following the
execution of ahalt instruction. During the halt state,
the 280 continuously executes aNOP instruction in
order to maintain memory refresh activity.
The WAlT line is an input which, when placed at a
logic low level, causes the Z80 to enter await state.
During the wait state, the 280 inserts clock pulses to
extend the cycle time as required by the external
logic selecting the wait state.
The Wline is an input which permits external
interrupt of the 280 as long as interrupts are not
disabled and the BUSRQ line is not at alogic low.
The Wline is anon-maskable interrupt input
which cannot be disabled.