Force SYS68K/CPU-30 R4 Product manual

P/N 204030
FORCE COMPUTERS Inc./GmbH
All Rights Reserved
This document shall not be duplicated, nor its contents used
for any purpose, unless express permission has been granted.
Copyright by FORCE COMPUTERS
SYS68K/CPU-30 R4
Technical Reference Manual
Edition No. 2
February 1997

Table of Contents
i
TABLE OF CONTENTS
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Getting Started. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1.1 SYS68K/CPU-30 R4 Technical Reference Manual Set . . . . . . . . . . . . . . . . . . . 1
1.1.2 Overview of the Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Overview of the SYS68K/CPU-30 R4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2.1 Features of the CPU-30 R4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.4 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.5 History of Manual Publication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2 Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1.1 Caution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1.2 Board Installation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2 Location Diagrams of the SYS68K/CPU-30 R4 Board . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2.1 Before Powering Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3 Default Switch Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.4 Front Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.4.1 RESET and ABORT Keys. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.4.2 Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.4.3 Voltage Sensor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.4.4 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.4.5 Two Rotary Switches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

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2.5 Serial I/O Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
2.6 AUI-Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
2.7 SCSI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
2.8 Parallel I/O (Option) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
2.9 Connector Pinout for VMEbus P2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
2.10 Introduction to VMEPROM Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
2.10.1 Booting up VMEPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
2.11 The SYS68K/IOBP-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
3 Hardware Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.1 SYS68K/CPU-30 R4 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
3.2 The CPU 68030 Processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
3.2.1 Hardware Interface of the 68030 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
3.2.2 The Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
3.2.3 Vector Table of the 68030 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
3.3 The Floating Point Coprocessor (FPCP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
3.3.1 Features of the 68882. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
3.3.2 Interfacing to the 68882 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
3.3.3 Addressing the 68882. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
3.3.4 FPCP ID Number. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
3.3.5 Detection of the 68882. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
3.3.6 Summary of the 68882. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
3.4 The Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
3.4.1 The FGA-002 Gate Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
3.4.2 Shared DRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
3.4.2.1 Bank Selection of DRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
3.4.3 Board Type with Memory Capacity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
3.4.4 Reading the Shared RAM Capacity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

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3.4.5 Shared RAM Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.4.6 Shared RAM Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.5 The System PROM Area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.5.1 Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.5.2 Memory Organization of the System PROM Area . . . . . . . . . . . . . . . . . . . . . . 42
3.5.3 Read/Write to the System Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.5.4 Programming the System Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.5.5 Device Types for the System Flash Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.5.6 Address Map of the System PROM Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.5.7 Summary of the PROM Area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.6 The Boot PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.6.1 The Boot PROM Sockets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.6.1.1 Boot PROM Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.6.1.2 Device Type Selection for Optional Boot PROM (Socket J28). . . . . . 46
3.6.1.3 Programming the Boot PROM Devices. . . . . . . . . . . . . . . . . . . . . . . . 46
3.6.1.4 Programming Flash Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.6.2 The Boot PROM Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.6.2.1 Address Map of the Default Boot PROM Socket J36 . . . . . . . . . . . . . 47
3.6.2.2 Opt. Boot PROM Addresses (J28), SW5-1=OFF . . . . . . . . . . . . . . . . 48
3.6.2.3 Opt. Boot PROM Addresses (J28), SW5-1=ON . . . . . . . . . . . . . . . . . 48
3.6.3 Summary of the Boot PROM Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.7 The Local SRAM Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.7.1 Memory Organization SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.7.2 Used Devices for SRAM Area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.7.3 Access Time Selection of the SRAM Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.7.4 Backup Power for the SRAM Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.7.5 Summary of the SRAM Area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.8 The Real-Time Clock (RTC) 72423 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.8.1 Address Map of the RTC Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.8.2 RTC Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.8.3 RTC Programming Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.8.4 Backup Power for the RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

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3.8.5 Summary of the RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
3.9 The DUSCC 68562 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
3.9.1 Features of the DUSCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
3.9.2 Address Map of DUSCC #1 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
3.9.3 Address Map of DUSCC #2 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
3.9.4 Configuration of Serial I/O Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
3.9.5 RS-232 and RS-422/485 Driver Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
3.9.6 RS-232 Configuration of Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
3.9.7 RS-422/RS-485 Hardware Configuration of Serial Ports . . . . . . . . . . . . . . . . .66
3.9.8 Termination Resistors for RS-422/RS-485 Configuration. . . . . . . . . . . . . . . . .67
3.9.9 Summary of DUSCC #1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
3.9.10 Summary of DUSCC #2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
3.10 The PI/T 68230 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
3.10.1 Features of the PI/T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
3.10.2 Address Map of the PI/T #1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
3.10.3 I/O Configuration of PI/T #1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
3.10.4 Rotary Switches at PI/T #1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
3.10.5 Floppy Disk Drive Control Lines at PI/T #1 . . . . . . . . . . . . . . . . . . . . . . . . . . .71
3.10.6 DMA Control Lines at PI/T #1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
3.10.7 8-Bit User Defined I/O Port at PI/T #1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
3.10.8 Interrupt Request Signals of PI/T #1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
3.10.9 Floating Point Coprocessor Sense Line at PI/T #1 . . . . . . . . . . . . . . . . . . . . . .73
3.10.10 Reserved Line at PI/T #1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
3.10.11 Summary of PI/T #1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
3.10.12 Address Map of the PI/T #2 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
3.10.13 I/O Configuration of PI/T #2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
3.10.14 12-Bit User I/O Port at PI/T #2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
3.10.15 Memory Size Identification at PI/T #2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
3.10.16 Board Identification at PI/T #2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
3.10.17 Interrupt Request Signal of PI/T #2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
3.10.18 PC0-PC1 Hardware ID at PI/T #2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

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3.10.19 Floppy Drive Ready Signal at PI/T #2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
3.10.20 Floppy Drive Write Protect Signal at PI/T #2 . . . . . . . . . . . . . . . . . . . . . . . . . . 78
3.10.21 DMA Control Line at PI/T #2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
3.10.22 Flash Programming Control at PI/T #2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
3.10.23 Reserved Lines at PI/T #2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
3.10.24 Summary of PI/T #2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
3.11 SCSIbus Controller MB 87033/34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
3.11.1 Features of the 87033/34 SCSI Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
3.11.2 Address Map of MB 87033/34 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
3.11.3 The SCSI DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
3.11.3.1DMA Control Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
3.11.3.2DMA Transfer Programming Example . . . . . . . . . . . . . . . . . . . . . . . . 82
3.11.4 The SCSIbus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
3.11.4.1SCSIbus Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
3.11.4.2SCSIbus Signal Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
3.11.4.3SCSIbus Terminator Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
3.11.5 Summary of the SCSIbus Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
3.12 The Floppy Disk Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
3.12.1 Features of the FDC37C65C Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
3.12.2 Address Map of the FDC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
3.12.3 Data Rate Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
3.12.4 Drive Select Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
3.12.5 Motor-On Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
3.12.6 DMA Control Lines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
3.12.7 Floppy Disk Connector Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
3.12.7.1DMA Transfer Programming Example . . . . . . . . . . . . . . . . . . . . . . . . 86
3.12.8 Jumper Setting on the Floppy Disk Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
3.12.9 Summary of the Floppy Disk Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
3.13 The Local Area Network Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
3.13.1 Features of the Ethernet Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
3.13.1.1Ethernet Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
3.13.2 The Am7990 LANCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
3.13.2.1Address Map of the LANCE Registers . . . . . . . . . . . . . . . . . . . . . . . . 89

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3.13.2.2The LANCE Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
3.13.2.3Summary of the LANCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
3.13.3 The Am7992B Serial Interface Adapter (SIA) . . . . . . . . . . . . . . . . . . . . . . . . .90
3.13.4 Features of the Am7992B SIA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
3.13.4.1The Am7992B Transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
3.13.4.2The Am7992B Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
3.13.4.3Network Interface Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
3.13.5 The LAN Buffer RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
3.13.6 Summary of the LAN RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
3.14 Function Switches and Indication LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
3.14.1 RESET Function Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
3.14.2 ABORT Function Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
3.14.3 "RUN" LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
3.14.4 "BM" LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
3.14.5 Rotary Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
3.14.6 Reserved Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
3.15 The CPU Board Interrupt Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
3.16 VMEbus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
3.17 VMEbus Master Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
3.17.1 Data Transfer Size of the VMEbus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . .96
3.17.2 Address Modifier Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
3.18 VMEbus Slave Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
3.18.1 The Access Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
3.18.2 Data Transfer Size of the Shared RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
3.18.3 Address Modifier Decoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
3.19 The VMEbus Interrupt Handler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
3.19.1 VMEbus IACK Daisy Chain Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
3.20 VMEbus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
3.20.1 Single-Level VMEbus Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
3.20.2 VMEbus Requester . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103

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vii
3.20.3 VMEbus Release Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
3.20.3.1Release Every Cycle (REC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
3.20.3.2Release on Request (ROR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
3.20.3.3Release After Timeout (RAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
3.20.3.4Release on Bus Clear (RBCLR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
3.20.3.5Release When Done (RWD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
3.20.3.6Release on ACFAIL (ACFAIL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
3.20.3.7Summary of Release Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
3.20.4 VMEbus Grant Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
3.21 Slot-1 Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
3.21.1 Special Slot-1 Situation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
3.21.2 Slot-1 Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
3.21.3 Enabling the Arbiter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
3.21.4 The SYSCLK Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
3.21.5 VMEbus Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
3.22 Exception Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
3.22.1 The SYSFAIL* Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
3.22.2 The SYSRESET* Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
3.22.3 The ACFAIL* Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
3.23 Reset Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
3.23.1 Front Panel Reset Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
3.23.2 The RESET Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
3.23.3 Voltage Sensor Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
4 Circuit Schematics and Data Sheets . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
4.1 Circuit Schematics of SYS68K/CPU-30 R4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
4.2 List of Data Sheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
4.2.1 RTC 72421. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
4.2.2 DUSCC 68562. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
4.2.3 PI/T TS68230. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
4.2.4 SCSI 87033/34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Table of Contents
viii
4.2.5 FDC37C65C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
4.2.6 LANCE Am79C90. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
4.2.7 SIA Am7992B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
4.2.8 Motorola MC68030 and MC68882 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
5 VMEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
5.1 General Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
5.2 Features of VMEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
5.3 Power-up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
5.4 Front Panel Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
5.4.1 RESET Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
5.4.2 ABORT Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
5.4.3 Control Switches (Rotary Switches) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
5.4.4 Default Memory Usage of VMEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
5.4.5 Default ROM Usage of VMEPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
6 Devices and Interrupts used by VMEPROM . . . . . . . . . . . . . . . . . . . . 133
6.1 Addresses of the On-board I/O Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
6.2 On-board Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
6.3 Off-board Interrupt Sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
6.4 The On-board Real-Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
7 Concept of VMEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
7.1 Getting Started. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
7.2 Command Line Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
7.3 VMEPROM Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136

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ix
8 Special VMEPROM Commands for CPU Boards . . . . . . . . . . . . . . . . 137
8.1 ARB - Set the Arbiter of the CPU Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
8.2 CONFIG - Search VMEbus for Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
8.3 FERASE - Erase Flash Memories. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
8.4 FGA - Change Boot Setup for Gate Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
8.5 FLUSH - Set Buffered Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
8.6 FMB - FORCE Message Broadcast . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
8.7 FPROG - Program Flash Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
8.8 FUNCTIONAL - Perform Functional Test. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
8.9 MEM - Set Data Bus Width of the VMEbus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
8.10 SELFTEST - Perform On-board Selftest . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
8.11 Installing a New Hard Disk. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
9 Appendix to VMEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
9.1 Driver Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
9.1.1 VMEbus Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
9.1.2 SYS68K/SIO-1/2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
9.1.3 SYS68K/ISIO-1/2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
9.1.4 SYS68K/WFC-1 Disk Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
9.1.5 SYS68K/ISCSI-1 Disk Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
9.1.6 Local SCSI Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
9.2 S-Record Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
9.2.1 S-Record Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
9.3 System RAM Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
9.4 Task Control Block Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
9.5 Interrupt Vector Table of VMEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

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x
9.6 Benchmark Source Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165
9.7 Modifying Special Locations in ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
9.8 Binding Applications to VMEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
9.8.1 General Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
9.8.2 Using External Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
9.8.3 Using System Flash Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
9.8.4 Binding the Application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
10 Special FGA Boot Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
10.1 AS - Line Assembler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180
10.2 CONT - Continue with Calling Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181
10.3 DI - Disassembler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182
10.4 DRAMINIT - Initialize DRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182
10.5 FERASE - Erase Flash Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183
10.6 FPROG - Program Flash Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184
10.7 GO - Go to Subroutine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185
10.8 LO - Load S-Records to Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186
10.9 NETLOAD - Load File via Network to Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187
10.10 NETSAVE - Save Data via Network to File. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188
10.11 SETUP - Change Initialization Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189
10.12 SLOT - Change Slot Number and VMEbus Slave Address . . . . . . . . . . . . . . . . . . . . . .190
10.13 VMEADDR - Change VMEbus Slave Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190
11 The FGA Boot Utility Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

Page xi
SYS68K/CPU-30 R4 Technical Reference Manual Table of Contents
List of Figures
Figure 1. Diagram of the CPU-30 R4 (Top View) .......................................................................... 13
Figure 2. Diagram of the CPU-30 R4 (Bottom View) .................................................................... 14
Figure 3. Front Panel ....................................................................................................................... 19
Figure 4. The 48-bit (6-byte) Ethernet address ............................................................................... 88
Figure 5. Functional Block Diagram of the Ethernet Interface ....................................................... 89
Figure 6. Boot up procedure .......................................................................................................... 178
Figure 7. Boot up procedure (continued) ...................................................................................... 179

Table of Contents SYS68K/CPU-30 R4 Technical Reference Manual
Page xii
List of Tables
Table 1. Specifications for the CPU-30 R4 Board........................................................................... 7
Table 2. Ordering Information......................................................................................................... 9
Table 3. History of Manual............................................................................................................ 10
Table 4. Default Switch Settings.................................................................................................... 15
Table 5. Front Panel Layout........................................................................................................... 18
Table 6. 9-pin D-Sub Connector Pinout (RS-232)......................................................................... 21
Table 7. 15-pin AUI-Ethernet Connector....................................................................................... 22
Table 8. Signal Assignment of the VME P2 Connector ................................................................ 24
Table 9. Rotary Switches ............................................................................................................... 25
Table 10. SYS68K/IOBP-1 Pin Assignment ................................................................................... 26
Table 11. SYS68K/CPU-30 R4 Memory Map ................................................................................ 30
Table 12. Exception Vector Assignments........................................................................................ 33
Table 13. Used Device Types for the Shared Memory.................................................................... 38
Table 14. Device Types used for System Flash Memory ................................................................ 44
Table 15. Address Map of the PROM Area..................................................................................... 44
Table 16. RTC Register Layout....................................................................................................... 54
Table 17. Serial I/O Port #4 (DUSCC #1) Register Address Map................................................... 59
Table 18. Serial I/O Port #1 (DUSCC #1) Register Address Map................................................... 60
Table 19. Ports #1 and #4 (DUSCC #1) Common Register Address Map...................................... 60
Table 20. Serial I/O Port #2 (DUSCC #2) Register Address Map................................................... 61
Table 21. Serial I/O Port #3 (DUSCC #2) Register Address Map................................................... 62
Table 22. Ports #2 and #3 (DUSCC #2) Common Register Address Map...................................... 62
Table 23. Switches & Module Assignment for Serial Port Configuration ...................................... 63
Table 24. PI/T #1 Register Layout................................................................................................... 69
Table 25. PI/T #1 Interface Signals.................................................................................................. 69
Table 26. Rotary Switch Signals Assignment.................................................................................. 70
Table 27. PI/T #2 Register Layout................................................................................................... 74
Table 28. PI/T #2 Interface Signals.................................................................................................. 75
Table 29. LANCE Register Layout.................................................................................................. 89
Table 30. Data Bus Size of the VMEbus (Master Interface) ........................................................... 96
Table 31. Defined VMEbus Transfer Cycles (D32 Mode).............................................................. 97
Table 32. VMEbus Transfer Cycles (D16 Mode)............................................................................ 97
Table 33. Address Ranges................................................................................................................ 97
Table 34. Address Modifier Codes .................................................................................................. 98
Table 35. Address Modifier Codes Used by the CPU Board........................................................... 99
Table 36. VMEbus Slave AM Codes............................................................................................. 101
Table 37. Bus Release Functions................................................................................................... 106
Table 38. Upper Rotary Switch (SW2).......................................................................................... 128
Table 39. Lower Rotary Switch (SW1).......................................................................................... 128
Table 40. RAM Disk Usage........................................................................................................... 128
Table 41. Program After Reset....................................................................................................... 129
Table 42. Boot an Operating System (if AUTOBOOT is selected)............................................... 129
Table 43. Examples in Using the Rotary Switches........................................................................ 129
Table 44. Main Memory Layout.................................................................................................... 130
Table 45. Layout of System Flash Memory................................................................................... 130
Table 46. On-board I/O Devices.................................................................................................... 133
Table 47. On-board Interrupt Sources............................................................................................ 133
Table 48. Off-board Interrupt Sources........................................................................................... 134
Table 49. User’s Patch Table......................................................................................................... 172

SYS68K/CPU-30 R4 Technical Reference Manual Introduction
Page 1
1 Introduction
1.1 Getting Started
This SYS68K/CPU-30 R4 Technical Reference Manual provides a
comprehensive guide to the CPU-30 R4 board you purchased from
FORCE COMPUTERS. In addition, each board delivered by FORCE
includes an Installation Guide.
CAUTION: Before installing the board, please read the complete
installation instructions.
1.1.1 SYS68K/CPU-30
R4 Technical
Reference Manual
Set
When purchased from FORCE, this set includes the SYS68K/CPU-30 R4
Technical Reference Manual, a copy of the circuit schematics, and copies
of the following data sheets:
1.1.2 Overviewofthe
Manual Section 1 provides a brief overview of the product, the specifications, the ordering information, and the publication history of the manual.
Information concerning the installation, default configuration,
initialization, and connector pinouts is included in Section 2. A detailed
hardware description is described in Section 3. The CPU board operates
under the control of VMEPROM, which is described in Sections 5, 6, 7,
8, and 9. There is additional space allocated in the manual for user notes,
modifications, etc.
NOTE: Please take a moment to examine the Table of Contents of the
SYS68K/CPU-30 R4 Technical Reference Manual to see how this
documentation is structured. This will be of value to you when looking
for information in the future.
1. The FDC37C65C is pin-to-pin compatible with Industry Standard
WD37C65C
RTC 72421 FDC37C65C1)
DUSCC 68562 LANCE Am79C90
PI/T TS68230 SIA Am7992B
SCSI 87033/34 Motorola MC68030 and MC68882
i

Introduction SYS68K/CPU-30 R4 Technical Reference Manual
Page 2
1.2 Overview of the SYS68K/CPU-30 R4
This CPU board is a high performance single-board computer based on
the 68030 microprocessor and the VMEbus. The CPU board also
includes an enhanced Floating Point Coprocessor 68882. The board
design utilizes all of the features of the powerful FORCE Gate Array
FGA-002.
The CPU-30 R4 provides an A32/D32 VMEbus interface including
DMA, up to 32 Mbyte shared DRAM on-board, up to 8 Mbyte System
Flash Memory, an Ethernet Interface, a single-ended SCSI interface, a
floppy interface, four RS-232 serial I/O channels, up to 256 Kbyte
SRAM and a Real-Time Clock, both with on-board battery backup.
Besides the CPU-30 R4, there will be a CPU-30Lite R4 without a
coprocessor, a SCSI, an Ethernet, and a floppy disk interface.
SEE ALSO: Please refer to Table 2, “Ordering Information,” on page 9
for more detailed information.
The shared DRAM is accessible from the 68030 CPU, the FGA-002
DMA controller, and also from other VMEbus masters.
The CPU-30 R4 has an Ethernet port and three serial ports available on
the front panel permitting a console port, download and data
communication channels. One further serial port, as well as the SCSI
interface and the Floppy interface are available via the 3-row VMEbus P2
connector. A 20-bit parallel interface and the three serial ports on the
front panel are available via the optional 5-row VMEbus P2 connector.
1.2.1 Features of the
CPU-30 R4 The main features of the SYS68K/CPU-30 R4 board are listed below.
Processor
- 68030 with 25 MHz frequency
- Flexible high bandwidth synchronous bus
- 68020 compatible integer unit
- Memory management unit
- Independent data and instruction memory management units
- Dual 256-byte on-chip caches for instructions and data
- 4-Gbyte addressing range
- Upward user object code compatible with the 68020
☞

SYS68K/CPU-30 R4 Technical Reference Manual Introduction
Page 3
Coprocessor
- 68882 with 25 MHz frequency
- Pin- and SW-compatible with the MC68881
Main Memory
- 4, 8, 16, or 32 Mbyte of shared DRAM on-board
- Byte parity
VMEbus Interface
- Via FGA-002 in the 304-pin PQFP package
- Slot-1 detection switch enabled
-Master:
A32, A24, A16: D8, D16, D32, ADO, UAT, RMW
AM CODES:
Standard supervisory data/program access
Standard non-privileged data/program access
Short supervisory access
Short non-privileged access
Extended supervisory data/program access
Extended non-privileged data/program access
-Slave:
A32: D8, D16, D32, ADO, UAT, RMW
Access Address: SW programmable (FGA-002)
AM CODES:
Standard supervisory data/program access
Standard non-privileged data/program access
Extended supervisory data/program access
Extended non-privileged data/program access
SW programmable inside FGA-002 for DMA controller
Single-level arbiter
Request modes: ROR, RBCLR, REC, RAT
IACK daisy chain driver
FORCE Message Broadcast (FMB)

Introduction SYS68K/CPU-30 R4 Technical Reference Manual
Page 4
System Flash Memory
- 4 Mbyte Flash Memory is default configuration
- Up to 8 Mbyte Flash Memory
- 32-bit wide
- Reprogrammable on-board
- HW write protection
Ethernet Interface
- Via AM79C90
- Compatible with IEEE 802.3 Rev.0
- On-Chip DMA and buffer management
- 48-byte FIFO
- 24-bit wide linear addressing
- Network and packet error reporting
- Back-to-back reception with as little as 4.1 µ s inter-packet gaptime
- AUI Ethernet available on the front panel via a standard 15-pin D-
Sub connector.
SCSI Interface
- Via MB87033/34
- Full support for SCSI control
- Service of either initiator or target device
- 8-byte data buffer register incorporated
- Transfer byte counter (28-bit)
- Independent control and data transfer bus
- On-chip single-ended drivers/receivers
- SCSI interface available on the VMEbus P2 connector
Floppy Disk Interface
- Via FDC37C65C (the FCD37C65C is pin-to-pin compatible with
Industry Standard WD37C65C)
- Available on VMEbus P2 connector

SYS68K/CPU-30 R4 Technical Reference Manual Introduction
Page 5
Boot ROM
- 128 -, 256 -, and 512 Kbyte of Flash Memory or up to 1 Mbyte OTP
- 8-bit wide
- Reprogrammable on-board in case of Flash Memory
- HW write protection in case of Flash Memory
- Two 32-pin PLCC sockets
Serial I/O Ports
- Via 68562 DUSCC
- Dual full-duplex asynchronous receiver and transmitter
(programmable)
- Multi-protocol operation enabling support of bit- or character-
oriented protocols
- Additional software allows the support of HDLC, SDLC, BISYNC,
etc.
- Three ports available on the front panel via standard 9-pin D-Sub
connectors
- One port available on standard 3-row VMEbus P2 connector.
- All channels support RS-232 or RS-422 via the FORCE hybrids
FH-00x – as factory option also RS-485.
- RS-422 – and as factory option also RS-485 – terminations via
cable resistors
Parallel I/O
- Available via two 68230 PI/T
- 20-bit user I/O available on optional 5-row VMEbus P2 connector,
TTL level
SRAM
- 32-Kbyte or 128-Kbyte (assembly option) SRAM
- Optional 512-Kbyte SRAM in DIL package
- 8-bit wide
- On-board battery backup or backup via +5V-Stdby
- Socketed battery

Introduction SYS68K/CPU-30 R4 Technical Reference Manual
Page 6
RTC
- Real-Time Clock 72423
- IRQ capability
- Time of day and date counter included (year, month, week, day)
- Built-in quartz oscillator
- 12 hr/24 hr clock switch-over
- Automatic leap year setting
- CMOS design provides low power consumption during power-
down mode
- On-board battery backup or backup via +5V-Stdby
- Socketed battery
Additional Features
- RESET/ABORT key
- Reset watchdog timer
- Status LEDs
- Rotary switches

SYS68K/CPU-30 R4 Technical Reference Manual Introduction
Page 7
1.3 Specifications
Table 1: Specifications for the CPU-30 R4 Board
CPU type 68030
CPU clock frequency 25 MHz
Shared DRAM capacity with parity CPU-30ZBE R4
CPU-30BE/8 R4
CPU-30BE/16 R4
factory option
CPU-30Lite/4 R4
CPU-30Lite/8 R4
4 Mbyte
8 Mbyte
16 Mbyte
32 Mbyte
4 Mbyte
8 Mbyte
SRAM capacity with on-board battery backup 32 Kbyte
128 Kbyte SRAM (optional)
No. of system EPROM sockets
Data path 4 32-bit
Serial I/O interfaces
RS-232/422/RS-485 compatible
3 via the front panel and via
the 3-row VME P2 connec-
tor and 1 via the optional
5-row VME P2 connector
via FORCE hybrids
Ethernet Interface
Ethernet SRAM buffer AM7990 64 Kbyte
Parallel I/O interface (optional) Via 68230 PI/T
20 lines
Real-Time Clock with on-board battery backup RTC 72423
SCSI interface MB87033/34
Single-ended
Floppy disk interface FDC37C65C1)
24-bit timer with 5-bit prescaler
8-bit timer 2 1
VMEbus interface A32,A24,A16:D8,D16,D32,ADO,UAT,RMW
A32:D8,D16,D32,ADO,UAT,RMW Master Slave
ARBITER
SYSCLK driver
Mailbox interrupts
Single-level
yes
8
FORCE Message Broadcast FMB-FIFO 0
FMB-FIFO 1 8 byte 1 byte
VMEbus interrupter (level programmable)
VMEbus and local interrupt handler
Programmable IRQ levels for all sources
Total number of IRQ sources
none
1 to 7
yes
42