Frontgrade Gr740-mini User manual

Quick start guide for GR740-MINI Evaluation board

GR740-MINI

GR740-MINI Quick Start Guide

USER MANUAL

RELEASED NOVEMBER 2023

Nov 2023, Version 1.0

Nov 2023, Version 1.0 2

Table of Contents

1. Introduction .......................................................................................................................... 3

1.1. Overview ................................................................................................................... 3

1.2. IP addresses ............................................................................................................... 3

1.3. Handling .................................................................................................................... 3

1.4. References .................................................................................................................. 3

2. Overview .............................................................................................................................. 4

3. Board Configuration ............................................................................................................... 5

3.1. Overview ................................................................................................................... 5

3.2. Power Up the board ..................................................................................................... 5

3.3. LED power indication .................................................................................................. 5

3.4. Switch buttons ............................................................................................................ 6

3.4.1. Master reset (SW1) ........................................................................................... 6

3.4.2. Program switch (SW2) ....................................................................................... 6

3.5. FTDI chip .................................................................................................................. 6

4. FPGA development Environment .............................................................................................. 7

4.1. Lattice Radiant Software ............................................................................................... 7

4.2. Program the FPGA ...................................................................................................... 7

4.2.1. Lattice programmer ........................................................................................... 7

4.2.2. GRMON3 ........................................................................................................ 7

5. GRMON3 hardware debugger .................................................................................................. 9

5.1. Overview ................................................................................................................... 9

5.2. GR740 License options ................................................................................................ 9

5.3. Debug-link alternatives for GR740 ................................................................................. 9

5.3.1. Connecting via the FTDI USB/JTAG interface ....................................................... 9

5.3.2. Connecting via the Ethernet debug interfaces ......................................................... 9

5.4. Debug-link alternatives for CertusPro ............................................................................ 10

5.4.1. Connecting via the FTDI USB/UART interface .................................................... 10

5.4.2. Connecting via the Ethernet debug interfaces ........................................................ 10

5.5. First steps ................................................................................................................. 10

5.6. Connecting to the board .............................................................................................. 11

5.6.1. GR740 ........................................................................................................... 11

5.6.2. CertusPro ....................................................................................................... 14

6. Examples Bitstreams ............................................................................................................. 15

6.1. Overview .................................................................................................................. 15

6.2. Cores and Memory Map ............................................................................................. 15

6.2.1. ex-1 .............................................................................................................. 15

7. Support ............................................................................................................................... 17

Nov 2023, Version 1.0 3

1. Introduction

1.1. Overview

This document is a quick start guide for the GR740-MINI Development Board.

The purpose of this document is to get users quickly started using the board.

For a complete description of the board please refer to the GR740-MINI Board User's Manual

The GR740 system-on-chip is described in the GR740 Data Sheet and User’s Manual.

The CertusPro FPGA is described in the CertusPro-NX Family Data Sheet.

This quick start guide does not contain as many technical details and is instead how-to oriented. However, to make

the most of the guide the user should have glanced through the aforementioned documents and should ideally also

be familiar with the GRMON debug monitor.

1.2. IP addresses

The GR740-MINI board is equipped with two Ethernet ports that have default IP addresses 192.168.0.24 and

192.168.0.51. The GR740-MINI should not be connected to an existing network where these addresses may be

already occupied. Please see Chapter 5 before conneceting to the network or for more information.

1.3. Handling

This unit contains sensitive electronic components which can be damaged by Electrostatic Discharges (ESD).

When handling or installing the unit observe appropriate precautions and ESD safe practices.

When not in use, store the unit in an electrostatic protective container or bag.

When connecting/disconnecting cables, ensure that the unit is in an un-powered state.

This equipment has SpW ports that use Low Voltage Differential Signalling (LVDS) which has limited common

mode voltage protection. Please refer to the user’s manual for instructions on how to ensure that the grounds of

equipment are connected together when using SpaceWire.

1.4. References

Table 1.1. References

RD-1 GR740-MINI User’s Manual [https://gaisler.com/index.php/products/boards/gr740-mini]

RD-2 GR740 Data Sheet and User’s Manual [https://gaisler.com/gr740]

RD-3 CertusPro-NX Family Data Sheet [https://www.latticesemi.com/Products/FPGAandC-

PLD/CertusPro-NX]

RD-4 GRMON User's Manual [https://www.gaisler.com/doc/grmon3.pdf]

RD-14 GRLIB IP Core User’s Manual [https://www.gaisler.com/products/grlib/grip.pdf]

Nov 2023, Version 1.0 4

2. Overview

The GR740-MINI board is a compact evaluation platform built around the Frontgrade GR740 quad-core

LEON4FT SPARC V8 processor and Lattice Semiconductor FPGA CertusPro-NX, shown in Figure 2.1.

Figure 2.1. Top view of GR740-MINI board

The GR740-MINI architecture includes the following modules:

• 2 x USB-C connectors for debug and power

• GR470 Processor

• 1 x USB interface via FTDI FT4232 providing JTAG and UART

• 1 x Ethernet for communication and debug

• 4 x SpaceWire channels to FMC+ connector

• 256MiB SDRAM

• 128MiB FLASH

• CertusPro-NX FPGA

• 1 x USB interface via FTDI FT4232 providing JTAG and UART

• 1 x Ethernet for communication and debug

• 4 x SerDes to FMC+ connector

• LVDS to FMC+ connector

• 3V3 IO to FMC+ connector

• I2C link to FMC+ connector

• 1GiB DDR3 memory

• 512Mib SPI FLASH

• Intercommunication between GR740 and CertusPro-NX

• PCI link 32bit 33MHz

• GMII/MII

• 4 x SpaceWire channels

Nov 2023, Version 1.0 5

3. Board Configuration

3.1. Overview

The primary sources of information for the development board is the GR740-MINI User’s Manual. The primary

information for the Processor is GR740 Data Sheet and User’s Manual and for the FPGA CertusPro-NX Family

Data Sheet

3.2. Power Up the board

The GR740-MINI board is powered using either of the USB-C connectors (J1 or J2). Therefor there are two ways

to power up the board and is accomplished by attaching a 2-pin jumper to the 3-pin head (JP5), see Figure 3.1.

The overall power requirement for the board is 15W. Note that both the UCB-C cable and source must deliver

at least 3A, 5V (15W). Observe that not all sources with USB-C sockets support that. Check the sources manual

before connecting to the GR740-MINI board.

J2 is considered as the main power supply, and the configuration jumper is set to this as default JP5: 1-2 mode

(blue). This mode can be used when communicating with USB-C (data and power through the same cable), Eth-

ernet or FMC+ connector.

If J2 is connected to a source that cannot provide the minimum power requirement (for example a computer or a

docking station), then J1 can be connected to a external power source. Set jumper JP5 to 2-3 (red) mode to use

J1 as the power source.

Figure 3.1. Jumper configuration for power supply

3.3. LED power indication

When powering the board there are 3 LED for indicating the availability and communication status see Figure 3.2.

• LED1 Indicates that 3V3 is available

• LED2 Light when USB is in suspended mode

• LED3 Indicate normal USB operational mode

Nov 2023, Version 1.0 6

Figure 3.2. Led indication for power

3.4. Switch buttons

3.4.1. Master reset (SW1)

There is switch button (SW1) to reset the board. The reset signal will reset the GR740, the Ethernet PHYs, flash

memory (GR740) and the FPGA user design. It will not trigger an FPGA reconfiguration or interrupt USB com-

munication

3.4.2. Program switch (SW2)

This switch is connected to the FPGA and will initiate configuration sequence when asserted.

3.5. FTDI chip

A FTDI FT4323HP chip is connected to USB-C connector J2 and provides Serial to USB conversion up to 4 ports.

In Table 3.1 the port are listed. The corresponing "vendor id" is 0403 and "product id" is 6043 for the FTDI chip.

Table 3.1. FTDI port assignment

Port Function Target

A JTAG GR740

B JTAG CertusPro-NX

C UART GR740

D UART CertusPro-NX

Nov 2023, Version 1.0 7

4. FPGA development Environment

4.1. Lattice Radiant Software

Lattics provides a software development tool for the FPGA development. Lattice Radiant software is available for

both linux and windows enviorment. Can be downloaded from https://www.latticesemi.com/latticeradiant

4.2. Program the FPGA

The FPGA can be programmed in the volatile (RAM) memory or non-volatile (SPI flash) memory. The FPGA is

programmed with JTAG through the FTDI chip.

4.2.1. Lattice programmer

TBC

4.2.2. GRMON3

GRMON3 can be used to program the FPGA in both linux and windows enviorment, see sections below for

prerequisites. Note that GRMON version 3.3.6 or higher is needed.

In order to program the FPGA using GRMON3 it is needed to connect the debuglink to GR740 via JTAG, please

se section Section 5.3.1 for how to connect. In GRMON3, the following command is used to program the RAM

grmon3> fpgaload ex-1.bit

write to ram

Jtag frequency : requested 1.00MHzOpen file: DONE

Parse file: DONE

Enable configuration: DONE

SRAM erase: DONE

Loading: [==================================================] 100.00%

Done

Disable configuration: DONE

4.2.2.1. Linux prerequisites

Prerequisites: the following programs needs to be installed:

• libusb-1.0

• libftdi1

• libudev

• libhidapi-hidraw

• libz

• glibc-2.29 or higher

• libstdc++.so.x.x.21 or higher

4.2.2.2. Windows prerequisites

To be able to program the FPGA you must replace the driver for the FT4232 interface connected to FPGA. The

tool Zadig can be used for this purpose and can be downloaded from https://zadig.akeo.ie/ . Start Zadig and click

on "Options" and enable "List All Devices" from the drop-down menu. Select GR740-MINI (Interface 1) and set

the driver to WinUSB as in Figure 4.1. Click on "Replace Driver"

Nov 2023, Version 1.0 8

Figure 4.1. Zadig interface

Nov 2023, Version 1.0 9

5. GRMON3 hardware debugger

5.1. Overview

GRMON3 is a debug monitor used to develop and debug GRLIB/LEON systems. The target system, including

the processor and peripherals, is accessed on the AHB bus through a debug-link connected to the host computer.

GRMON3 has GDB support which makes C/C++ level debugging possible by connecting GDB to the GRMON3's

GDB socket. With GRMON3 one can for example:

• Inspect LEON and peripheral registers

• Upload applications to RAM with the load command.

• Program the FLASH with the flash command.

• Control execution flow by starting applications (run), continue execution (cont), single-stepping (step), in-

serting breakpoints/watchpoints (bp) etc.

• Inspect the current CPU state listing the back-trace, instruction trace and disassemble machine code.

The first step is to set up a debug link in order to connect to the board. The following section outlines which

debug interfaces are available and how to use them on the GR740-MINI Evaluation Board. After that, a basic first

inspection of the board is exemplified.

5.2. GR740 License options

The GRMON3 evaluation version which is freely available can be used to operate the GR740-MINI board. The

evaluation version does not support any other GR740 boards. The evaluation version is limited in certain regards

compared with the GRMON3 professional product. GRMON3 can be downloaded from the GRMON3 homepage

[RD-4].

The following table summarizes the GRMON3 license options for GR740.

Table 5.1. GRMON3 license options for GR740. All references to GRMON3 is for version 3.3.6 or later.

Program version License Supported hardware

GRMON3 professional Professional • All GR740 systems

• All LEON/GRLIB systems

GRMON3 evaluation Evaluation (21 days free)

• No cost

• No registration

• GR740-MINI

5.3. Debug-link alternatives for GR740

5.3.1. Connecting via the FTDI USB/JTAG interface

Please see GRMON User's Manual for how to set up the required FTDI driver software.

Due to the SDRAM configuration on the board the -sddcs flag must be set. -jtagserial is used to connect to the

board, where xxx is the serialnumber of the board. Connect the PC to the board by using a USB cable to the J2

connector and issue the following command:

grmon -ftdi -jtagserial GR740M0xxxA -sddcs

5.3.2. Connecting via the Ethernet debug interfaces

Note: Debugging using Ethernet is not supported by grmon-eval

The GR740 supports one Ethernet debug communication link (EDCL) in the default configuration of the GR740-

MINI. The debug link have default address 192.168.0.24. The GR740-MINI should not be connected to an existing

network where this address may be already occupied.

If another address is wanted for the Ethernet debug link then one of the other debug links must be used to connect

GRMON3 to the board. The EDCL IP address can then be changed using GRMON3's edcl command. This new

address will persist until next system reset.

Nov 2023, Version 1.0 10

Ethernet debug link traffic is routed to the Debug AHB bus as default. Ethernet debug link traffic can be routed

either to the Master I/O AHB bus or to the Debug AHB bus by changing a bootstrap signal. In order to control

the LEON processors the debug link must be routed to the Debug AHB bus, otherwise GRMON3 will not be able

to use the debug link to access the Debug Support Unit.

After reset the Ethernet debug communication link will attempt to configure the Ethernet PHY. In order for this

to succeed, the Ethernet port must be connected to a switch or other networking equipment.

Connect the Ethernet to connector J3B. Due to the SDRAM configuration on the board the -sddcs flag must be

set. Issue the following command:

grmon -eth 192.168.0.24 -sddcs

5.4. Debug-link alternatives for CertusPro

The interfaces to debug the CertusPro can vary depening on how the FPGA is programmed. In this chapter the

interfaces that will be provided from our pre-built bitsreams will be described.

5.4.1. Connecting via the FTDI USB/UART interface

Please see GRMON User's Manual for instructions how to connect GRMON3 to a board using a serial UART

connection. The PC is connected using a USB cable to the USB connector J2 and then start GRMON3 with the

-uart PORTNAME debug-link option and device name.

Example in Linux:

grmon -uart /dev/ttyUSB3

Example in Windows:

grmon -uart \\.\COM6

5.4.2. Connecting via the Ethernet debug interfaces

Note: Debugging using Ethernet is not supported by grmon-eval

Ethernet debug communication link (EDCL) have default address 192.168.0.51 The GR740-MINI should not be

connected to an existing network where these addresses may be already occupied.

If another address is wanted for the Ethernet debug link then one of the other debug links must be used to connect

GRMON3 to the board. The EDCL IP address can then be changed using GRMON3's edcl command. This new

address will persist until next system reset.

The Ethernet debug link traffic is routed to the Debug AHB bus.

After reset the first Ethernet debug communication link will attempt to configure the Ethernet PHY. In order for

this to succeed, the Ethernet port must be connected to a switch or other networking equipment. Connect the

Ethernet to connector J3A and issue the following command:

grmon -eth 192.168.0.51

5.5. First steps

The previous sections have described which debug-links are available and how to start using them with GRMON3.

The subsections below assume that GRMON3, the host computer and the GR740-MINI board have been set up

so that GRMON3 can connect to the board.

When connecting to the board for the first time it is recommended to get to know the system by inspecting the

current configuration and hardware present using GRMON3. With the info sys command more details about the

system is printed and with info reg the register contents of the I/O registers can be inspected. Below is a list of

items of particular interest:

• AMBA system frequency is printed out at connect, if the frequency is wrong then it might be due to noise in

auto detection (small error). See -freq flag in the GRMON User's Manual [RD-4].

• Memory location and size configuration is found from the info sys output.

Nov 2023, Version 1.0 11

5.6. Connecting to the board

5.6.1. GR740

The transcript below shows an example session with GRMON3. GRMON3 is started with the -u flag in order to

redirect UART output to the GRMON3 terminal.

user@user:~/ $ grmon -ftdi -jtagserial GR740M0001A -sddcs -u

GRMON debug monitor v3.3.6 64-bit eval version

For latest updates, go to https://www.gaisler.com/

Comments or bug-reports to [email protected]

This eval version will expire on 28/04/2024

Parsing -ftdi

Parsing -sddcs

Parsing -u

Commands missing help:

echotrace

package

JTAG chain (1): GR740

Device ID: 0x740

GRLIB build version: 4153

Detected system: GR740 rev1

Detected frequency: 250.0 MHz

Component Vendor

JTAG Debug Link Frontgrade Gaisler

GRSPW2 SpaceWire Serial Link Frontgrade Gaisler

EDCL master interface Frontgrade Gaisler

LEON4 SPARC V8 Processor Frontgrade Gaisler

IO Memory Management Unit Frontgrade Gaisler

AHB-to-AHB Bridge Frontgrade Gaisler

L2-Cache Controller Frontgrade Gaisler

AHB Memory Scrubber Frontgrade Gaisler

IOMMU secondary master i/f Frontgrade Gaisler

AHB-to-AHB Bridge Frontgrade Gaisler

LEON4 Debug Support Unit Frontgrade Gaisler

AHB/APB Bridge Frontgrade Gaisler

AMBA Trace Buffer Frontgrade Gaisler

AHB/APB Bridge Frontgrade Gaisler

Muxed FT DDR/SDRAM controller Frontgrade Gaisler

Memory controller with EDAC Frontgrade Gaisler

GRPCI2 PCI/AHB bridge Frontgrade Gaisler

GRSPW Router Frontgrade Gaisler

LEON4 Statistics Unit Frontgrade Gaisler

GRPCI2 Trace buffer Frontgrade Gaisler

Generic UART Frontgrade Gaisler

General Purpose I/O port Frontgrade Gaisler

Multi-processor Interrupt Ctrl. Frontgrade Gaisler

Modular Timer Unit Frontgrade Gaisler

GRSPW Router DMA interface Frontgrade Gaisler

GR Ethernet MAC Frontgrade Gaisler

CAN Controller with DMA Frontgrade Gaisler

SPI Controller Frontgrade Gaisler

Clock gating unit Frontgrade Gaisler

MIL-STD-1553B Interface Frontgrade Gaisler

AHB Status Register Frontgrade Gaisler

Nov 2023, Version 1.0 12

General Purpose I/O port Frontgrade Gaisler

General Purpose Register Frontgrade Gaisler

Temperature sensor Frontgrade Gaisler

General Purpose Register Bank Frontgrade Gaisler

CCSDS TDP / SpaceWire I/F Frontgrade Gaisler

LEON4 Statistics Unit Frontgrade Gaisler

64-bit PC133 SDRAM Controller Frontgrade Gaisler

Use command 'info sys' to print a detailed report of attached cores

grmon3> info sys

ahbjtag0 Frontgrade Gaisler JTAG Debug Link

AHB Master 0

grspw0 Frontgrade Gaisler GRSPW2 SpaceWire Serial Link

AHB Master 1

APB: e4000000 - e4000100

Number of ports: 1

edcl0 Frontgrade Gaisler EDCL master interface

AHB Master 2

edcl1 Frontgrade Gaisler EDCL master interface

AHB Master 3

cpu0 Frontgrade Gaisler LEON4 SPARC V8 Processor

AHB Master 0

cpu1 Frontgrade Gaisler LEON4 SPARC V8 Processor

AHB Master 1

cpu2 Frontgrade Gaisler LEON4 SPARC V8 Processor

AHB Master 2

cpu3 Frontgrade Gaisler LEON4 SPARC V8 Processor

AHB Master 3

iommu0 Frontgrade Gaisler IO Memory Management Unit

AHB Master 4

AHB: ff840000 - ff848000

IRQ: 31

Device index: 0

Protection modes: APV and IOMMU

msts: 11, grps: 8, accsz: 128 bits

APV cache lines: 32, line size: 16 bytes

cached area: 0x00000000 - 0x80000000

IOMMU TLB entries: 32, entry size: 16 bytes

translation mask: 0xff000000

Core has multi-bus support

Core has 4 ASMP register blocks

ahb2ahb0 Frontgrade Gaisler AHB-to-AHB Bridge

AHB Master 5

AHB: 00000000 - 80000000

AHB: 80000000 - c0000000

AHB: c0000000 - e0000000

AHB: f0000000 - 00000000

USR: 00000113

USR: fff00000

l2cache0 Frontgrade Gaisler L2-Cache Controller

AHB Master 0

AHB: 00000000 - 80000000

AHB: f0000000 - f0400000

AHB: ffe00000 - fff00000

USR: 00000114

USR: ffe00000

IRQ: 28

L2C: 4-ways, cachesize: 2048 kbytes, mtrr: 16, FT, AHB SPLIT support

memscrub0 Frontgrade Gaisler AHB Memory Scrubber

AHB Master 1

AHB: ffe01000 - ffe01100

IRQ: 28

burst length: 32 bytes

adev12 Frontgrade Gaisler IOMMU secondary master i/f

AHB Master 2

ahb2ahb1 Frontgrade Gaisler AHB-to-AHB Bridge

AHB Master 0

AHB: 80000000 - c0000000

AHB: c0000000 - d0000000

AHB: d0000000 - e0000000

AHB: ff800000 - ff900000

USR: 00000118

USR: ff800000

dsu0 Frontgrade Gaisler LEON4 Debug Support Unit

AHB: e0000000 - e4000000

AHB trace: 256 lines, 128-bit bus

CPU0: win 8, nwp 4, itrace 512, V8 mul/div, srmmu, lddel 1, GRFPU

, FT

stack pointer 0x0ffffff0

icache 4 * 4 kB, 32 B/line, rnd

dcache 4 * 4 kB, 32 B/line, rnd, snoop tags

CPU1: win 8, nwp 4, itrace 512, V8 mul/div, srmmu, lddel 1, GRFPU

, FT

stack pointer 0x0ffffff0

Nov 2023, Version 1.0 13

icache 4 * 4 kB, 32 B/line, rnd

dcache 4 * 4 kB, 32 B/line, rnd, snoop tags

CPU2: win 8, nwp 4, itrace 512, V8 mul/div, srmmu, lddel 1, GRFPU

, FT

stack pointer 0x0ffffff0

icache 4 * 4 kB, 32 B/line, rnd

dcache 4 * 4 kB, 32 B/line, rnd, snoop tags

CPU3: win 8, nwp 4, itrace 512, V8 mul/div, srmmu, lddel 1, GRFPU

, FT

stack pointer 0x0ffffff0

icache 4 * 4 kB, 32 B/line, rnd

dcache 4 * 4 kB, 32 B/line, rnd, snoop tags

apbmst0 Frontgrade Gaisler AHB/APB Bridge

AHB: e4000000 - e4100000

ahbtrace0 Frontgrade Gaisler AMBA Trace Buffer

AHB: eff00000 - eff20000

Trace buffer size: 128 lines

apbmst1 Frontgrade Gaisler AHB/APB Bridge

AHB: ff900000 - ffa00000

apbmst2 Frontgrade Gaisler AHB/APB Bridge

AHB: ffa00000 - ffb00000

ddrsdmux0 Frontgrade Gaisler Muxed FT DDR/SDRAM controller

AHB: 00000000 - 80000000

AHB: ffe00000 - ffe00100

Backend: sdctrl0

mctrl0 Frontgrade Gaisler Memory controller with EDAC

AHB: c0000000 - d0000000

AHB: d0000000 - e0000000

USR: 00000003

APB: ff903000 - ff903100

8-bit prom @ 0xc0000000

pci0 Frontgrade Gaisler GRPCI2 PCI/AHB bridge

AHB: 80000000 - c0000000

AHB: ff800000 - ff840000

APB: ffa00000 - ffa00100

IRQ: 11

Trace buffer size: 256 lines

spwrtr0 Frontgrade Gaisler GRSPW Router

AHB: ff880000 - ff882000

IRQ: 31

Instance id: 17

SpW ports: 8 AMBA ports: 4 FIFO ports: 0

l4stat0 Frontgrade Gaisler LEON4 Statistics Unit

APB: e4000200 - e4000400

Device is disabled

pcitrace0 Frontgrade Gaisler GRPCI2 Trace buffer

APB: e4040000 - e4080000

Trace buffer size: 256 lines

uart0 Frontgrade Gaisler Generic UART

APB: ff900000 - ff900100

IRQ: 29

Baudrate 38390, FIFO debug mode available

uart1 Frontgrade Gaisler Generic UART

APB: ff901000 - ff901100

IRQ: 30

Baudrate 38390, Loop-back mode available

gpio0 Frontgrade Gaisler General Purpose I/O port

APB: ff902000 - ff902100

IRQ: 16

irqmp0 Frontgrade Gaisler Multi-processor Interrupt Ctrl.

APB: ff904000 - ff908000

EIRQ: 10

gptimer0 Frontgrade Gaisler Modular Timer Unit

APB: ff908000 - ff908100

IRQ: 1

16-bit scalar, 5 * 32-bit timers, divisor 250

gptimer1 Frontgrade Gaisler Modular Timer Unit

APB: ff909000 - ff909100

IRQ: 6

16-bit scalar, 4 * 32-bit timers, divisor 250

gptimer2 Frontgrade Gaisler Modular Timer Unit

APB: ff90a000 - ff90a100

IRQ: 7

16-bit scalar, 4 * 32-bit timers, divisor 250

gptimer3 Frontgrade Gaisler Modular Timer Unit

APB: ff90b000 - ff90b100

IRQ: 8

16-bit scalar, 4 * 32-bit timers, divisor 250

gptimer4 Frontgrade Gaisler Modular Timer Unit

APB: ff90c000 - ff90c100

IRQ: 9

16-bit scalar, 4 * 32-bit timers, divisor 250

grspw1 Frontgrade Gaisler GRSPW Router DMA interface

APB: ff90d000 - ff90e000

IRQ: 20

Nov 2023, Version 1.0 14

Number of ports: 1

grspw2 Frontgrade Gaisler GRSPW Router DMA interface

APB: ff90e000 - ff90f000

IRQ: 21

Number of ports: 1

grspw3 Frontgrade Gaisler GRSPW Router DMA interface

APB: ff90f000 - ff910000

IRQ: 22

Number of ports: 1

grspw4 Frontgrade Gaisler GRSPW Router DMA interface

APB: ff910000 - ff911000

IRQ: 23

Number of ports: 1

greth0 Frontgrade Gaisler GR Ethernet MAC

APB: ff940000 - ff940100

IRQ: 24

1000 Mbit capable

edcl ip 192.168.0.24, buffer 2 kbyte

greth1 Frontgrade Gaisler GR Ethernet MAC

APB: ff980000 - ff980100

IRQ: 25

Device is disabled

grcan0 Frontgrade Gaisler CAN Controller with DMA

APB: ffa01000 - ffa01400

IRQ: 16

Device is disabled

grcan1 Frontgrade Gaisler CAN Controller with DMA

APB: ffa02000 - ffa02400

IRQ: 16

Device is disabled

spi0 Frontgrade Gaisler SPI Controller

APB: ffa03000 - ffa03100

IRQ: 19

Device is disabled

grcg0 Frontgrade Gaisler Clock gating unit

APB: ffa04000 - ffa04100

GRMON did NOT enable clocks during initialization

gr1553b0 Frontgrade Gaisler MIL-STD-1553B Interface

APB: ffa05000 - ffa05100

IRQ: 26

Device is disabled

ahbstat0 Frontgrade Gaisler AHB Status Register

APB: ffa06000 - ffa06100

IRQ: 27

ahbstat1 Frontgrade Gaisler AHB Status Register

APB: ffa07000 - ffa07100

IRQ: 27

gpio1 Frontgrade Gaisler General Purpose I/O port

APB: ffa08000 - ffa08100

IRQ: 16

gpreg0 Frontgrade Gaisler General Purpose Register

APB: ffa09000 - ffa09100

temp0 Frontgrade Gaisler Temperature sensor

APB: ffa0a000 - ffa0a100

gpreg1 Frontgrade Gaisler General Purpose Register Bank

APB: ffa0b000 - ffa0b100

spwtdp0 Frontgrade Gaisler CCSDS TDP / SpaceWire I/F

APB: ffa0c000 - ffa0c200

IRQ: 31

l4stat1 Frontgrade Gaisler LEON4 Statistics Unit

APB: ffa0d000 - ffa0d200

Device is disabled

sdctrl0 Frontgrade Gaisler 64-bit PC133 SDRAM Controller

AHB: 00000000 - 80000000

AHB: ffe00000 - ffe00100

32-bit sdram: 2 * 128 Mbyte @ 0x00000000,

col 10, cas 2, ref 1.6 us

5.6.2. CertusPro

Please see Chapter 6 for the output corresponding the FPGA design.

Nov 2023, Version 1.0 15

6. Examples Bitstreams

6.1. Overview

For the GR740-MINI board, there will be example bitstream(s) uploaded for end-user to easily interact with the

hardware. The bitstreams are based on an architecture centered around the AMBA Advanced High-speed Bus

(AHB),towhichhigh-bandwidthunitsareconnected.Low-bandwidthunitsareconnectedtotheAMBAAdvanced

Peripheral Bus (APB) which is accessed through an AHB to APB bridge.

The bitstreams are available on the webpage www.gaisler.com/gr740-mini

6.2. Cores and Memory Map

In this section we present the different bistreams configuration how the cores are instantiated in the design with

their AHB/APB memory mapping and interrupt. For more information on the operations of each individual core,

please refer to the grip documentation; available at GRLIB IP Core User’s Manual xml:id="ref.grip_um"

6.2.1. ex-1

using port /dev/ttyUSB3 @ 115200 baud

Device ID: 0x801

GRLIB build version: 4283

Detected frequency: 50.0 MHz

Component Vendor

AHB Debug UART Frontgrade Gaisler

GR Ethernet MAC Frontgrade Gaisler

GRPCI2 PCI/AHB bridge Frontgrade Gaisler

GRSPW2 SpaceWire Serial Link Frontgrade Gaisler

AHB/APB Bridge Frontgrade Gaisler

SPI Memory Controller Frontgrade Gaisler

Single-port AHB SRAM module Frontgrade Gaisler

Generic UART Frontgrade Gaisler

Modular Timer Unit Frontgrade Gaisler

Use command 'info sys' to print a detailed report of attached cores

grmon3> info sys

ahbuart0 Frontgrade Gaisler AHB Debug UART

AHB Master 0

APB: 80000400 - 80000500

Baudrate 115200, AHB frequency 50.00 MHz

greth0 Frontgrade Gaisler GR Ethernet MAC

AHB Master 1

APB: 80001100 - 80001200

IRQ: 12

1000 Mbit capable

edcl ip 192.168.0.51, buffer 16 kbyte

pci0 Frontgrade Gaisler GRPCI2 PCI/AHB bridge

AHB Master 2

APB: 80000500 - 80000600

grspw0 Frontgrade Gaisler GRSPW2 SpaceWire Serial Link

AHB Master 3

APB: 80000900 - 80000a00

IRQ: 3

Number of ports: 1

grspw1 Frontgrade Gaisler GRSPW2 SpaceWire Serial Link

AHB Master 4

APB: 80000a00 - 80000b00

IRQ: 4

Number of ports: 1

grspw2 Frontgrade Gaisler GRSPW2 SpaceWire Serial Link

AHB Master 5

APB: 80000b00 - 80000c00

IRQ: 5

Number of ports: 1

grspw3 Frontgrade Gaisler GRSPW2 SpaceWire Serial Link

AHB Master 6

APB: 80000c00 - 80000d00

IRQ: 6

Number of ports: 1

apbmst0 Frontgrade Gaisler AHB/APB Bridge

Nov 2023, Version 1.0 16

AHB: 80000000 - 80100000

spim0 Frontgrade Gaisler SPI Memory Controller

AHB: fff00000 - fff00100

AHB: 00000000 - 01000000

IRQ: 10

SPI memory device read command: 0x3b

ahbram0 Frontgrade Gaisler Single-port AHB SRAM module

AHB: 40000000 - 40100000

32-bit SRAM: 128 kB @ 0x40000000

uart0 Frontgrade Gaisler Generic UART

APB: 80000100 - 80000200

IRQ: 2

Baudrate 38343, FIFO debug mode available

gptimer0 Frontgrade Gaisler Modular Timer Unit

APB: 80000300 - 80000400

IRQ: 8

16-bit scalar, 2 * 32-bit timers, divisor 50

Nov 2023, Version 1.0 17

7. Support

For support contact the Frontgrade Gaisler support team at [email protected].

When contacting support, please identify yourself in full, including company affiliation and site name and address.

Please identify exactly what product that is used, specifying if it is an IP core (with full name of the library

distribution archive file), component, software version, compiler version, operating system version, debug tool

version, simulator tool version, board version, etc.

There is also an open forum available at https://grlib.community.

Nov 2023, Version 1.0 18

Frontgrade Gaisler AB

Kungsgatan 12

411 19 Göteborg

Sweden

frontgrade.com/gaisler

[email protected]

T: +46 31 7758650

F: +46 31 421407

Frontgrade Gaisler AB, reserves the right to make changes to any products and services described herein at any time without

notice. Consult the company or an authorized sales representative to verify that the information in this document is current before

using this product. The company does not assume any responsibility or liability arising out of the application or use of any product

or service described herein, except as expressly agreed to in writing by the company; nor does the purchase, lease, or use of

a product or service from the company convey a license under any patent rights, copyrights, trademark rights, or any other of

the intellectual rights of the company or of third parties. All information is provided as is. There is no warranty that it is correct or

suitable for any purpose, neither implicit nor explicit.

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