FRONTGRADE GR740-MINI User manual

Quick start guide for GR740-MINI Evaluation board
GR740-MINI
GR740-MINI Quick Start Guide
USER MANUAL
RELEASED NOVEMBER 2023
GR740-MINI-QSG Frontgrade Gaisler AB | Kungsgatan 12 | SE-411 19 | Göteborg | Sweden | frontgrade.com/gaisler
Nov 2023, Version 1.0

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Nov 2023, Version 1.0 2
Table of Contents
1. Introduction .......................................................................................................................... 3
1.1. Overview ................................................................................................................... 3
1.2. IP addresses ............................................................................................................... 3
1.3. Handling .................................................................................................................... 3
1.4. References .................................................................................................................. 3
2. Overview .............................................................................................................................. 4
3. Board Configuration ............................................................................................................... 5
3.1. Overview ................................................................................................................... 5
3.2. Power Up the board ..................................................................................................... 5
3.3. LED power indication .................................................................................................. 5
3.4. Switch buttons ............................................................................................................ 6
3.4.1. Master reset (SW1) ........................................................................................... 6
3.4.2. Program switch (SW2) ....................................................................................... 6
3.5. FTDI chip .................................................................................................................. 6
4. FPGA development Environment .............................................................................................. 7
4.1. Lattice Radiant Software ............................................................................................... 7
4.2. Program the FPGA ...................................................................................................... 7
4.2.1. Lattice programmer ........................................................................................... 7
4.2.2. GRMON3 ........................................................................................................ 7
5. GRMON3 hardware debugger .................................................................................................. 9
5.1. Overview ................................................................................................................... 9
5.2. GR740 License options ................................................................................................ 9
5.3. Debug-link alternatives for GR740 ................................................................................. 9
5.3.1. Connecting via the FTDI USB/JTAG interface ....................................................... 9
5.3.2. Connecting via the Ethernet debug interfaces ......................................................... 9
5.4. Debug-link alternatives for CertusPro ............................................................................ 10
5.4.1. Connecting via the FTDI USB/UART interface .................................................... 10
5.4.2. Connecting via the Ethernet debug interfaces ........................................................ 10
5.5. First steps ................................................................................................................. 10
5.6. Connecting to the board .............................................................................................. 11
5.6.1. GR740 ........................................................................................................... 11
5.6.2. CertusPro ....................................................................................................... 14
6. Examples Bitstreams ............................................................................................................. 15
6.1. Overview .................................................................................................................. 15
6.2. Cores and Memory Map ............................................................................................. 15
6.2.1. ex-1 .............................................................................................................. 15
7. Support ............................................................................................................................... 17

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Nov 2023, Version 1.0 3
1. Introduction
1.1. Overview
This document is a quick start guide for the GR740-MINI Development Board.
The purpose of this document is to get users quickly started using the board.
For a complete description of the board please refer to the GR740-MINI Board User's Manual
The GR740 system-on-chip is described in the GR740 Data Sheet and User’s Manual.
The CertusPro FPGA is described in the CertusPro-NX Family Data Sheet.
This quick start guide does not contain as many technical details and is instead how-to oriented. However, to make
the most of the guide the user should have glanced through the aforementioned documents and should ideally also
be familiar with the GRMON debug monitor.
1.2. IP addresses
The GR740-MINI board is equipped with two Ethernet ports that have default IP addresses 192.168.0.24 and
192.168.0.51. The GR740-MINI should not be connected to an existing network where these addresses may be
already occupied. Please see Chapter 5 before conneceting to the network or for more information.
1.3. Handling
This unit contains sensitive electronic components which can be damaged by Electrostatic Discharges (ESD).
When handling or installing the unit observe appropriate precautions and ESD safe practices.
When not in use, store the unit in an electrostatic protective container or bag.
When connecting/disconnecting cables, ensure that the unit is in an un-powered state.
This equipment has SpW ports that use Low Voltage Differential Signalling (LVDS) which has limited common
mode voltage protection. Please refer to the user’s manual for instructions on how to ensure that the grounds of
equipment are connected together when using SpaceWire.
1.4. References
Table 1.1. References
RD-1 GR740-MINI User’s Manual [https://gaisler.com/index.php/products/boards/gr740-mini]
RD-2 GR740 Data Sheet and User’s Manual [https://gaisler.com/gr740]
RD-3 CertusPro-NX Family Data Sheet [https://www.latticesemi.com/Products/FPGAandC-
PLD/CertusPro-NX]
RD-4 GRMON User's Manual [https://www.gaisler.com/doc/grmon3.pdf]
RD-14 GRLIB IP Core User’s Manual [https://www.gaisler.com/products/grlib/grip.pdf]

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2. Overview
The GR740-MINI board is a compact evaluation platform built around the Frontgrade GR740 quad-core
LEON4FT SPARC V8 processor and Lattice Semiconductor FPGA CertusPro-NX, shown in Figure 2.1.
Figure 2.1. Top view of GR740-MINI board
The GR740-MINI architecture includes the following modules:
• 2 x USB-C connectors for debug and power
• GR470 Processor
• 1 x USB interface via FTDI FT4232 providing JTAG and UART
• 1 x Ethernet for communication and debug
• 4 x SpaceWire channels to FMC+ connector
• 256MiB SDRAM
• 128MiB FLASH
• CertusPro-NX FPGA
• 1 x USB interface via FTDI FT4232 providing JTAG and UART
• 1 x Ethernet for communication and debug
• 4 x SerDes to FMC+ connector
• LVDS to FMC+ connector
• 3V3 IO to FMC+ connector
• I2C link to FMC+ connector
• 1GiB DDR3 memory
• 512Mib SPI FLASH
• Intercommunication between GR740 and CertusPro-NX
• PCI link 32bit 33MHz
• GMII/MII
• 4 x SpaceWire channels

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3. Board Configuration
3.1. Overview
The primary sources of information for the development board is the GR740-MINI User’s Manual. The primary
information for the Processor is GR740 Data Sheet and User’s Manual and for the FPGA CertusPro-NX Family
Data Sheet
3.2. Power Up the board
The GR740-MINI board is powered using either of the USB-C connectors (J1 or J2). Therefor there are two ways
to power up the board and is accomplished by attaching a 2-pin jumper to the 3-pin head (JP5), see Figure 3.1.
The overall power requirement for the board is 15W. Note that both the UCB-C cable and source must deliver
at least 3A, 5V (15W). Observe that not all sources with USB-C sockets support that. Check the sources manual
before connecting to the GR740-MINI board.
J2 is considered as the main power supply, and the configuration jumper is set to this as default JP5: 1-2 mode
(blue). This mode can be used when communicating with USB-C (data and power through the same cable), Eth-
ernet or FMC+ connector.
If J2 is connected to a source that cannot provide the minimum power requirement (for example a computer or a
docking station), then J1 can be connected to a external power source. Set jumper JP5 to 2-3 (red) mode to use
J1 as the power source.
Figure 3.1. Jumper configuration for power supply
3.3. LED power indication
When powering the board there are 3 LED for indicating the availability and communication status see Figure 3.2.
• LED1 Indicates that 3V3 is available
• LED2 Light when USB is in suspended mode
• LED3 Indicate normal USB operational mode

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Figure 3.2. Led indication for power
3.4. Switch buttons
3.4.1. Master reset (SW1)
There is switch button (SW1) to reset the board. The reset signal will reset the GR740, the Ethernet PHYs, flash
memory (GR740) and the FPGA user design. It will not trigger an FPGA reconfiguration or interrupt USB com-
munication
3.4.2. Program switch (SW2)
This switch is connected to the FPGA and will initiate configuration sequence when asserted.
3.5. FTDI chip
A FTDI FT4323HP chip is connected to USB-C connector J2 and provides Serial to USB conversion up to 4 ports.
In Table 3.1 the port are listed. The corresponing "vendor id" is 0403 and "product id" is 6043 for the FTDI chip.
Table 3.1. FTDI port assignment
Port Function Target
A JTAG GR740
B JTAG CertusPro-NX
C UART GR740
D UART CertusPro-NX

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4. FPGA development Environment
4.1. Lattice Radiant Software
Lattics provides a software development tool for the FPGA development. Lattice Radiant software is available for
both linux and windows enviorment. Can be downloaded from https://www.latticesemi.com/latticeradiant
4.2. Program the FPGA
The FPGA can be programmed in the volatile (RAM) memory or non-volatile (SPI flash) memory. The FPGA is
programmed with JTAG through the FTDI chip.
4.2.1. Lattice programmer
TBC
4.2.2. GRMON3
GRMON3 can be used to program the FPGA in both linux and windows enviorment, see sections below for
prerequisites. Note that GRMON version 3.3.6 or higher is needed.
In order to program the FPGA using GRMON3 it is needed to connect the debuglink to GR740 via JTAG, please
se section Section 5.3.1 for how to connect. In GRMON3, the following command is used to program the RAM
grmon3> fpgaload ex-1.bit
write to ram
Jtag frequency : requested 1.00MHzOpen file: DONE
Parse file: DONE
Enable configuration: DONE
SRAM erase: DONE
Loading: [==================================================] 100.00%
Done
Disable configuration: DONE
4.2.2.1. Linux prerequisites
Prerequisites: the following programs needs to be installed:
• libusb-1.0
• libftdi1
• libudev
• libhidapi-hidraw
• libz
• glibc-2.29 or higher
• libstdc++.so.x.x.21 or higher
4.2.2.2. Windows prerequisites
To be able to program the FPGA you must replace the driver for the FT4232 interface connected to FPGA. The
tool Zadig can be used for this purpose and can be downloaded from https://zadig.akeo.ie/ . Start Zadig and click
on "Options" and enable "List All Devices" from the drop-down menu. Select GR740-MINI (Interface 1) and set
the driver to WinUSB as in Figure 4.1. Click on "Replace Driver"

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Figure 4.1. Zadig interface

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5. GRMON3 hardware debugger
5.1. Overview
GRMON3 is a debug monitor used to develop and debug GRLIB/LEON systems. The target system, including
the processor and peripherals, is accessed on the AHB bus through a debug-link connected to the host computer.
GRMON3 has GDB support which makes C/C++ level debugging possible by connecting GDB to the GRMON3's
GDB socket. With GRMON3 one can for example:
• Inspect LEON and peripheral registers
• Upload applications to RAM with the load command.
• Program the FLASH with the flash command.
• Control execution flow by starting applications (run), continue execution (cont), single-stepping (step), in-
serting breakpoints/watchpoints (bp) etc.
• Inspect the current CPU state listing the back-trace, instruction trace and disassemble machine code.
The first step is to set up a debug link in order to connect to the board. The following section outlines which
debug interfaces are available and how to use them on the GR740-MINI Evaluation Board. After that, a basic first
inspection of the board is exemplified.
5.2. GR740 License options
The GRMON3 evaluation version which is freely available can be used to operate the GR740-MINI board. The
evaluation version does not support any other GR740 boards. The evaluation version is limited in certain regards
compared with the GRMON3 professional product. GRMON3 can be downloaded from the GRMON3 homepage
[RD-4].
The following table summarizes the GRMON3 license options for GR740.
Table 5.1. GRMON3 license options for GR740. All references to GRMON3 is for version 3.3.6 or later.
Program version License Supported hardware
GRMON3 professional Professional • All GR740 systems
• All LEON/GRLIB systems
GRMON3 evaluation Evaluation (21 days free)
• No cost
• No registration
• GR740-MINI
5.3. Debug-link alternatives for GR740
5.3.1. Connecting via the FTDI USB/JTAG interface
Please see GRMON User's Manual for how to set up the required FTDI driver software.
Due to the SDRAM configuration on the board the -sddcs flag must be set. -jtagserial is used to connect to the
board, where xxx is the serialnumber of the board. Connect the PC to the board by using a USB cable to the J2
connector and issue the following command:
grmon -ftdi -jtagserial GR740M0xxxA -sddcs
5.3.2. Connecting via the Ethernet debug interfaces
Note: Debugging using Ethernet is not supported by grmon-eval
The GR740 supports one Ethernet debug communication link (EDCL) in the default configuration of the GR740-
MINI. The debug link have default address 192.168.0.24. The GR740-MINI should not be connected to an existing
network where this address may be already occupied.
If another address is wanted for the Ethernet debug link then one of the other debug links must be used to connect
GRMON3 to the board. The EDCL IP address can then be changed using GRMON3's edcl command. This new
address will persist until next system reset.

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Ethernet debug link traffic is routed to the Debug AHB bus as default. Ethernet debug link traffic can be routed
either to the Master I/O AHB bus or to the Debug AHB bus by changing a bootstrap signal. In order to control
the LEON processors the debug link must be routed to the Debug AHB bus, otherwise GRMON3 will not be able
to use the debug link to access the Debug Support Unit.
After reset the Ethernet debug communication link will attempt to configure the Ethernet PHY. In order for this
to succeed, the Ethernet port must be connected to a switch or other networking equipment.
Connect the Ethernet to connector J3B. Due to the SDRAM configuration on the board the -sddcs flag must be
set. Issue the following command:
grmon -eth 192.168.0.24 -sddcs
5.4. Debug-link alternatives for CertusPro
The interfaces to debug the CertusPro can vary depening on how the FPGA is programmed. In this chapter the
interfaces that will be provided from our pre-built bitsreams will be described.
5.4.1. Connecting via the FTDI USB/UART interface
Please see GRMON User's Manual for instructions how to connect GRMON3 to a board using a serial UART
connection. The PC is connected using a USB cable to the USB connector J2 and then start GRMON3 with the
-uart PORTNAME debug-link option and device name.
Example in Linux:
grmon -uart /dev/ttyUSB3
Example in Windows:
grmon -uart \\.\COM6
5.4.2. Connecting via the Ethernet debug interfaces
Note: Debugging using Ethernet is not supported by grmon-eval
Ethernet debug communication link (EDCL) have default address 192.168.0.51 The GR740-MINI should not be
connected to an existing network where these addresses may be already occupied.
If another address is wanted for the Ethernet debug link then one of the other debug links must be used to connect
GRMON3 to the board. The EDCL IP address can then be changed using GRMON3's edcl command. This new
address will persist until next system reset.
The Ethernet debug link traffic is routed to the Debug AHB bus.
After reset the first Ethernet debug communication link will attempt to configure the Ethernet PHY. In order for
this to succeed, the Ethernet port must be connected to a switch or other networking equipment. Connect the
Ethernet to connector J3A and issue the following command:
grmon -eth 192.168.0.51
5.5. First steps
The previous sections have described which debug-links are available and how to start using them with GRMON3.
The subsections below assume that GRMON3, the host computer and the GR740-MINI board have been set up
so that GRMON3 can connect to the board.
When connecting to the board for the first time it is recommended to get to know the system by inspecting the
current configuration and hardware present using GRMON3. With the info sys command more details about the
system is printed and with info reg the register contents of the I/O registers can be inspected. Below is a list of
items of particular interest:
• AMBA system frequency is printed out at connect, if the frequency is wrong then it might be due to noise in
auto detection (small error). See -freq flag in the GRMON User's Manual [RD-4].
• Memory location and size configuration is found from the info sys output.