FTDI FT51A Installation and operating instructions

Use of FTDI devices in life support and/or safety applications is entirely at the user’s risk, and the
user agrees to defend, indemnify and hold FTDI harmless from any and all damages, claims, suits
or expense resulting from such use.
Future Technology Devices International Limited (FTDI)
Unit 1, 2 Seaward Place, Glasgow G41 1HH, United Kingdom
Tel.: [phone] Fax: + 44 (0) 141 429 2758
Web Site: http://ftdichip.com
Copyright © 2015 Future Technology Devices International Limited
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FT51A Programming Guide
Version 1.0
Issue Date: 2015-12-21
This document provides a guide for using FT51A firmware libraries supplied
by FTDI and writing applications.

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Table of Contents
1Introduction .............................................................. 7
1.1 Overview .............................................................................7
1.2 Features ..............................................................................7
1.3 Scope ..................................................................................7
2Hardware Reference .................................................. 9
2.1 Hardware Access...............................................................10
2.1.1 Registers Accessed by SFR............................................................................. 10
2.1.2 Registers Accessed through I/O Ports.............................................................. 10
2.1.3 Register Descriptions .................................................................................... 11
2.2 Device Control Registers ...................................................12
2.2.1 DEVICE_CONTROL_REGISTER ........................................................................ 13
2.2.2 SYSTEM_CLOCK_DIVIDER ............................................................................. 14
2.2.3 TOP_USB_ENABLE ........................................................................................ 16
2.2.4 PERIPHERAL_INT0 ........................................................................................ 17
2.2.5 PERIPHERAL_IEN0 ........................................................................................ 17
2.2.6 PERIPHERAL_INT1 ........................................................................................ 18
2.2.7 PERIPHERAL_IEN1 ........................................................................................ 19
2.2.8 PIN_CONFIG ................................................................................................ 19
2.2.9 MTP_CONTROL ............................................................................................. 19
2.2.10 MTP_ADDR_L, MTP_ADDR_U and MTP_PROG_DATA.......................................... 20
2.2.11 MTP_CRC_CTRL, MTP_CRC_RESULT_L and MTP_CRC_RESULT_U........................ 21
2.2.12 PIN_PACKAGE_CONFIG ................................................................................. 22
2.2.13 TOP_ SECURITY_LEVEL ................................................................................. 22
2.3 SPI Master.........................................................................25
2.3.1 SPI_MASTER_CONTROL................................................................................. 27
2.3.2 SPI_MASTER_TX_DATA ................................................................................. 27
2.3.3 SPI_MASTER_RX_DATA ................................................................................. 27
2.3.4 SPI_MASTER_IEN ......................................................................................... 28
2.3.5 SPI_MASTER_INT ......................................................................................... 29
2.3.6 SPI_MASTER_SETUP ..................................................................................... 30
2.3.7 SPI_MASTER_CLK_DIV.................................................................................. 31

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2.3.8 SPI_MASTER_DATA_DELAY............................................................................ 31
2.3.9 SPI_MASTER_SS_SETUP ............................................................................... 32
2.3.10 SPI_MASTER_TRANSFER_SIZE ....................................................................... 32
2.3.11 SPI_MASTER_TRANSFER_PENDING................................................................. 33
2.3.12 Use Cases.................................................................................................... 33
2.4 SPI Slave...........................................................................36
2.4.1 SPI_SLAVE_CONTROL ................................................................................... 37
2.4.2 SPI_SLAVE_TX_DATA.................................................................................... 37
2.4.3 SPI_SLAVE_RX_DATA ................................................................................... 38
2.4.4 SPI_SLAVE_IEN............................................................................................ 38
2.4.5 SPI_SLAVE_INT............................................................................................ 39
2.4.6 SPI_SLAVE_SETUP........................................................................................ 40
2.5 I2C Master.........................................................................41
2.5.1 I2CMSA ....................................................................................................... 41
2.5.2 I2CMCR ....................................................................................................... 42
2.5.3 I2CMSR ....................................................................................................... 43
2.5.4 I2CMBUF ..................................................................................................... 43
2.5.5 I2CMTP ....................................................................................................... 44
2.5.6 Use Case ..................................................................................................... 44
2.6 I2C Slave...........................................................................47
2.6.1 I2CSOA ....................................................................................................... 47
2.6.2 I2CSCR ....................................................................................................... 48
2.6.3 I2CSSR ....................................................................................................... 48
2.6.4 I2CSBUF...................................................................................................... 49
2.6.5 Use Case ..................................................................................................... 49
2.7 UART .................................................................................51
2.7.1 UART_CONTROL ........................................................................................... 52
2.7.2 UART_DMA_CTRL ......................................................................................... 52
2.7.3 UART_RX_DATA ........................................................................................... 52
2.7.4 UART_TX_DATA............................................................................................ 52
2.7.5 UART_TX_IEN .............................................................................................. 53
2.7.6 UART_TX_INT .............................................................................................. 53
2.7.7 UART_RX_IEN .............................................................................................. 54
2.7.8 UART_RX_INT .............................................................................................. 54
2.7.9 UART_LINE_CTRL ......................................................................................... 55

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2.7.10 UART_BAUD................................................................................................. 56
2.7.11 UART Baud Rate Example .............................................................................. 57
2.7.12 UART_FLOW_CTRL........................................................................................ 57
2.7.13 UART_FLOW_STAT........................................................................................ 58
2.8 GPIOs................................................................................59
2.8.1 Digital GPIO Pads ......................................................................................... 59
2.8.2 Analogue GPIO Pads ..................................................................................... 60
2.9 IOMUX...............................................................................63
2.9.1 IOMUX_CONTROL ......................................................................................... 63
2.9.2 IOMUX_OUTPUT_PAD_SEL............................................................................. 64
2.9.3 IOMUX_OUTPUT_SIG_SEL ............................................................................. 64
2.9.4 IOMUX_INPUT_SIG_SEL ................................................................................ 64
2.9.5 IOMUX_INPUT_PAD_SEL ............................................................................... 65
2.9.6 IOMUX Pad Values ........................................................................................ 65
2.9.7 IOMUX Output Signal Mapping Values ............................................................. 66
2.9.8 IOMUX Input Signal Mapping Values ............................................................... 68
2.9.9 Use Cases.................................................................................................... 69
2.10 Analogue IO Ports...........................................................70
2.10.1 AIO_CONTROL ............................................................................................. 70
2.10.2 Implementation............................................................................................ 71
2.10.3 AIO Configuration ......................................................................................... 71
2.10.4 AIO ADC Mode ............................................................................................. 74
2.10.5 AIO Interrupts.............................................................................................. 77
2.10.6 Global Mode................................................................................................. 79
2.10.7 Differential Mode .......................................................................................... 82
2.10.8 Settling Times .............................................................................................. 83
2.10.9 ADC Programming Flow ................................................................................. 86
2.11 USB Full Speed Device Controller....................................87
2.11.1 Endpoint Buffer Management ......................................................................... 87
2.11.2 Command Summary ..................................................................................... 91
2.11.3 Initialization Commands ................................................................................ 96
2.11.4 Data Flow Commands ................................................................................... 99
2.11.5 General Commands .....................................................................................105
2.12 Pulse Width Modulation ................................................106

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2.12.1 PWM_CONTROL ...........................................................................................108
2.12.2 PWM_INT_CTRL...........................................................................................109
2.12.3 PWM_PRESCALER ........................................................................................109
2.12.4 PWM_CNT16_LSB ........................................................................................109
2.12.5 PWM_CNT16_MSB .......................................................................................110
2.12.6 PWM_CMP16_0_LSB - PWM_CMP16_7_LSB ....................................................110
2.12.7 PWM_CMP16_0_MSB - PWM_CMP16_7_MSB...................................................110
2.12.8 PWM_OUT_TOGGLE_EN_0 - PWM_OUT_TOGGLE_EN_7 ....................................110
2.12.9 PWM_OUT_CLR_EN......................................................................................111
2.12.10 PWM_CTRL_BL_CMP8 ...............................................................................111
2.12.11 PWM_INIT ...............................................................................................111
2.12.12 Use Cases ...............................................................................................111
2.13 Timers ..........................................................................115
2.13.1 TIMER_CONTROL.........................................................................................116
2.13.2 TIMER_CONTROL_1 .....................................................................................117
2.13.3 TIMER_CONTROL_2 .....................................................................................117
2.13.4 TIMER_CONTROL_3 .....................................................................................117
2.13.5 TIMER_CONTROL_4 .....................................................................................118
2.13.6 TIMER_INT .................................................................................................118
2.13.7 TIMER_SELECT............................................................................................119
2.13.8 TIMER_WDG ...............................................................................................119
2.13.9 TIMER_WRITE_LS........................................................................................119
2.13.10 TIMER_WRITE_MS....................................................................................119
2.13.11 TIMER_PRESC_LS ....................................................................................119
2.13.12 TIMER_PRESC_MS....................................................................................120
2.13.13 TIMER_READ_LS ......................................................................................120
2.13.14 TIMER_READ_MS .....................................................................................120
2.13.15 Use Cases ...............................................................................................121
2.14 DMA ..............................................................................127
2.14.1 DMA_CONTROL_x........................................................................................130
2.14.2 DMA_ENABLE_x ..........................................................................................131
2.14.3 DMA_IRQ_ENA_x.........................................................................................131
2.14.4 DMA_IRQ_x ................................................................................................132
2.14.5 DMA_SRC_MEM_ADDR_L_x ..........................................................................132
2.14.6 DMA_SRC_MEM_ADDR_U_x..........................................................................132

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2.14.7 DMA_DEST_MEM_ADDR_L_x ........................................................................132
2.14.8 DMA_DEST_MEM_ADDR_U_x ........................................................................133
2.14.9 DMA_IO_ADDR_L_x.....................................................................................133
2.14.10 DMA_SRC_MEM_ADDR_U_x ......................................................................133
2.14.11 DMA_TRANS_CNT_L_x..............................................................................134
2.14.12 DMA_TRANS_CNT_U_x .............................................................................134
2.14.13 DMA_CURR_CNT_L_x ...............................................................................134
2.14.14 DMA_TRANS_CNT_U_x .............................................................................134
2.14.15 DMA_FIFO_DATA_x ..................................................................................134
2.14.16 DMA_AFULL_TRIGGER_x...........................................................................135
2.14.17 Use Cases ...............................................................................................135
3Application Guide .................................................. 137
3.1 Libraries ..........................................................................137
3.1.1 Configuration Library ...................................................................................137
3.1.2 USB Library ................................................................................................138
3.1.3 DMA Library ................................................................................................141
3.1.4 UART Library...............................................................................................142
3.1.5 SPI Master Library .......................................................................................143
3.1.6 I2C Master Library .......................................................................................144
3.1.7 I2C Slave Library.........................................................................................145
3.1.8 AIO Library .................................................................................................145
3.1.9 IOMUX Library.............................................................................................146
3.1.10 Watchdog Library ........................................................................................146
3.1.11 DFU Library ................................................................................................147
3.1.12 LCD Library.................................................................................................148
3.1.13 TMC Library ................................................................................................148
3.2 USB Applications .............................................................150
3.2.1 Initialising USB Device .................................................................................150
3.2.2 Descriptors .................................................................................................151
3.2.3 Standard Requests ......................................................................................153
3.2.4 Class and Vendor Requests ...........................................................................157
3.2.5 Call-backs...................................................................................................157
3.2.6 Main Function..............................................................................................158
3.2.7 Sending and Receiving Data..........................................................................159
3.2.8 Link Power Management...............................................................................159

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4Contact Information .............................................. 161
Appendix A –References ........................................... 162
Document References .............................................................162
Acronyms and Abbreviations...................................................163
Appendix B –List of Tables & Figures ........................ 164
List of Tables...........................................................................164
List of Figures .........................................................................168
Appendix C –Revision History ................................... 170

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1Introduction
This guide documents the registers and internal architecture of the FT51A. It also covers the
firmware libraries and samples provided for the FT51A by FTDI.
1.1 Overview
The FT51A series of devices provides a USB device interface, a built-in USB hub and an 8051
compatible microcontroller. The 8051 compatible component is referred to as the ‘core’.
There is 16kB of program storage in MTP (Multiple Time Programmable) memory, 16kB of Shadow
RAM (from where code is run), 8kB of data RAM and 128 bytes of internal RAM.
Details of the device are fully documented in the FT51A Series Datasheets which can be obtained
from the FTDI website. http://www.ftdichip.com/Products/ICs/FT51.html.
Additionally there are the following hardware interfaces:
-GPIO
-UART
-PWM
-SPI Master and Slave
-I2C Master and Slave
-FT245 Parallel
-ADC
-Additional Timers
The FT51A has an internal USB Full Speed device controller that is register compatible with an
FT122. An internal on-chip USB hub can optionally be enabled to allow a single downstream port
from the FT51A.
1.2 Features
The firmware libraries for the FT51A have the following features:
-Abstracted access to USB functions for simple implementation of device emulation.
-Functions for performing basic access to ADC, SPI Master, I2C Master, I2C Slave and UART
hardware interfaces.
-Macros and definitions for hardware related features.
-Additional libraries for LCD devices, DFU (Device Firmware Update), TMC (Test and
Measurement).
The use of the firmware libraries is shown in the sample applications:
-DFU Firmware update,
-Keyboard and Mouse demos,
-Test and Measurement Class,
-Interfacing to FT800 demos,
-Interfacing to LCD screen.
1.3 Scope
This guide is intended for developers who are creating applications, extending FTDI provided
applications or implementing example applications for the FT51A.
In the reference of the FT51A, an “application” refers to firmware that runs on the FT51A;
“libraries” are source code provided by FTDI to help users access specific hardware features of the
chip.

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The FT51A Tools are currently only available for Microsoft Windows, and are tested on Windows 7
and Windows 8.1.
The following diagram shows the overall system structure:

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2Hardware Reference
The FT51A has an 8051 compatible core. There are extended Special Function Registers (SFRs) to
enable access to the registers of all the peripherals and modules. Certain registers are accessed
directly through SFRs and others are accessed through I/O ports addressed though SFRs.
The SFR map is shown in Table 2.1.
SFRs
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x80
P0
SP
DPL0
DPH0
DPL1
DPH1
DPS
PCON
0x88
TCON
TMOD
TL0
TL1
TH0
TH1
CKCON
0x90
P1
EIF
IO_DATA_9
0x98
SCON0
SBUF0
IO_ADDR_0 H
IO_ADDR_0 L
IO_DATA_0
IO_ADDR_1 H
IO_ADDR_1
L
IO_DATA_1
0xA0
P2
0xA8
IE
IO_ADDR_2
H
IO_ADDR_2 L
IO_DATA_2
0xB0
P3
IO_ADDR_3
H
IO_ADDR_3 L
IO_DATA_3
0xB8
IP
IO_ADDR_4
H
IO_ADDR_4 L
IO_DATA_4
0xC0
0xC8
T2CON
T2IF
RCAP2L
RCAP2H
TL2
TH2
0xD0
PSW
IO_ADDR_5
H
IO_ADDR_5 L
IO_DATA_5
0xD8
IO_ADDR_6
H
IO_ADDR_6 L
IO_DATA_6
0xE0
ACC
IO_ADDR_7
H
IO_ADDR_7 L
IO_DATA_7
0xE8
EIE
STATUS
0xF0
B
I2CSOA
I2CSCR
I2CSBUF
I2CMSA
I2CMCR
I2CMBUF
I2CMTP
0xF8
EIP
IO_ADDR_8
H
IO_ADDR_8 L
IO_DATA_8
FT122_CMD
FT122_DATA
IO_ADDR_9
H
IO_ADDR_9
L
Table 2.1 FT51A SFR Map

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2.1 Hardware Access
The SFRs contain registers to allow direct access to the USB Full Speed device controller, I2C
Master and I2C Slave peripherals.
There are 10 sets of I/O ports that permit access to the registers of the ADC, PWM, SPI Master,
SPI Slave, UART FTDI, 245 FIFO, DMA, Timers, Watchdog and IOMUX.
Table 2.2 summarises the methods required to access each module.
Name
Method
Name
Method
ADC
I/O
GPIO FTDI
I/O
PWM
I/O
GPIO
SFR
SPI Master
I/O
AIO
SFR
SPI Slave
I/O
Debugger
SFR
I2C Master
SFR
Device Control
I/O
I2C Slave
SFR
IOMUX
I/O
UART FTDI
I/O
Timers 0, 1, 2
SFR
UART DCD
SFR
Timers A, B, C, D
I/O
245 FIFO
I/O
Watchdog FTDI
I/O
DMA Controller
I/O
Watchdog 8051
SFR
USB Device Hub Port
SFR
Table 2.2 FT51A Peripherals
2.1.1 Registers Accessed by SFR
For peripherals and modules addressed directly through the SFRs, the SDCC compiler provides a
“__sfr” keyword to allow their registers to be used like variables. For example, specify
__sfr __at (0x80) P0; to allow access to port 0 via P0 variable. Refer to the SDCC
documentation for further information.
2.1.2 Registers Accessed through I/O Ports
To access a register via the I/O port method, the address of the register has to first be written to
one of the IO_ADDR_x SFRs; then the data can be read from, or written to, the matching IO_DATA_x
SFR.
The I/O port address space is 9 bits, 0x000 to 0x1FF. Therefore the IO_ADDR_x SFRs have a high
and a low byte. The high byte is normally zero because only the IO Cell Controller is located above
the address 0xFF.
The SFRs contain 10 separate I/O ports. Writing to the address register for one port does not
interfere with an address written previously for a different port.
Example macros for writing and reading I/O ports are presented below:

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#define WRITE_IO_REG(address, data) \
do \
{ \
IO_ADDR_9_H = (unsigned char)((unsigned int)(address) >> 8); \
IO_ADDR_9_L = (unsigned char)(address); \
IO_DATA_9 = (data); \
} \
while (0)
#define READ_IO_REG(address, data) \
do \
{ \
IO_ADDR_9_H = (unsigned char)((unsigned int)(address) >> 8); \
IO_ADDR_9_L = (unsigned char)(address); \
(data) = IO_DATA_9; \
} \
while (0)
2.1.3 Register Descriptions
The hardware and peripheral descriptions in this chapter include register maps which define the
initial state of the registers, their behaviour and provide a description of the bit fields.
Bit type is the behaviour of the bit when accessed. It can be read only, read and write or write to
clear. The mnemonics used in this chapter are defined in Table 2.3.
Type
Definition
R
Read Only
R/W
Read/Write
W1C
Write ‘1’ to Clear
RFU
Reserved for Future Use
W1T
Write ‘1’ to Trigger, Reads as ‘0’
Table 2.3 Register Bit Type Definitions
The initial state of each register is given in the Reset column of the register descriptions.

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2.2 Device Control Registers
These registers control and provide status on the FT51A device. They are collectively referred to as
the ‘top-level’ registers.
Address
Register Name
Description
0x00
DEVICE_CONTROL_REGISTER
Device Control Registers
0x01
SYSTEM_CLOCK_DIVIDER
System Clock Divider
0x02
TOP_USB_ENABLE
USB Top-Level Control Register
0x03
PERIPHERAL_INT0
Peripheral Interrupt Status 0
0x04
PERIPHERAL_IEN0
Peripheral Interrupt Enable 0
0x05
PERIPHERAL_INT1
Peripheral Interrupt status 1
0x06
PERIPHERAL_IEN1
Peripheral Interrupt Enable 1
0x09
PIN_CONFIG
Debugger State and BDC mode
0x2B
MTP_CONTROL
MTP Memory Control
0x2C
MTP_ADDR_L
MTP Lower Address
0x2D
MTP_ADDR_U
MTP Upper Address
0x2E
MTP_PROG_DATA
MTP Write Data
0x36
MTP_CRC_CTRL
16-bit CRC enable of MTP memory
0x37
MTP_CRC_RESULT_L
16-bit CRC Result Lower Byte
0x38
MTP_CRC_RESULT_U
16-bit CRC Result Lower Byte
0x34
PIN_PACKAGE_CONFIG
Device package Information
0x39
TOP_SECURITY_LEVEL
Device Security Status Register
Table 2.4 Device Control Register Addresses
In addition to the standard interrupts generated by the 8051 core, the FT51A supports other
modules and peripherals as sources. These interrupts can be queried in a hierarchical manner.
Once the top-level interrupt source is known by reading PERIPHERAL_INT0 or PERIPHERAL_INT1 the
interrupt status registers in the pertinent module can then be investigated to determine the low-
level interrupt source.
To clear an interrupt, first the low-level interrupt with the module should be cleared, followed by
the high-level interrupt in the PERIPHERAL_INT0 or PERIPHERAL_INT1 registers.
Interrupt handler routines may need to check if a particular interrupt source is enabled in
INTERRUPT_EN_0 or PERIPHERAL_IEN1 before acting on the interrupt.
To perform a reset of the entire device the top_soft_reset bit in DEVICE_CONTROL_REGISTER must be
set, followed by the reset_8051 bit in the SYSTEM_CLOCK_DIVIDER register.

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2.2.1 DEVICE_CONTROL_REGISTER
Bit
Position
Bit Field Name
Type
Reset
Description
7..2
RFU
R
0
Reserved
1
top_dev_en
R/W
0
This bit MUST be set to allow
write access to all top-level
registers.
0
top_soft_reset
R/W
0
When set will cause a reset of
the entire device. This bit will
always read as zero
Table 2.5 Device Control Register
The Device Control register provides top-level write enable and reset functions for all top-level
registers on the FT51A device. This encompasses only the registers described in this chapter and
not any 8051 core registers or other module’s registers.
Write access to the top-level registers is enabled by setting the top_dev_en bit to 1. Clearing this
bit will disable write access.
To reset all top-level registers, a 1 is written to the top_soft_reset bit. The module clears this bit
when a reset is performed and will therefore always read as ‘0’.

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2.2.2 SYSTEM_CLOCK_DIVIDER
Bit
Position
Bit Field Name
Type
Reset
Description
7..5
RFU
R
0
Reserved
4
reset_8051
R/W
0
Set to reset the 8051 core.
This will cause the 8051
state and registers to be
reset. The program
counter will return to its
RESET value 0x0000. All
other modules and
peripherals except the top-
level registers will be
reset.
3
system_stop_request
R/W
0
For reduced power
consumption. When set
will stop all internal clocks
and place the chip in a low
power state.
Alternatively use PCON
SFR (more below).
2..1
clk_sys_divisor
R/W
0
1
0
Clock
division
0
0
1
0
1
2
1
0
4
1
1
8
0
hub_suspend_en
R/W
0
Allow the hub to enter
suspend mode.
Table 2.6 System and Clock Divider Register
Note: When requesting a low power state and to obtain the lowest possible current
consumption the User must ensure all pad IO controls have no pull ups or downs enabled,
and are configured as an input. Also ensure that the external VCC3V3 is not under any
load conditions.
Note: When running with clock division set to divide-by-8 certain functions are affected:
debugger access is NOT possible; UART cannot run at 3M BAUD. A minimum of divide-by-4
is advised for such operations.
Note: Setting PCON SFR bit 0, so called Power Management Mode (PMM), reduces power
consumption by externally dividing the clock signal provided to the microcontroller,
causing it to operate at a reduced speed. When PMM is invoked, the external pin called
PMM is set into logic 1. It signalizes to external divider that CLK frequency should be
divided by 256. Note that all internal functions, on‐board timers (including serial port baud
rate generation), watchdog timer, and software timing loops will run at the reduced speed.

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PMM is entered and exited by setting the PMM bit (PCON.0). In addition, use of the switchback
feature is possible to affect a return from PMM to the full speed mode. This allows both hardware
and software to cause an exit from PMM. It is the responsibility of the software to test for UART
activity before attempting to change speed, as a modification of the clock divider bits during a
UART operation will corrupt the data.
The switchback feature allows a system to burst to a faster mode when required by an external
event. Enable this feature by setting the PCON bit 2, a qualified interrupt (interrupt which has
occurred and been acknowledged) or serial port reception or transmission cause the
microcontroller to return to full speed mode. An interrupt must be enabled and not blocked by a
higher priority interrupt. Software should manually return the microcontroller to PMM after the
event is completed. The following sources can trigger the Switchback:
external interrupt 0/1,
serial start bit detected, UART,
transmit buffer loaded, UART,
reset,
external reset.

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2.2.3 TOP_USB_ENABLE
Bit
Position
Bit Field Name
Type
Reset
Description
7..6
RFU
R
0
Reserved
5
hub_compd_dev
R/W
Controls the way the hub module
identifies itself during
enumeration :
1 –Hub is part of a compound
device
0 –Hub is not part of a compound
device
4
hub_remote_wakeup_en
R/W
0
1- Enable remote wakeup:
Hub will respond to a host
get_status command with an ACK
0 - Disable remote wakeup:
Hub will respond to a host
get_status command with a STALL
3
hub_stsnzdatahsk
R/W
0
On receipt of a non-zero-length
data packet, device will:
1 –Hub returns a STALL
0 –Hub returns an ACK
2
hub_ext_localpwrsrc
R/W
The setting of this bit is used as a
power status flag which is returned
in response to a Host Get_Status
command :
1 –External power source
0 –Bus powered
1
hub_enable
R/W
0
Write to this bit to enable or disable
the Hub:
1 –Hub enabled
0 –Hub disabled
0
ft122_enable
R/W
0
Write to this bit to enable or disable
USB functionality:
1 –USB enabled
0 –USB disabled
Table 2.7 USB Control Register

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2.2.4 PERIPHERAL_INT0
Bit
Position
Bit Field Name
Type
Reset
Description
7..5
RFU
R
0
Reserved
4
dma3_irq
R/W1C
0
Set when the memory contents
have been successfully copied.
Write '1' to clear interrupt.
3
dma2_irq
R/W1C
0
Set when the memory contents
have been successfully copied.
Write '1' to clear interrupt.
2
dma1_irq
R/W1C
0
Set when the memory contents
have been successfully copied.
Write '1' to clear interrupt.
1
dma0_irq
R/W1C
0
Set when the memory contents
have been successfully copied.
Write '1' to clear interrupt.
0
watchdog_irq
R/W1C
0
Set when a watchdog RESET is
generated after a timeout. Write '1'
to clear interrupt.
Table 2.8 Interrupt Status 0 Register
2.2.5 PERIPHERAL_IEN0
Bit
Position
Bit Field Name
Type
Reset
Description
7..5
RFU
R
0
Reserved
4
dma3_irq_ien
R/W
0
Set to enable the dma3 interrupt.
3
dma2_irq_ien
R/W
0
Set to enable the dma2 interrupt.
2
dma1_irq_ien
R/W
0
Set to enable the dma1 interrupt.
1
dma0_irq_ien
R/W
0
Set to enable the dma0 interrupt.
0
watchdog_irq_ien
R/W
0
Set to enable the watchdog reset
interrupt.
Table 2.9 Interrupt Enable 0 Register

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2.2.6 PERIPHERAL_INT1
Bit
Position
Bit Field Name
Type
Reset
Description
7
fifo_245_irq
R/W1C
0
Set when the 245 FIFO has
generated an interrupt. Write '1' to
clear interrupt.
6
timer_irq
R/W1C
0
Set when the TIMER has generated
an interrupt. Write '1' to clear
interrupt.
5
pwm_irq
R/W1C
0
Set when the PWM has generated
an interrupt. Write '1' to clear
interrupt.
4
spi_slave_irq
R/W1C
0
Set when the SPI slave has
generated an interrupt. Write '1' to
clear interrupt.
3
spi_master_irq
R/W1C
0
Set when the SPI master has
generated an interrupt. Write '1' to
clear interrupt.
2
uart_irq
R/W1C
0
Set when the UART has generated
an interrupt. Write '1' to clear
interrupt.
1
io_cell_controller_irq
R/W1C
0
Set after the completion of an ADC
conversion. Write '1' to clear
interrupt.
0
ft122_irq
R/W1C
0
Set when the USB has generated an
interrupt after a timeout. Write '1'
to clear interrupt.
Table 2.10 Interrupt Status 1 Register

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2.2.7 PERIPHERAL_IEN1
Bit
Position
Bit Field Name
Type
Reset
Description
7
fifo_245_irq_ien
R/W
0
Set to enable the 245 FIFO
interrupt.
6
timer_irq_ien
R/W
0
Set to enable the TIMER interrupt.
5
pwm_irq_ien
R/W
0
Set to enable the PWM interrupt.
4
spi_slave_irq_ien
R/W
0
Set to enable the SPI_SLAVE
interrupt.
3
spi_master_irq_ien
R/W
0
Set to enable the SPI_MASTER
interrupt.
2
uart_irq_ien
R/W
0
Set to enable the UART interrupt.
1
io_cell_controller_irq_ien
R/W
0
Set to enable the ADC interrupt.
0
ft122_irq_ien
R/W
0
Set to enable the USB interrupt.
Table 2.11 Interrupt Enable 1 Register
2.2.8 PIN_CONFIG
Bit
Position
Bit Field Name
Type
Reset
Description
7..1
RFU
R
0
Reserved
0
vbus_detect_mode
R/W
0
When set shall enable Battery
Charge Detection mode.
Table 2.12 Pin Config Register
2.2.9 MTP_CONTROL
The MTP area can be written with program code that is copied into the Shadow RAM at power-on
or reset.