FuturePlus Systems FS2334 User manual

FuturePlus Systems
Corporation
DDR2 DIMM HIGH SPEED PROBE
FS2334
Users Manual
For use with Agilent Technologies Logic Analyzers
Revision 1.4
FuturePlus is a registered trademark of FuturePlus Systems Corporation
Copyright 2006 FuturePlus Systems Corporation

2
How to reach us.......................................................................................................................4
Product Warranty....................................................................................................................5
Limitation of warranty................................................................................................................... 5
Exclusive Remedies ....................................................................................................................................5
Assistance......................................................................................................................................... 5
Software License Agreement..................................................................................................6
License Agreement.......................................................................................................................... 6
Use of the software.......................................................................................................................... 6
Copies and Adaptations.................................................................................................................. 6
Ownership ....................................................................................................................................... 6
Sublicensing and Distribution........................................................................................................ 6
Introduction.............................................................................................................................7
Definitions........................................................................................................................................ 7
Logic Analyzer Modules..............................................................................................................................7
Logic Analyzer Machine..............................................................................................................................7
FS2334 Probe Description......................................................................................................8
Probe Technical Feature Summary .............................................................................................. 8
Probe Components.......................................................................................................................... 8
Signal Assignments on Probe Pods................................................................................................9
Signal Threshold Voltage Settings................................................................................................. 9
Connecting the DDR2 Probe to the Logic Analyzer.................................................................... 9
Test Points ..................................................................................................................................... 10
Connecting to your Target System.............................................................................................. 11
Signal Isolation on the Probe....................................................................................................... 11
Buffered signals on the probe...................................................................................................... 11
Recommended Logic Analyzer Card Requirements and Configuration files......................... 12
Software Requirements.........................................................................................................14
Setting up the 169xx Analyzer..................................................................................................... 14
169xx Licensing............................................................................................................................. 14
Loading 169xx configuration files and General Purpose Probe Feature................................. 14
Offline Analysis............................................................................................................................. 15
TimingZoom Analysis...........................................................................................................17
Decoding DDR Commands.......................................................................................................... 17
Taking a Trace, Triggering, and Seeing Measurement Results ............................................... 17
State Analysis........................................................................................................................18

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Overview........................................................................................................................................ 18
State Analysis Operation – Read and Writes above 667MT/s....................................................................18
State Analysis Operation – Read and Write at 667MT/s or slower............................................................19
State Analysis Operation – Read or Write at 800MT/s ..............................................................................19
The process for setting sampling positions at speeds of 800MT/s:........................................... 20
State analysis calibration procedure ...........................................................................................................21
Adjusting the sampling positions with controlled stimulus ...................................................... 24
State Display.................................................................................................................................. 26
DDR2 Protocol Checking and Performance Tool (FS1140) ..............................................27
FS1140 Installation and Licensing .............................................................................................. 27
Loading the FS1140...................................................................................................................... 27
Setting up the FS1140 DDR2 Tool............................................................................................... 28
Functional and Performance Analysis – NOTE: The Functional Performance portion of this
software will NOT work with 2 FRAME configurations .......................................................... 29
Statistics......................................................................................................................................................29
Errors..........................................................................................................................................................29
Export.........................................................................................................................................................30
Repetitive Run............................................................................................................................................30
Timing Analysis ............................................................................................................................ 30
Export.........................................................................................................................................................30
Appendix................................................................................................................................32
FS2334 Signal to Logic Analyzer Connector and Channel Mapping ...................................... 32

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How to reach us
For Technical Support:
FuturePlus Systems Corporation
36 Olde English Road
Bedford NH 03110
TEL: [phone]
FAX: [phone]
On the web http://www.futureplus.com
For Sales and Marketing Support:
FuturePlus Systems Corporation
TEL: [phone]
FAX: [phone]
On the web http://www.futureplus.com
FuturePlus Systems has technical sales representatives in several major
countries. For an up to date listing please see
http://www.futureplus.com/contact.html.

5
Product Warranty
Due to wide variety of possible customer target implementations, the FS2334
DDR2 DIMM probe has a 30 day acceptance period by the customer from the date
of receipt. If the customer does not contact FuturePlus Systems within 30 days of
the receipt of the product it will be said that the customer has accepted the
product. If the customer is not satisfied with the FS2334 DDR2 DIMM probe they
may return the FS2334 within 30 days for a refund.
This FuturePlus Systems product has a warranty against defects in material and
workmanship for a period of 1 year from the date of shipment. During the warranty
period, FuturePlus Systems will, at its option, either replace or repair products proven to
be defective. For warranty service or repair, this product must be returned to the factory.
For products returned to FuturePlus Systems for warranty service, the Buyer shall
prepay shipping charges to FuturePlus Systems and FuturePlus Systems shall pay
shipping charges to return the product to the Buyer. However, the Buyer shall pay all
shipping charges, duties, and taxes for products returned to FuturePlus Systems from
another country.
FuturePlus Systems warrants that its software and hardware designated by FuturePlus
Systems for use with an instrument will execute its programming instructions when
properly installed on that instrument. FuturePlus Systems does not warrant that the
operation of the hardware or software will be uninterrupted or error-free.
The foregoing warranty shall not apply to defects resulting from improper or inadequate
maintenance by the Buyer, Buyer-supplied software or interfacing, unauthorized
modification or misuse, or improper site preparation or maintenance. NO OTHER
WARRANTY IS EXPRESSED OR IMPLIED. FUTUREPLUS SYSTEMS
SPECIFICALLY DISCLAIMS THE IMPLIED WARRANTIES OF MERCHANTABILITY
AND FITNESS FOR A PARTICULAR PURPOSE.
Exclusive Remedies
THE REMEDIES PROVIDED HEREIN ARE BUYER’S SOLE AND EXCLUSIVE
REMEDIES. FUTUREPLUS SYSTEMS SHALL NOT BE LIABLE FOR ANY DIRECT,
INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, WHETHER
BASED ON CONTRACT, TORT, OR ANY OTHER LEGAL THEORY.
Product maintenance agreements and other customer assistance agreements are
available for FuturePlus Systems products. For assistance, contact the factory.
Limitation of warranty
Assistance

6
Software License Agreement
IMPORTANT - Please read this license agreement carefully before opening the media
envelope. Rights in the software are offered only on the condition that the customer
agrees to all terms and conditions of the license agreement. Opening the media
envelope indicates your acceptance of these terms and conditions. If you do not agree
to the licensing agreement, you may return the unopened package for a full refund.
In return for payment for this product, FuturePlus Systems grants the Customer a
SINGLE user LICENSE in the software subject to the following:
Customer may use the software on any one Agilent mainframe logic analysis system.
•Customer may make copies or adaptations of the software.
•Customer may not reverse assemble or decompile the software.
•Are allowed for archival purpose only.
•When copying for adaptation is an essential step in the use of the software with the logic
analyzer and/or logic analysis mainframe so long as the copies and adaptations are used in no
other manner. Customer has no right to copy software unless it acquires an appropriate license
to reproduce from FuturePlus Systems.
•Customer agrees that it does not have any title or ownership of the software, other than the
physical media.
•Customer acknowledges and agrees that the software is copyrighted and protected under the
copyright laws.
•Transfer of the right of ownership shall only be done with the consent of FuturePlus Systems.
Customer may not sublicensing the software or distribute copies of the software to the public in
physical media or by electronic means or any other means without the prior written consent of
FuturePlus Systems.
License Agreement
Use of the software
Copies and Adaptations
Ownership
Sublicensing and Distribution

7
Introduction
Thank you for purchasing the FuturePlus Systems FS2334 DDR2 DIMM Interposer
Logic Analyzer Probe. We think you will find the FS2334, along with your Agilent
Technologies Logic Analyzer, a valuable tool for helping to characterize and debug your
DDR2-based systems. This Users Guide will provide the information you need to install,
configure, and use the DDR2 Probe. If you have any questions about this Guide or use
of this probe, please contact FuturePlus Systems Corporation.
Definitions
Logic Analyzer Modules
"Module" - A set of logic analyzer cards that have been configured (via cables
connecting the cards) to operate as a single logic analyzer whose total available
channels is the sum of the channels on each card. A trigger within a module can be
specified using all of the channels of that module. Each module may be further broken
up into "Machines”. A single module may not extend beyond a single 5 card 16700
frame or 6 card 16900 frame.
Logic Analyzer Machine
"Machine" - A set of logic analyzer pods from a logic analyzer module grouped together
to operate as a single state or timing analyzer.

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FS2334 Probe Description
The FS2334 DDR2 Probe allows you to perform timing analysis measurements on
DDR2 DIMM busses. It also provides a Protocol Decoder with the capability of providing
State analysis of both Read and Write activity is provided by using the dual sample
mode feature available on the 169xx.
The interposer design of this probe allows any DDR2 connection to be probed while it
supports a DDR2 DIMM module.
Probe Technical Feature Summary
•Quick and easy connection between the DDR2 240 pin DIMM connector and Agilent
Logic Analyzers.
•Interposer design does not consume a DDR2 slot.
•Complete and accurate state analysis up to 800MT/s.
•Available Protocol Checking capability (VBA license required) software.
•Uses Auto Sample Position Set-up (EyeFinder) and Auto Threshold Set-up to locate
tight DDR2 data valid windows for optimal state data capture.
Probe Components
The following components have been shipped with your FS2334 DDR2 Probe:
•FS2334 DDR2 DIMM Probe
•Supplemental DC power supply.
•This Users Guide and other information on CD-ROM.
•CD-ROM with the following software install files:
•FS1136 DDR2 Protocol decoder software and configuration files for 169xx
analyzers or offline analysis of 800MT/s data traffic
•FS1117 DDR2 Protocol Decoder software and configuration files for 169xx
analyzers or offline analysis of data traffic <= 667MT/s.
•FS1140 Protocol Checking software.
•Software Entitlement Certificate for Windows based FS1136, FS1117 and FS1140
software.
•Quick Start Sheet.

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Signal Assignments on Probe Pods
The overlap in the bit ranges (for DQxx) signals between pods occurs because the bits
are assigned to pods in the order that they appear physically on the DDR2 DIMM
connector, which is not strictly in logical bit order. This allows the Probe layout to better
match stub lengths among all DQxx signals.
See the Appendix for a detailed list of how Logic Analyzer Channels are mapped to
signals and DDR2 pins.
Signal Threshold Voltage Settings
The standard voltage threshold for the logic analyzer pods is defined as 900mV. This is
based on the SSTL2-1.8V signaling used by the DDR2 DIMM bus. The configuration
files provided with this product set-up the threshold voltages for both the Data and
Command pods to 900mV. Design differences between target platforms or overvoltage
settings may require adjustment of the logic analyzers threshold for optimal signal
capture. The use of Eye Scan can be very helpful in determining where to set these
thresholds.
NOTE: The optimal settings may need to be defined either through trial and error
or by using Eye Scan. Accurate data capture is very dependent on optimizing
these settings and changes of as little as 50mV may have a significant effect.
Connecting the DDR2 Probe to the Logic Analyzer
The FS2334 DDR2 Probe requires up to 7 logic analyzer cards depending on whether
state (Read and Write - quadruple sampled), state (Read or Write - dual sampled), or
timing measurements are desired. See Timing and State configuration information
below.
At this time the user may find it easier to connect the logic analyzer cables to the probe
before inserting the probe into the target system. The FS2334 probe has fourteen 90 pin
pod connections which mate directly to Agilent Logic analyzer cards. Adapter cables are
not required. Once a configuration file is loaded refer to the General Purpose Probe
feature in the Agilent 1690x Overview tab for cable connections.

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FS2334 Frontside layout
FS2334 Backside layout
Test Points
There are several test point on the board.
The first set of test points are used to select which signals go to the Clk input and the
D15 input of Header 2. The shipping configuration for the FS2334 is to have S0 wired to
the Clk input, which is TP3 wired to TP1. This is done in the factory by soldering a short
wire between the 2 test points.
If CKE0 is to be used as a Clk input then TP7 is wired to TP1 and S0 is brought to the
D15 input by wiring TP3 to TP2.
Header 3 Header 4 Header 5
Header 14
Header 1 Header 6 Header 7 Header 8
Header 13
Header 9
Header 2
Header 11 Header 10 Header 12
TP 5
TP 6 TP 4
TP 1,2,3,7
1.25”

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DM2_DQS11 is not brought to the logic analyzer, but it can be probed at TP4
DQS5n is not brought to the logic analyzer, but it can be probed at TP5
DQS14n is not brought to the logic analyzer, but it can be probed at TP6
Connecting to your Target System
To connect the probe to the DDR2 bus, select an available DDR2 slot. Remove the
DDR2 DIMM module, if present. Install the DDR2 DIMM module into the 240 pin
connector on the top of the FS2334 probe.
Install the DDR2 probe/DIMM into the target system.
Connect the supplemental power supply to the FS2334.
Connect the FS2334 Headers directly to the logic analyzer pods per the configuration
file requirements if not done prior to installing the probe. Refer to the General Purpose
Probe.
Signal Isolation on the Probe
All signals sent to the logic analyzer from the FS2334 DDR2 probe are isolated from the
DDR2 DIMM bus by a parallel RC network of 20K ohms and .3 pF. These resistors are
placed in a manner to minimize stubs seen by the DIMM bus and to match lengths to the
DIMM module so that Data bits and their Strobe/Mask bits are matched to within 20 ps.
Buffered signals on the probe
The DDR2 DIMM bus Control signals are buffered on the probe before they are
connected to the DIMM. This includes the S0:1, CKE0:1, and ODT0:1 signals.

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Recommended Logic Analyzer Card Requirements and Configuration files
169xx Analyzer
Type Timing Analysis State Analysis
667MT/s or slower
16753/4/5/6,
16950
FS234_2 3 cards
configured as one
module, one timing
machine
FS234_5 4 cards
configured as one logic
analyzer state machine.
Uses FS1117
800MT/s
16753/4/5/6,
16950
16960
FS234_2 3 cards
configured as one
module, one timing
machine
N/A
FS234_1 Read and Write
analysis requires 7 cards
across 2 frames
configured as 2 logic
analyzer state machines.
Uses FS1136
FS234_3 4 card
configuration provides
Write state analysis
only Uses FS1136
FS234_4 4 card
configuration provides
Read state analysis only
Uses FS1136
FS234_32_Lower(Upper)
4 card configuration
provides Read and Write
state analysis for only 32
bits of Data, either Lower
or Upper
Uses FS1136
FS234_6 4 card
configuration Read and
Write state analysis.
Uses FS1117

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Logic Analyzer card configurations – Note: These are all for unbuffered DIMM
probing
FS234_1 2 machine, 7 Card 800MT/s
Read and Write configuration file Write – Command machine 4 cards in slots A – D (B = Master). Read machine 3 cards in slots A – C (B =
master)
FS234_32_Lower(Upper) 4 card 32 bit
800MT/s Data State analysis configuration 4 cards in slots A – D (B = Master)
FS234_2 Timing analysis 3 card
configuration 3 cards in slots A – C (B = Master)
FS234_3 800MT/s Writes only 4 card
configuration 4 cards in slots A – D (B = Master)
FS234_3 800MT/s Reads only 4 card
configuration 4 cards in slots A – D (B = Master)
FS234_3 667MT/s Reads and Writes 4
card configuration 4 cards in slots A – D (B = Master)
FS234_6 and FS234_7. Reads and Writes
4 card configuration 4 cards in slots C – F (F= Master)

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Software Requirements
Setting up the 169xx Analyzer
A CD containing the 16900 software is included in the FS1136 package. The CD
contains a setup file that will automatically install the configuration files and protocol
decoder onto a PC containing the 16900 operating system or onto a 16900 analyzer
itself.
To install the software simply double click the .exe file on the CD containing the FS1136
and the FS1117 software. After accepting the license agreement the software should
install within a couple of minutes. Duplicate the process for the FS1140 Protocol
Checking software.
169xx Licensing
Once the software has been successfully installed you must license the software.
Please refer to the entitlement certificate for instructions on licensing each software
product. Please note that you are licensing 3 products, both the FS1136 and
FS1117 Protocol Decoders AND the FS1140 Protocol Checking software and all
require separate license installation on your system. The software can only be
installed on one machine. If you need to install the products on more than one machine
you must contact the FuturePlus sales department to purchase additional licenses.
Loading 169xx configuration files and General Purpose Probe Feature
When the software has been licensed you are able to load a configuration file. You can
access the configuration files by clicking on the folder that was placed on the desktop.
When you click on the folder it should open up to display all the configuration files to
choose from. If you put your mouse cursor on the name of the file a description will
appear telling you what the setup consists of, once you choose the configuration file that
is appropriate for your configuration, the 16900 operating system should execute. The
protocol decoder automatically loads when the configuration file is loaded. If the
decoder does not load, you may load it by selecting tools from the menu bar at the top of
the screen and select the decoder from the list.
Once you have loaded a configuration file on the 169xx machine you can find out how to
attach the logic analyzer cables to the probe by going to the workspace and selecting
Properties on the General Purpose Probe tool icon that appears before the logic
analyzer icon. Once you click on the Properties box a new window will appear showing
which analyzer pod attaches to which probe cable.

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Offline Analysis
Offline analysis allows a user to be able to analyze a trace offline at a PC so it frees up
the analyzer for another person to use the analyzer to capture data.
If you have already used the license that was included with your package on a
1680/90/900 analyzer and would like to have the offline analysis feature on a PC you
may buy additional licenses, please contact FuturePlus sales department.
In order to view decoded data offline, after installing the 1680/90/900 operating system
on a PC, you must install the FuturePlus software. Please follow the installation
instructions for “Setting up a 16900 analyzer”. Once the FuturePlus software has been
installed and licensed follow these steps to import the data and view it.
From the desktop, double click on the Agilent logic analyzer icon. When the application
comes up there will be a series of questions, answer the first question asking which
startup option to use, select Continue Offline. On the analyzer type question, select
cancel. When the application comes all the way up you should have a blank screen with
a menu bar and tool bar at the top.
For data from a 16900 analyzer, open the .ala file using the File, Open menu selections
and browse to the desired .ala file.
After clicking “next” you must browse for the fast binary data file you want to import.
Once you have located the file and clicked start import, the data should appear in the
listing.

16
After the decoder has loaded, select Preferences from the overview screen and set the
preferences to their correct value in order to decode the trace properly.
The protocol decoders, FS1136 and FS1117, require 4 parameters to be entered by the
user in order to decode valid states. To access the preferences on the 169xx select
Prefs from the graphic representation of the protocol decoder in the overview window.
The information required is generally available from the spec. sheet of the memory
device being used or by querying the BIOS of the target system.
a) Number of Chip Selects – This is either 1 or 2 based on the whether either
S0 is being probed and incorporated into the IA or both S0 and S1.
b) CAS Latency – Also defined as “CL”, or the delay from a valid Read
command to when the Read data is strobed on the bus.
c) Additive Latency – Defined by the chipset
d) Burst Length – Usually fixed at 4, or 8.
e) Additionally, the FS1136 has Preference selections for Data bit length and
number of logic machines
The input screen for this information is shown below

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TimingZoom Analysis
The TimingZoom feature of the 1690x logic analyzer allows for efficient timing analysis
of all the signals on the DDR2 DIMM bus.
Please refer to the “Setting up the 16900 Analyzer” section of this manual on the use of
the general purpose probe feature to determine how to attach the logic analyzer to the
probe.
Load the logic analyzer configuration file for timing, FS234_2. It doesn't matter whether
you select to load "Configs only" or "Configs and Data". You are now ready to start
making measurements.
For timing analysis operation above 600 MHz you need to use the ½ Channel Timing
Mode, which provides bandwidth to 1.2GHz. This mode makes every other pod
available to the user so 4 cards are required. These must be configured via the cables
supplied with the cards as a single logic analyzer module. Refer to the appropriate
Agilent Technologies manual for information on how to connect analyzer cards together
to create multi-card modules.
Please note that 6 of the ECC bits and their Data Strobe (DQS8) are contained on an
extra Header (#14), which will require an additional logic analyzer card in order to probe.
Decoding DDR Commands
No Protocol Decoder is used for timing analysis. However, symbols are pre-defined for
the DDR2 Command bus. These decode the RAS, CAS, and WE lines to display the
DDR Command as “Read”, “Write”, etc., so you don’t have to refer to the DDR chip data
sheet to see what command is being executed. These decoded values are displayed by
setting the display base (in the listing window) or the label property (in the waveform
window) to “Symbols”. The display base defaults to hexadecimal.
Taking a Trace, Triggering, and Seeing Measurement Results
Timing analysis is the simplest setup and there are no special factors involved in
analyzer trigger setup, initiating a trace, and viewing results. For the Command bus you
can use the pre-defined symbols to specify mnemonically the command you wish to
trigger on. These are set up by default and are accessible in the trigger tab. The default
waveform display also shows DDR Commands mnemonically.
You may setup a trigger, initiate a measurement, and view results in the usual ways via
the trigger tab, pressing the Run button, and opening the desired display window.

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State Analysis
Overview
There are several choices for State mode analysis using the FS2334 DDR2 probe
depending on the speed of the data bus being probed and the number of logic analyzer
cards available to the user. At data speeds of up to 667MT/s the logic analyzer can be
triggered on BOTH edges of the clock signal used for State analysis (state clock), at a
data speed of 800MT/s ONLY the rising edge of the state clock can be used.
Because the sampling point for a data signal is at a different position relative to the state
clock edges during a Read data burst than during a Write data burst you need 2
sampling points established for each data signal, which allows the analyzer to sample a
data signal twice at speeds up to 667MT/s. When you only have sampling on the rising
edge of the state clock (800MT/s) you need to sample each data signal four times
because you need to account for both the 2 data states per clock and both Reads and
Writes. This is all done by the logic analyzer cards, which drives the cards requirements.
If a user is willing to sample ONLY Read OR Write bursts at 800MT/s, then you reduce
your sampling requirements by ½.
FuturePlus has provided configuration files and a set-up procedure that anticipates
these different scenarios and has described them in the following pages. Please note
that these are for DIMMs without ECC because the addition of the DQ64-72 bits would
force the user to add another card in all the configurations. These bits are available
(refer to the Appendix) if the user wants to modify the existing configuration files and/or
add an additional logic analysis card.
State Analysis Operation – Read and Writes above 667MT/s
State mode capture of Reads and Writes at data rates above 667MT/s requires
quadruple sampling of the Data bits and is performed by using the rising edge of CK0.
This requires 7 cards, which means that for every Data bit there are 4 labels (or
sampling positions), Write Data rising and falling, and Read Data rising and falling. The
analyzer sample position of each channel is set as described later in this manual. The
DDR Command/Address bus is also sampled (along with the data bus) on the rising
edge of CK0.
The 7 cards are configured as 2 logic analyzer machines (Write/Command and Read) in
2 separate frames. CK signals are provided to both machines as well as MRASn and
RASn, which are 2 copies of the same signal from each logic analyzer machine that can
be used as a reference signal for intermodule skew adjustment.
The configurations are set-up with 4 cards melded together in Frame # 1 in slots C, D
(master), E and F. Frame #2 has 3 cards melded together in slots A, B (master) and C.
The frames need to be connected through the Intermodule cable and share a network
connection. More detailed information is available within the Help documentation on
your Agilent Logic analysis frame under “Multiframe operation”.
If you are using the special configurations for 32 bits of Read and Write Data decode
only, then a 4 card configuration in one frame is all that is required.

19
State Analysis Operation – Read and Write at 667MT/s or slower
State mode capture is performed by using both edges of CK0. This double probing of
each signal is handled internally by the Agilent Logic Analyzer using the Dual Sample
mode feature. State analysis within these parameters only requires dual sampling of the
Data signals, which can be done with 4 cards in one frame. The four cards used for
state analysis must be configured as one logic analyzer machine. You may also place
the cards in slots other than described here, but must then adjust the pod connection
tables and configuration file loading instructions accordingly. The configuration file is set
up with the Master in slot D, expanders in C, E, and F.
The analyzer sample position of the channel capturing data is set via a calibration
procedure (described in this document) to the optimum value. The DDR
Command/Address bus is also sampled (along with the Data bus) on both edges of
CK0. This does not reduce triggering capability but does require additional care when
setting up triggers because the command/address bus is not valid on the falling edge of
CK0.
The Auto Sample Position Set-up function can be a more accurate means to set the
sampling position for each bit used in the State analysis, but this requires using known,
continuous data patterns of exclusive Reads and then exclusive Writes.
The logic analyzer’s TimingZoom traces can be used to set the sampling positions for
the labels as described in the following sections. Note: The label names are different
depending on whether you are doing Read and Write <= 667MT/s (FS1117) or doing
Read or Write at 800 MT/s (FS1136).
State Analysis Operation – Read or Write at 800MT/s
This mode of State Analysis permits just the use of 4 cards and one logic analyzer
frame. There are 2 different configuration files provided, on for Read only and one for
Write only State analysis. These configuration files use the FS1136 Protocol Decoder
and difference between the 2 is there pre-defined sampling positions are set for one
type of data burst or the other. The State clock operates on only the rising edge of the
clock and each data signal is sampled twice.
Please note that the Protocol decoder listing will show invalid data for the type of burst
that the sampling positions are not defined for.
Setting the sampling positions is done in the same manner as for the 7 card, 800MT/s
configuration, the only difference being fewer labels to set sampling positions for.

20
The process for setting sampling positions at speeds of 800MT/s:
This procedure requires the probe user to capture TimingZoom traces and use the
markers to determine the correct sampling positions. This is an iterative, trial and error
procedure where adjustments to Data signal sampling positions may need to be
adjusted several times before they provide correct State data capture on both Read and
Writes.
When operating at 800MT/s data speed and a Multi-Frame configuration. There are
several things to consider:
1) There are 4 sets of State Data. These are:
a. Write Data sampled on the rising edge of CK0 Data63-0_R
b. Write Data sampled on the falling edge of CK0 Data63-0_F
c. Read Data sampled on the rising edge of CK2 READdata63-0_R
d. Read Data sampled on the falling edge of CK2 READdata63-0_F
2) Please note within each of these 4 groups of labels there are additional labels
organized by data byte. This is because many platforms may display timing
differences between byte groups and therefore require a slightly different sampling
setting which the byte labels make easier to both measure and set.
3) At 400MHz clock speed the 16900 analyzer in this configuration will display both the
State and TimingZoom version of the State Clock signal, (CommandClk) CK0 for the
Write analyzer and CK2 for the Read analyzer, at ½ it’s actual frequency. For an
.actual representation of the state clock use Write – Command:CK2_TZ
4) Because of the logic analyzer’s pod to pod skew of +/- 1.75ns, you want to take
several timing offset measurements before setting a sampling value.
5) Both the Write and Read analyzers are clocked only on the rising edge of their State
Clocks.
6) The Intermodule Skew should not need adjustment for State analysis. This can
done if necessary by aligning the MRAS_TZ (Write analyzer) and RAS_TZ (Read
analyzer) signals, but the user will have to reset it after every trace capture.
7) Sample positions for Command, Address and Control signals are already set to
values that should allow proper State analysis. If adjustment is necessary they can
be moved using either the TimingZoom measurement procedure described here, or
by using Auto Sample positioning provided that Chip Select qualification is applied
or the system is slowed down to a DDR clock rate of 333MHz and the logic analyzer
is set to 300MHz State mode.