Gan Systems GS-EVB-HB-66508B-RN User manual

GS-EVB-HB-66508B-RN Technical Manual
_____________________________________________________________________________________________________________________
GS-EVB-HB-66508B-RN Rev. 210118 © 2021 GaN Systems Inc. www.gansystems.com 1
Please refer to the Evaluation Board/Kit Important Notice on page 26
GS-EVB-HB-66508B-RN
Technical Manual
Visit www.gansystems.com for the latest version of this technical manual.
DANGER!
This evaluation kit is designed for engineering evaluation in a controlled
lab environment and should be handled by qualified personnel ONLY.
High voltage will be exposed on the board during the test and even brief
contact during operation may result in severe injury or death.
Never leave the board operating unattended. After it is de-energized,
always wait until all capacitors are discharged before touching the board.
CAUTION:
This product contains parts that are susceptible to damage by electrostatic
discharge (ESD). Always follow ESD prevention procedures when
handling the product.

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Overview
The GS-EVB-HB-66508B-RN is a RTK226110DE0010BU RAA226110
https://www.renesas.com/products/raa226110 gate drive demo board following GS665XXX-EVBDB
daughter board style. This evaluation kit consists of two GaN Systems 650V GaN Enhancement-mode
HEMTs (E-HEMTs) and all necessary circuits including half bridge gate drivers, isolated power supplies
and optional heatsink to form a functional half bridge power stage. It allows users to easily evaluate the
GaN E-HEMT performance in any half bridge-based topology, either with the universal mother board
(P/N: GS665MB-EVB) or users’ own system design. The GS-EVB-HB-66508B-RN demo board provides 0V
turn-off voltage solution. 0V turn-off solution is normally used in low power application. 0V turn-off
solution is easy to implement as there is no need a negative power supply rail. And the reverse
conduction voltage drop of GaN is lower. For E-mode GaN device the Vgs threshold voltage is low (typ:
1.7V). 0V turn-off has the risk of false turn-on when the GaN device is in off state. Also, the switching-off
loss will be higher than negative turn-off voltage. The 0V turn-off solution is normally used in the low
power applications.
Features:
•Serves as a reference design and evaluation tool as well as deployment-ready solution for easy in-
system evaluation.
•Vertical mount style with height of 35mm, which fits in majority of 1U design and allows
evaluation of GaN E-HEMT in traditional through-hole type power supply board.
•Current shunt position for switching characterization testing
•Universal form factor and footprint for all products
•0V turn off voltage
The daughter board and universal mother board ordering part numbers are below:
Table 1 Ordering part numbers
Part Number
GaN E-HEMT P/N:
Description
GS-EVB-HB-66508B-RN GS66508B GaN E-HEMT 650V/30A, 50mΩ With
RAA226110 gate driver, 0V turn off voltage
GS665MB-EVB
Universal 650V Mother Board
Control and Power I/Os:
The daughter board GS-EVB-HB-66508B-RN circuit diagram is shown in Figure 1. The control logic
inputs on 2x3 pin header J1 are listed below:

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Table 2 Control pins
Pin
Descriptipon
ENABLE Enable input. It is internally pulled up to VCC, a low logic disables all the PWM gate
drive outputs.
+5V +5V auxillary power supply input for logic circuit and gate driver. On the daughter
board there are 2 isolated 5V to 9V DC/DC power supplies for top and bottom
switches.
VDRV
Not used. VDRV can be connected to VCC though R43. R43 is DNP by default.
PWMH_IN
High side PWM logic input for top switch Q1. It is compatible wth 3.3V and 5V
PWML_IN
Low side PWM logic input for bottom switch Q2. It is compatible wth 3.3V and 5V
0V
Logic inputs and gate drive power supply ground return.
The 3 power pins are:
•VDC+: Input DC Bus voltage
•VSW: Switching node output
•VDC-: Input DC bus voltage ground return. Note that control ground 0V is isolated from VDC-
Figure 1 GS-EVB-HB-66508B-RN Evaluation Board Block Diagram
Isolator
IL611-1E
Q
1
Q
2
Iso
.
DC
/
DC
Iso
.
DC
/
DC
VDC
+
VSW
VDC
-
VCC
ENABLE
shunt
C
4
-
10
PWMH
PWML
Gate Driver
RAA226110
Gate Driver
Isolator
IL611-1E
RAA226110

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GS-EVB-HB-66508B-RN half bridge daughter board
Figure 2 GS-EVB-HB-66508B-RN top side
Figure 3 GS-EVB-HB-66508B-RN bottom side
A. 2x GaN Systems 650V E-HEMT GS66508B, 30A/50mΩ.
B. Decoupling capacitors C14-C17 and C47-C54.
C. Signal isolator IL611-1E.
D. GaN driver RAA226110.
E. OCP shunt.
F. TP8(gate) and TP3(source) test points for bottom Q2 VGS.
G. 5V-9V isolated DC/DC gate drive power supply
C
D
F
E
A
B
G
Heat sink location

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GaN E-HEMTs:
•This daughter board includes two GaN Systems E-HEMT GS66508B (650V/30A, 50mΩ) in a
GaNPx™ B type package. The large S pad serves as source connection and thermal pad. The pin
4 is the kelvin source connection for gate drive return.
Figure 4 Package outline of GS66508B
Gate driver circuit:
•Renesas RAA226110 low-side gate driver is chosen for this design. This driver provides 5.8V gate
drive with 3.8V UVLO. It supports the 5.8V turn on and -3V/0V turn off. It has separated source
and sink drive outputs which eliminates the need for additional diode. OCP is also integrated in
the driver.
•RAA226110 provides configurable source current(0.3A/0.75A/2A) to adjust the slew rate of
GS66508B without gate resistor to minimize the gate loop. The turn off speed can be directly
controlled by the gate resistor Rg_off (R19/R20).
Figure 5 Gate driver circuit
Gate drive power supply:
•5V-9V isolated DC/DC converters are used for gate drive. The RAA226110 accpets 4.5V to 18V
VDD input voltage. DC/DC conterter 9V output is directly connected to RAA226110.

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Figure 6 Gate drive power supply
Current shunt:
•The board provides an optional current shunt position E(figure2) between the source of Q2 and
power ground return. This allows drain current measurement for switching characterization test
such as Eon/Eoff measurement.
•The current shunt is also used to provide the OCP signal for the RAA226110 to trigger OCP. The
OCP threchold voltage 40mV/80mV/120mV can be configured through the IDSET pin of
RAA226110.
•If current shunt is not used position Emust be shorted.
Figure 7 Current shunt position E
Q2 source
VDC-
Shunt

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CAUTION:
Check the shunt position E before the first time use. To complete the circuit
position Eneeds to be either shorted or a current shunt must be inserted
before powering up.
Measurement with current shunt:
1. When measuring VSW with current shunt, ensure all channel probe grounds and current shunt
BNC output case are all referenced to the source end of Q2 before the current shunt. The
recommended setup of probes is shown as below.
2. The output of coaxial current shunt can be connected to oscilloscope via 50Ωtermination
impedance to reduce the ringing.
3. The measured current is inverted and can be scaled by using: Id=Vid/Rshunt.
Figure 8 Recommended probe connection with current shunt
Thermal design:
1. GS66508B has a thermal pad at the bottom side for heat dissipation. The heat is transferred to the
bottom side of PCB using thermal vias and copper plane.
2. A heatsink (35x35mm size) can be attached to the bottom side of board for optimum cooling.
Thermal Interface Material (TIM) is needed to provide electrical insulation and conformance to
the PCB surface. The daughter board evaluation kit supplies with a sample 35x35mm fin heatsink
(not installed), although other heatsinks can also be used to fit users’ system design.
3. A thermal tape type TIM (Berguist®Bond-Ply 100) is chosen for its easy assembly. The supplied
heatsink has the thermal tape pre-applied so simply peel off the protective film and attach the
heatsink to the back of board as marked in Figure 3.
4. Two optional mounting holes as shown in Figure 9 are provided for mounting customized
heatsink using screws.
5. Using the supplied heatsink and TIM, the overall junction to ambient thermal resistance RthJ-A is
~9°C/W with 500LFM airflow.
6. Forced air cooling is recommended for power testing.
VGL
VSL
VSW
BNC case
To oscilloscope
probe input (use
50Ω termination)
BNC tip
V
DS
V
GS
I
D

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Figure 9 The daughter board with heatsink attached
CAUTION:
There is no on-board over-temperature protection. Device temperature must
be closely monitored during the test. Never operate the board with device
temperature exceeding TJ_MAX (150°C)
Using GS-EVB-HB-66508B-RN with universal mother board GS665MB-EVB
Figure 10 650V universal mother board GS665MB-EVB
12V INPUT
(+)
5V Power Supply
CIN
VSW
PWM control & dead
time circuit
Daughter Board
Probing point for VSW
For Ext.
12VDC Fan
Airflow direction
Optional Cout
VDC- VOUT
VDC-
VDC+

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GaN Systems provides a universal 650V mother board (ordering part number: GS665MB-EVB, sold
separately) that can be used as the basic evaluation platform for all the daughter boards.
The universal 650V mother board evaluation kit includes following items:
1. Mother board GS665MB-EVB
2. 12VDC Fan
12V input:
The board can be powered by 9-12V on J1. On-board voltage regulator creates to 5V for daughter board
and control logic circuits. J3 is used for external 12VDC fan.
PWM control circuit:
Figure 11 PWM control input and dead time circuit
Figure 12 On board dead time generatrion circuit
The top and bottom switches PWM inputs can be individually controlled by two jumpers J4 and J6. Users
can choose between a pair of complementary on-board internal PWM signals (non-inverted and inverted,
0V
D1 PMEG2005EB
SOD523
R6
1K00
TR12K C11
100pF
0V
R5
1K00
C10
1uF
C9
0.1uF
+5V
J7
112538 1
2
3 4
5
R4
100R
R1206
R2
100R
R1206
U2A
74VHC132
3
1
2
14
7
0V
R1
49R9
0V
D2 PMEG2005EB
SOD523
TR22K
C12
100pF
0V
U2B
74VHC132
4
5
6
U2C
74VHC132
9
10
8
U2D
74VHC132
12
13
11
TP7
TP8
DNP
DNP
PWM
OUTPUT
INVERTED
PWM OUTPUT
R3
49R9
DNP
DNP
R7
49R9

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controlled by J7 input) with dead time or external high/low side drive signals from J5 (users’ own control
board).
An on-board dead time generation circuit is included on the mother board. Dead time is controlled by
two RC delay circuits, R6/C12 and R5/C11. The default dead time is set to about 100ns. Additionally two
potentiometers locations are provided (TR1/TR2, not included) to allow fine adjustment of the dead time
if needed.
WARNING!
ALWAYS double check the jumper setting and PWM gate drive signals
before applying power. Incorrect PWM inputs or jumper settings may cause
device failures
Test points:
Test points are designed in groups/pairs to facilitate probing:
Test points
Name
Description
TP1/TP2
+5V/0V
5V bias power
TP7/TP8
PWMIN/0V
PWM input signal from J7
TP4/TP3/TP13
PWMH/PWML/0V
High/low side gate signals to daughter board
TP9/TP10
VDC+/VDC-
DC bus voltage
TP11/TP12
VOUT/VDC-
Output voltage
TP6/TP5 VSW/VDC- Switching node output voltage (for HV oscilloscope
probe)
Power connections:
CON1-CON7 mounting pads are designed to be compatible with following mounting terminals:
•#10-32 Screw mount,
•Banana Jack PCB mount (Keystone P/N: 575-4), or
•PC Mount Screw Terminal (Keystone P/N: 8191)
Output passives (L and C14)
An external power inductor (not included) can be connected between VSW (CON1) and VOUT (CON4/5)
or VDC+ (CON2/3) for double pulse test. Users can choose their inductor size to meet the test
requirement. Generally it is recommended to use power inductor with low inter-winding capacitance to
obtain best switching performance. For the double pulse testing we use 2x 60uH/40Amp inductor (CWS,
P/N: HF467-600M-40AV) in series. C14 is designed to accommodate a film capacitor as output filter.

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Double pulse test mode
CON1
Q1
CON2
Q2
VDC-
CON4
CON3
LOUT
400V DC
+
VDC+
CON7CON6
VSW
CON5
+5V
0V
PWM
INPUT
(J7)
VDS
IL
ISW
VGL
+6V
0V
VDS
VGL
IL
t0 t1 t2 t3
T
ON1
Figure 13 Double pulse test setup
Double pulse test allows easy evaluation of device switching performance at high voltage/current
without the need of actually running at high power. It can also be used for switching loss (Eon/Eoff)
measurement and other switching characterization parameter test.
The circuit configuration and operating principle can be found in Figure 13:
1. The output inductor is connected to the VDC+.
2. At t0 when Q2 is switched on, the inductor current starts to ramp up until t1. The period of first
pulse Ton1 defines the switching current ISW = (VDS*TON1) / L.
3. t1-t2 is the free wheeling period when the inductor current ILforces Q1 to conduct in reverse.
4. t1 (turn-off) and t2 (turn-on) are of interest for this test as they are the hard switching trasients for
the half bridge circuit when Q2 is under high switching stress.
5. The second pulse t2-t3 is kept short to limit the peak inductor current at t3.
The double pulse signal can be generated using programmable signal generaotor or microcontroller/DSP
board. As this test involves high switching stress and high current, it is recommended to set the double
pulse test gate signal as single trigger mode or use long repetition period (for example >50-100ms) to void
excess stress to the switches. Q1 can be kept off during the test or driven synchronously (J4 set to OFF or
INT_INV) and Q2 is set to INT (or EXT position if PWM signal is from J5).
WARNING!
Limit the maximum switching test current to 30A and ensure maximum drain
voltage including ringing is below 650V for pulse testing. Exceeding this limit
may cause damage to the devices.

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Buck/Standard half bridge mode
CON1
Q1
CON2
Q2
VDC-
CON4
CON3
LOUT
400V DC
+
VDC+
CON7
CON6
VSW
CON5
COUT RLoad
This is standard half bridge configuration that can be used in
following circuits :
•Synchronous Buck DC/DC
•Single phase half bridge inverter
•ZVS half bridge LLC
•Phase leg for full bridge DC/DC or
•Phase leg for a 3-phase motor drive
Jumper setting:
•J4 (Q1): INT
•J6 (Q2): INT_INV
Boost mode
CON1
Q1
CON2
Q2
VDC-
CON4
CON3
L
IN
VDC+
CON7
CON6
VSW
CON5
INPUT
VIN
When the output becomes the input and the load is
attached between VDC+ and VDC-, the board is
converted into a boost mode circuit and can be used for:
•Synchronous Boost DC/DC
•Totem pole bridgeless PFC
Jumper setting:
•J4 (Q1): INT_INV
•J6 (Q2): INT

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Using GS-EVB-HB-66508B-RN in system:
The daughter board allows users to easily evaluate the GaN performance in their own systems. Refer to
the footprint drawing of GS-EVB-HB-66508B-RN as shown below:
Figure 14 Recommended footprint drawing of daughter board GS665XXX-EVBDB
1 3 5
2 4 6
7
8 9
1. All units are in mm.
2. Pin 1-6: Dia. 1mm
3. Pin 7-9: 1.91mm (75mil) mounting hole for Mill-max Receptacle P/N: 0312-0-15-15-34-27-10-0.

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Quick Start procedure –Pulses test
Follow the instructions below to quickly get started with your evaluation of GaN E-HEMT. Equipment
and components you will need:
•Four-channel oscilloscope with 500MHz bandwidth or higher
•high bandwidth (500MHz or higher) passive probe
•high bandwidth (500MHz) high voltage probe (>600V)
•AC/DC current probe for inductor current measurement
•12V DC power supply
•Signal generator capable of creating testing pulses
•High voltage power supply (0-400VDC) with current limit.
•External power inductor (recommend toroid inductor 50-200uH)
1. Check the position E(figure2) on daughter board GS-EVB-HB-66508B-RN.
2. Install GS-EVB-HB-66508B-RN on the mother board. Press all the way down until you feel a click.
Connect probe between TP8(low side GaN gate) and TP3(low side GaN source) for gate voltage
measurement in the daughter board.
3. Set up the mother board:
a. Connect 12VDC bias supply to J1.
b. Connect PWM input gate signal (0-5V) to J7. If it is generated from a signal generator ensure
the output mode is high-Z mode.
c. Set J4 to OFF position and J7 to INT.
d. Set High voltage (HV) DC supply voltage to 0V and ensure the output is OFF. Connect HV
supply to CON2 and CON6.
e. Use HV probe between TP6 and TP5 for Vds measurement.
f. Connect external inductor between CON1 and CON3. Use current probe to measure inductor
current IL.
4. Set up and check PWM gate signal:
a. Turn-on 12VDC power.
b. Check the 2 LEDs on the daughter board. They should be turned on indicating the isolated
9V is present.
c. Set up signal generator to create the waveforms as shown in Figure 13. Use equation ISW =
(VDS*TON1) / L to calculate the pulse width of the first pulse and ensure the Isw_max is ≤40A at
400VDC.
d. Set the operation mode to either single trigger or Burst mode with repetition period of 100ms.
e. Turn on the PWM output and check on the oscilloscope to make sure the GaN gate drive
voltage waveform is present and matches the PWM input.
5. Power-on:
a. Turn on the output of the HV supply. Start with low voltage and slowly ramp the voltage up
until it reaches 400VDC. During the ramping period closely observe the the voltage and
current waveforms on the oscilloscope.
6. Power-off:

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a. After the test is complete, slowly ramp down the HV supply voltage to 0V and turn off the
output. Then turn off the 12V bias supply and signal generator output.
Figure 15 Pulses test setup example
12VDC
PWM in
Vdc+/Vdc-
Inductor

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Test results – GS66508B-EVBDB
Pulses test (VDS=400V, IMAX = 33A, Lp=120uH, RG(ON)=0Ω, Igsel is connected to VDRV , Gate driver current is 0.3A,
RG(OFF)=1Ω, 8 pulses, periode=4us, duty=50%):
Figure 16 400V/33A pulses test waveform
Figure 16 shows the hard switching on waveforms at 400V/33A. A Vds dip can be seen due to the rising
drain current (di/dt in the power loop ΔV=Lp*di/dt, where Lp is the total power loop inductance). After
the drain current reaches the inductor current, the Vds starts to fall. The Vgs undershoot spike is caused
by the miller feedback via Cgd under negative dv/dt.
Due to the low gate charge and small RG(OFF) , GaN E-HEMT gate has limited control on the turn-off
dv/dt. Instead the Vds rise time is determined by how fast the turn-off current charges switching node
capacitance (Coss).
The low Coss of GaN E-HEMT and low parasitic inductance of GaNPX™ package together with
optimized PCB alyout, enables a fast and clean turn-off Vds waveform with 50V the turn-off Vds
overshoot at dv/dt > 100V/ns. The measured rise time is 4ns at 400V and 33A hard turn-off.
The OCP seting point is 40A. Due to the ringing on the current sensing signal, the actual OCP trigger point is 33A.
After the OCP occurs, the driver will be locked with Gate pulled low regardless the PWM input.
Vds_low side
I_inductor
PWM_low side

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Synchronous Buck Test (L=120uH, VIN=400V, VOUT=80V, D=20%, FSW=100 kHz, POUT =300W)
Figure 17 Buck test waveform (Pout=300W)
Vds_low side
I_inductor
PWM_low side
V_out

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Appendix A - GS-EVB-HB-66508B-RN
Circuit schematics

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Assembly Drawing

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PCB layout
Top Layer
Mid Layer 1