GOWIN DK_START_GW2A-LV18PG256C8I7_V2.0 User manual

DK_START_GW2A-LV18PG256C8I7_V2.0
RISC-V DEMO_B
User Guide
DBUG385-1.1E,09/10/2021

Copyright © 2021 Guangdong Gowin Semiconductor Corporation. All Rights Reserved.
, Gowin, and GOWINSEMI are trademarks of Guangdong Gowin Semiconductor
Corporation and are registered in China, the U.S. Patent and Trademark Office, and other
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or otherwise, without the prior written consent of GOWINSEMI.
Disclaimer
GOWINSEMI assumes no liability and provides no warranty (either expressed or implied)
and is not responsible for any damage incurred to your hardware, software, data, or
property resulting from usage of the materials or intellectual property except as outlined in
the GOWINSEMI Terms and Conditions of Sale. All information in this document should be
treated as preliminary. GOWINSEMI may make changes to this document at any time
without prior notice. Anyone relying on this documentation should contact GOWINSEMI for
the current documentation and errata.

Revision History
Date
Version
Description
01/20/2021
1.0E
Initial version published.
09/10/2021
1.1E
The Quick Start in 2.2 A Development Board Suite removed.

Contents
DBUG385-1.1E
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Contents
Contents ...............................................................................................................i
List of Figures.....................................................................................................ii
List of Tables......................................................................................................iii
1About This Guide ..........................................................................................1
1.1 Purpose ..............................................................................................................................1
1.2 Related Documents ............................................................................................................1
1.3 Abbreviations and Terminology...........................................................................................1
1.4 Support and Feedback .......................................................................................................2
2Development Board Description..................................................................3
2.1 Overview............................................................................................................................. 3
2.2 A Development Board Suite................................................................................................4
2.3 PCB Components...............................................................................................................5
2.4 System Architecture............................................................................................................5
2.5 Features..............................................................................................................................6
3Development Board Circuit ..........................................................................8
3.1 FPGA Module .....................................................................................................................8
3.2 Download Module...............................................................................................................8
3.2.1 Introduction......................................................................................................................8
3.2.2 Pinsout............................................................................................................................. 9
3.3 Power Supply...................................................................................................................... 9
3.3.1 Introduction......................................................................................................................9
3.3.2 Power System Distribution ............................................................................................10
3.4 Clock, Reset ......................................................................................................................11
3.4.1 Introduction.....................................................................................................................11
3.4.2 Pinout..............................................................................................................................11
3.5 DDR3 .................................................................................................................................11

Contents
DBUG385-1.1E
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3.5.1 Introduction.....................................................................................................................11
3.5.2 Pinout.............................................................................................................................12
3.6 Ethernet interface ............................................................................................................. 14
3.6.1 Introduction....................................................................................................................14
3.6.2 Pinout.............................................................................................................................14
3.7 LVDS interfaces ................................................................................................................15
3.7.1 Introduction....................................................................................................................15
3.7.2 Pinout.............................................................................................................................16
3.8 SD Card ............................................................................................................................17
3.8.1 Introduction....................................................................................................................17
3.8.2 Pinout.............................................................................................................................17
3.9 GPIO.................................................................................................................................18
3.9.1 Introduction....................................................................................................................18
3.9.2 Pinout.............................................................................................................................19
3.10 LED.................................................................................................................................20
3.10.1 Introduction..................................................................................................................20
3.10.2 Pinout...........................................................................................................................20
3.11 Key ..................................................................................................................................21
3.11.1 Introduction .................................................................................................................. 21
3.11.2 Pinout ........................................................................................................................... 21
3.12 Switch .............................................................................................................................21
3.12.1 Introduction..................................................................................................................21
3.12.2 Pinout...........................................................................................................................22
4Gowin Software ...........................................................................................23

List of Figures
DBUG385-1.1E
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List of Figures
Figure 2-1 PCB Components.............................................................................................................5
Figure 2-2 System Architecture.......................................................................................................... 5
Figure 3-1 Connection Diagram of FPGA Download and Configuration ........................................... 9
Figure 3-2 Power System Distribution ............................................................................................... 10
Figure 3-3 Connection Diagram of Clock and Reset .........................................................................11
Figure 3-4 Connection Diagram of FPGA and DDR3 ........................................................................ 12
Figure 3-5 Connection Diagram of FPGA and Ethernet ....................................................................14
Figure 3-6 LVDS TX Interface............................................................................................................ 15
Figure 3-7 LVDS RX Interface ...........................................................................................................16
Figure 3-8 Connection Diagram of SD Card......................................................................................17
Figure 3-9 20 pin Interface.................................................................................................................18
Figure 3-10 30 pin Interface............................................................................................................... 18
Figure 3-11 LED Connection.............................................................................................................. 20
Figure 3-12 GPIO Circuit ................................................................................................................... 21
Figure 3-13 GPIO Circuit ................................................................................................................... 22

List of Tables
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List of Tables
Table 1-1 Abbreviations and Terminology ..........................................................................................1
Table 3-1 FPGA Download and Pinout .............................................................................................. 9
Table 3-2 Clock and Reset Pinout .....................................................................................................11
Table 3-3 DDR3 Pinout ...................................................................................................................... 12
Table 3-4 Ethernet Pinout ..................................................................................................................14
Table 3-5 LVDS TX Interface Pinout ..................................................................................................16
Table 3-6 LVDS RX Interface Pinout.................................................................................................. 16
Table 3-7 20 pin Interface Pinout ....................................................................................................... 19
Table 3-8 30 pin Interface Pinout ....................................................................................................... 19
Table 3-9 LED Pinout .........................................................................................................................20
Table 3-10 Key Pinout........................................................................................................................ 21
Table 3-11 Switch Pinout.................................................................................................................... 22

1 About This Guide
1.1 Purpose
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1About This Guide
1.1 Purpose
The DK_START_GW2A-LV18PG256C8I7_V2.0 development board
(hereinafter referred to as development board) user manual consists of the
following four parts:
A brief introduction to the features and hardware resources of the
development board;
An introduction to the development board architecture and hardware
resources;
An introduction to the hardware circuit functions, circuits, and pins
distribution;
An introduction to the use of the Gowin Software.
1.2 Related Documents
The latest user guides are available on the GOWINSEMI Website. You
can find the related documents at www.gowinsemi.com:
1. DS102, GW2A series of FPGA Products Data Sheet
2. UG110, GW2A-18 Pinout
3. UG111, GW2A series of FPGA Products Package and Pinout
4. SUG100, Gowin Software User Guide
1.3 Abbreviations and Terminology
The abbreviations and terminology used in this manual are set out in
Table 1-1 below.
Table 1-1 Abbreviations and Terminology
Abbreviations and Terminology
Full Name
BSRAM
Block Static Random Access Memory

1 About This Guide
1.4 Support and Feedback
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Abbreviations and Terminology
Full Name
DDR
Double Data Rate
DSP
Digital Signal Processing
FLASH
Flash Memory
FPGA
Field Programmable Gate Array
GPIO
Gowin Programmable I/O
LDO
Low Dropout Regulator
LUT4
4-input Look-up Table
LVDS
Low-Voltage Differential Signaling
SSRAM
Shadow Static Random Access Memory
1.4 Support and Feedback
Gowin Semiconductor provides customers with comprehensive
technical support. If you have any questions, comments, or suggestions,
please feel free to contact us directly using the information provided below.
Website: www.gowinsemi.com
E-mail: [email protected]

2 Development Board Description
2.1 Overview
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2Development Board Description
2.1 Overview
Figure 2-1 DK_START_GW2A-LV18PG256C8I7_V2.0 Development Board
DK_START_GW2A-LV18PG256C8I7_V2.0 development board
applies to high speed data storage, high-speed communication test, FPGA
functions evaluation, the verification of hardware reliability, software
learning and debugging, etc.
The development board uses the GW2A-LV18PG256 FPGA device,
which is the first generation product of Gowin Arora family. The GW2A
series of FPGA products offer a range of comprehensive features and rich
internal resources like high-performance DSP resources, a high-speed
LVDS interface, and abundant BSRAM memory resources. These
embedded resources combine a streamlined FPGA architecture with a
55nm process to make the GW2A series of FPGA products ideal for

2 Development Board Description
2.2 A Development Board Suite
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high-speed and low-cost applications.
DK_START_GW2A-LV18PG256C8I7_V2.0 development board
includes a DDR3 chip with 2Gbit storage space,16-bit data bus width, and
the highest data speed of 1600MT/s. Its two Gigabit Ethernet interfaces
support 10M, 100M, 1000M Ethernet communication. It has abundant
peripheral interfaces, including LVDS interfaces, a SD card slot, and GPIO
interfaces. Besides that, it also offers an external Flash, slide switches, key
switches, external clocks, etc.
2.2 A Development Board Suite
A development board suite includes the following items:
1. DK_START_GW2A-LV18PG256C8I7_V2.0 development board
2. 5V power adaptor (Input: 100-240V~50/60Hz 0.5A, output: DC 5V 2A)
3. USB Mini B cable
Figure 2-2 A Development Board Suite
1
2 3
①DK_START_GW2A-LV18PG256C8I7_V2.0
development board
②5V power adaptor
③USB Mini B cable

2 Development Board Description
2.3 PCB Components
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2.3 PCB Components
Figure 2-1 PCB Components
Alternate Power
1.2V
Power 2.5V
Power 1.0V
Power 1.5V
Power 3.3V
Power
DDR3
Ethernet
Interface Chip*2
Ethernet
Interface*2
Configuration
FLASH
SD Card
Reset Key
External Clock
Key*4
LVDS TX
FPGA
LVDS RX USB-to-
JTAG Chip
Switch*4
Power
Socket
Power
Switch
20PIN
GPIO
30PIN
GPIO
MODE
BANK7
Level
Selection
LED*4
USB
MINI B
2.4 System Architecture
Figure 2-2 System Architecture
DDR3
(2Gbit)
LEDSwitches
Crystal
Oscillator
JTAG
EthernetI
nterface 1
EthernetI
nterface 2
20PIN GPIO
Header
30PIN GPIO
Header
Configure
FLASH
X16
X24
SD Card
X31 X4 X10 X10
X29
X7
X1 X4 X4 X4
X4
Keys
LVDS
TX LVDS RX

2 Development Board Description
2.5 Features
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2.5 Features
The key features of DK_START_GW2A-LV18PG256C8I7_V2.0 are as
follows:
1. The FPGA device
GW2A-LV18PG256C8/I7
Max. user I/O 207
2. Download and Boot
Integrates the download module; can be downloaded with the USB
Mini B cable
External Flash boot
The blue DONE light is on after loading
3. Power
External 5V 2A Power supply
The blue POWER light is on after power on
The development board generates 3.3V, 2.5V, 1.5V, 1.2V, 1.0V,
and 0.75V (required by DDR3)
4. Clock system
50MHz crystal oscillator Input
External signals input
5. Memory device
2Gbit DDR3 SDRAM
64Mbit FLASH
6. Ethernet interface
Two Ethernet interfaces
Supports 10M/100M/1000M
RJ45 connector with built-in transformer
7. LVDS interfaces;
One LVDS interface for receiving, including five pairs of differential
signals.
One LVDS interface for sending, including five pairs of differential
signals.
The receiving/sending functions can be modified by changing the
resistance.
Note！
For the V2.0 development board, J13 needs to be set as 2.5V when LVDS is used.
8. SD card slot

2 Development Board Description
2.5 Features
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Eight contacts, push-push type
Card detection
9. Extension interface
20PIN double row pins, including 16 GPIO, one I/O Bank voltage
(can be adjusted as 3.3V, 2.5V, 1.2V), one 3.3V voltage, one 5V
voltage, and two ground pins.
30PIN double row pins, including 24 GPIO, one 2.5V I/O Bank
voltage, one 3.3V voltage, one 5V voltage, and three ground pins.
Note!
For the V2.0 development board, the BANK0 voltage and BANK1 voltage can be set
as 3.3V or 2.5V using J13.
10. Debugging module
Four keys
Four switches
Four blue LEDs

3 Development Board Circuit
3.1 FPGA Module
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3Development Board Circuit
3.1 FPGA Module
Overview
For the resources of GW2A series of FPGA Products, please refer to
DS102, GW2A series of FPGA Products Data Sheet.
I/O BANK Introduction
For the I/O BANK, package and pinout information, please refer to
UG111, GW2A series of FPGA Products Package and Pinout.
3.2 Download Module
3.2.1 Introduction
The development board offers a USB download interface. You can set
the MODE value to download the programs to the on-chip SRAM or
external Flash. When downloaded to SRAM, the data stream file will be lost
if the device is power down. When downloaded to Flash, the data stream
file will not be lost.
The MODE value configuration:
1. In any modes, you can download the data stream file to the on-chip
SRAM and run it immediately.
2. Set MODE as "011" to download the data stream file to the external
Flash. Set MODE as "000", and when power-on again, the device will
read the FPGA configuration data from the Flash automatically.
The connection diagram for downloading and configuration is as
follows.

3 Development Board Circuit
3.3 Power Supply
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Figure 3-1 Connection Diagram of FPGA Download and Configuration
FLASH_SPI_MISO
FLASH_SPI_MOSI
FLASH_SPI_CS_N
FLASH_SPI_CLK
P10 R10 M9 L10
JTAG_TCK
JTAG_TDO
JTAG_TDI
JTAG_TMS
USB-to-
JTAG Chip
USB_D+
USB_D- C6
A7
A6
B8
Configuration
FLASH
3.2.2 Pinsout
Table 3-1 FPGA Download and Pinout
Signal Name
FPGA Pin No.
BANK
I/O
Description
JTAG_TCK
A7
2
3.3V
JTAG Signal
JTAG_TDO
C6
2
3.3V
JTAG Signal
JTAG_TDI
A6
2
3.3V
JTAG Signal
JTAG_TMS
B8
2
3.3V
JTAG Signal
FLASH_SPI_MISO
P10
3
3.3V
FLASH signal configuration
FLASH_SPI_MOSI
R10
3
3.3V
FLASH signal configuration
FLASH_SPI_CS_N
M9
3
3.3V
FLASH signal configuration
FLASH_SPI_CLK
L10
3
3.3V
FLASH signal configuration
3.3 Power Supply
3.3.1 Introduction
5V power (Input: 100-240V~50/60MHz 0.5A, output: DC +5V 2A) The
development board generates 3.3V, 2.5V, 1.5V, 1.2V, 1.0V, and 0.75V
(required by DDR3).
One redundant power location is reserved on the development board.
A LDO can be wielded to generate 3.3V, 1.5V, and 1.0V. The rated current
is 2A. When the redundant power is used to replace the main power, you
need to take off the main power's magnetic beads to avoid the power
conflicts.

3 Development Board Circuit
3.3 Power Supply
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3.3.2 Power System Distribution
Figure 3-2 Power System Distribution
5V 2A Power
Adaptor
NCP3170
Switch Power
3.3V 3A
NCP3170
Switch Power
1.0V 3A
NCP3170
Switch Power
1.5V 3A
TPS7A7001
LDO
2.5V 2A
TPS7A7001
LDO
1.2V 2A
TPS7A7001
Reserved LDO
3.3V/1.5V/
1.0V 2A
TPS51200
DDR Terminal
Regulator
0.75V
VDDQ & VDD
(DDR3)
VREFDQ & VREFCA
(DDR3)
Pull-up power of singal line
(DDR3)
VCC & VCCPLLL &
VCCPLLR
(FPGA)
VCCO0 & VCCO1 &
VCCO7
(FPGA)
VCCO2 & VCCO3 &
VCCO7 & VCCX
(FPGA)
VCCO4 & VCCO5 &
VCCO6
(FPGA)
VCCO7
(FPGA)
30PIN GPIO
Pin
20PIN GPIO
Pin
Ethernet Interface Chip1
（B50610KML）
Ethernet Interface Chip2
（B50610KML）
USB to JTAG
（FT2232）
Configure FLASH
(W25Q64)
SD Card
Keys & Switches
LED*4
Note！
For the V2.0 development board, the BANK0 voltage and BANK1 voltage can be set as
3.3V or 2.5V using J13.

3 Development Board Circuit
3.4 Clock, Reset
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3.4 Clock, Reset
3.4.1 Introduction
The development board offers a 50MHz oscillator, connecting to the
global clock pins. It also offers a female SMA seat for users to input the
external clock for multiple tests.
The reset circuit adopts keys and dedicated reset chips. After powered
on the device, the reset chip automatically generates a reset signal to reset
the FPGA and Ethernet PHY chip. The 3.3V voltage is monitored in real
time. The reset signal will be generated once an exception occurs. The
reset signal can also be generated via the reset key.
Figure 3-3 Connection Diagram of Clock and Reset
H11
T15
T10
KEY1
50MHz
ADM811
EXT CLK
3.3V
RST_N
CLK_SMA
CLK_G
3.4.2 Pinout
Table 3-2 Clock and Reset Pinout
Signal Name
FPGA Pin No.
BANK
I/O
Description
CLK_G
H11
0
2.5V
50MHz crystal oscillator Input
CLK_SMA
T15
2
3.3V
External clock input
RST_N
T10
3
3.3V
Reset signal, active low
3.5 DDR3
3.5.1 Introduction
The development board includes a DDR3 chip with 2Gbit storage
space, 16 bits data bus width, and the highest data speed of 1600MT/s.

3 Development Board Circuit
3.5 DDR3
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Figure 3-4 Connection Diagram of FPGA and DDR3
DDR3_BA[2..0]
DDR3_A[13..0]
DDR3 SDRAM
2Gbit
DDR3_DQ[15..0]
DDR3_UDQSn
DDR3_LDQSn
DDR3_UDQSp
DDR3_LDQSp
DDR3_UDM
DDR3_LDM
DDR3_CASn
DDR3_RASn
DDR3_WEn
DDR3_ODT
DDR3_CK_EN
DDR3_CSn
DDR3_RSTn
DDR3_CKn
DDR3_CKp
3.5.2 Pinout
Table 3-3 DDR3 Pinout
Signal Name
FPGA Pin No.
BANK
I/O
Description
DDR3_A0
F7
6
1.5V
Address
DDR3_A1
A4
5
1.5V
Address
DDR3_A2
D6
5
1.5V
Address
DDR3_A3
F8
6
1.5V
Address
DDR3_A4
C4
6
1.5V
Address
DDR3_A5
E6
6
1.5V
Address
DDR3_A6
B1
5
1.5V
Address
DDR3_A7
D8
6
1.5V
Address
DDR3_A8
A5
5
1.5V
Address
DDR3_A9
F9
6
1.5V
Address
DDR3_A10
K3
4
1.5V
Address
DDR3_A11
B7
6
1.5V
Address
DDR3_A12
A3
5
1.5V
Address
DDR3_A13
C8
6
1.5V
Address
DDR3_BA0
H4
5
1.5V
Bank address
DDR3_BA1
D3
5
1.5V
Bank address
DDR3_BA2
H5
4
1.5V
Bank address
DDR3_CASn
R6
4
1.5V
Column address

3 Development Board Circuit
3.5 DDR3
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Signal Name
FPGA Pin No.
BANK
I/O
Description
strobe
DDR3_CK_EN
J2
4
1.5V
Clock Enable
DDR3_CKn
J3
5
1.5V
Differential clock
DDR3_CKp
J1
5
1.5V
Differential clock
DDR3_CSn
P5
4
1.5V
Chip select
DDR3_DQ0
G5
5
1.5V
Data
DDR3_DQ1
F5
5
1.5V
Data
DDR3_DQ2
F4
5
1.5V
Data
DDR3_DQ3
F3
5
1.5V
Data
DDR3_DQ4
E2
5
1.5V
Data
DDR3_DQ5
C1
5
1.5V
Data
DDR3_DQ6
E1
5
1.5V
Data
DDR3_DQ7
B3
5
1.5V
Data
DDR3_DQ8
M3
4
1.5V
Data
DDR3_DQ9
K4
4
1.5V
Data
DDR3_DQ10
N2
4
1.5V
Data
DDR3_DQ11
L1
4
1.5V
Data
DDR3_DQ12
P4
4
1.5V
Data
DDR3_DQ13
H3
4
1.5V
Data
DDR3_DQ14
R1
4
1.5V
Data
DDR3_DQ15
M2
4
1.5V
Data
DDR3_LDM
G1
5
1.5V
Data input mask
DDR3_LDQSn
G3
5
1.5V
Data strobe
DDR3_LDQSp
G2
5
1.5V
Data strobe
DDR3_ODT
R3
4
1.5V
On-Die Termination
Enable
DDR3_RASn
R4
4
1.5V
Row address
strobe
DDR3_RSTn
B9
6
1.5V
Reset
DDR3_UDM
K5
4
1.5V
Data input mask
DDR3_UDQSn
K6
4
1.5V
Data strobe
DDR3_UDQSp
J5
4
1.5V
Data strobe
DDR3_WEn
L2
4
1.5V
Write enable