GOWIN GW1NSR Series User manual

GW1NSR series of FPGA Products
Package & Pinout User Guide
UG823-1.5E, 10/18/2022

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Revision History
Date
Version
Description
10/29/2018
1.0E
Initial version published.
12/24/2018
1.1Ｅ
IO bank description updated.
10/15/2019
1.2E
Devices of GW1NSR-4/GW1NSR-4C added.
03/11/2020
1.3E
MG64P package outline updated.
04/16/2020
1.4E
The pin distribution view and pin number of GW1NSR-4/GW1NSR-4C
QN48P updated.
06/30/2020
1.4.1E
The package name of GW1NS-2/2C QN48 (PSRAM embedded) corrected
as QN48P.
10/18/2022
1.5E
GW1NSR-2 and GW1NSR-2C removed.
Pin definitions updated.

Contents
UG823-1.5E
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Contents
Contents ...............................................................................................................i
List of Figures.....................................................................................................ii
List of Tables......................................................................................................iii
1 About This Guide.............................................................................................1
1.1 Purpose .............................................................................................................................. 1
1.2 Related Documents ............................................................................................................1
1.3 Abbreviations and Terminology...........................................................................................1
1.4 Support and Feedback ....................................................................................................... 2
2 Overview...........................................................................................................3
2.1 PB-Free Package ...............................................................................................................3
2.2 Package and Max. User I/O Information ............................................................................ 3
2.3 Power Pin ........................................................................................................................... 4
2.4 Pin Quantity ........................................................................................................................4
2.4.1 Quantity of GW1NSR-4/GW1NSR-4C Pins ....................................................................4
2.5 Pin Definitions.....................................................................................................................5
2.6 I/O BANK Introduction ........................................................................................................ 7
3 View of Pin Distribution ..................................................................................9
3.1 View of GW1NSR-4/GW1NSR-4C Pins Distribution ........................................................10
3.1.1 View of QN48P Pins Distribution ...................................................................................10
3.1.2 View of QN48G Pins Distribution................................................................................... 11
3.1.3 View of GW1NSR-4/GW1NSR-4C MG64P Pins Distribution........................................12
4 Package Diagrams.........................................................................................13
4.1 GW1NSR-4C QN48P/QN48G Package Outline (6mm x 6mm) .......................................14
4.2 GW1NSR-4/GW1NSR-4C MG64P Package Outline (4.2mm x 4.2mm).......................... 15

List of Figures
UG823-1.5E
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List of Figures
Figure 2-1 GW1NSR series I/O Bank Distribution ............................................................................. 7
Figure 3-2 View of GW1NSR-4C QN48P Pins Distribution (Top View) ............................................. 10
Figure 3-3 View of GW1NSR-4C QN48G Pins Distribution (Top View).............................................11
Figure 3-4 View of GW1NSR-4/GW1NSR-4C MG64P Pins Distribution (Top View)......................... 12
Figure 4-2 Package Outline QN48P/QN48G .....................................................................................14
Figure 4-3 Package Outline MG64P..................................................................................................15

List of Tables
UG823-1.5E
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List of Tables
Table 1-1 Abbreviations and Terminology ..........................................................................................1
Table 2-1 Package, Max. User I/O Information, and LVDS Paris ...................................................... 3
Table 2-2 GW1NSR Power Pins ........................................................................................................4
Table 2-4 Quantity of GW1NSR-4/GW1NSR-4C Pins .......................................................................4
Table 2-5 Definition of the Pins in the GW1NSR series of FPGA products ....................................... 5
Table 3-2 Other Pins in GW1NSR-4C QN48P...................................................................................10
Table 3-3 Other Pins in GW1NSR-4C QN48G ..................................................................................11
Table 3-4 Other Pins in GW1NSR-4/GW1NSR-4C MG64P ..............................................................12

1 About This Guide
1.1 Purpose
UG823-1.5E
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1About This Guide
1.1 Purpose
This manual contains an introduction to the GW1NSR series of FPGA
products together with a definition of the pins, list of pin numbers,
distribution of pins, and package diagrams.
1.2 Related Documents
The latest user guides are available on the GOWINSEMI Website. You
can find the related documents at www.gowinsemi.com:
1. DS861, GW1NSR series of FPGA Products Data Sheet
2. UG290, Gowin FPGA Products Programming and Configuration User
Guide
3. UG864, GW1NSR-4 Pinout
4. UG865, GW1NSR-4C Pinout
1.3 Abbreviations and Terminology
The abbreviations and terminology used in this manual are as shown in
Table 1-1 below.
Table 1-1 Abbreviations and Terminology
Abbreviations and Terminology
Full Name
FPGA
Field Programmable Gate Array
MG64P
MBGA64P
QN48G
QFN48G
QN48P
QFN48P

1 About This Guide
1.4 Support and Feedback
UG823-1.5E
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1.4 Support and Feedback
Gowin Semiconductor provides customers with comprehensive
technical support. If you have any questions, comments, or suggestions,
please feel free to contact us directly using the information provided below.
Website: www.gowinsemi.com
E-mail: [email protected]

2 Overview
2.1 PB-Free Package
UG823-1.5E
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2Overview
GW1NSR series of FPGA products are the first-generation products in
the LittleBee family. They integrate with PSRAM based on the GW1NS
series. When the ARM Cortex-M3 hard-core processor is employed as the
core, the needs of the Min. memory can be met. FPGA logic resources and
other embedded resources can flexibly facilitate the peripheral control
functions, which provide excellent calculation functions and exceptional
system response interrupts. They also offer high performance, low power
consumption, a small number of pins, flexible usage, instant start-up,
affordability, nonvolatile, high security, and abundant package types,
among other benefits. GW1NSR series of SoC FPFA products achieve
seamless connection between programmable logic devices and embedded
processors. They are compatible with multiple peripheral device standards
and can, therefore, reduce costs of operation and be widely deployed in
industrial control, communication, Internet of Things, servo drive,
consumption fields, etc.
2.1 PB-Free Package
The GW1NSR series of FPGA products are PB free in line with the EU
ROHS environmental directives. The substances used in the GW1NSR
series of FPGA products are in full compliance with the IPC-1752
standards.
2.2 Package and Max. User I/O Information
Table 2-1 Package, Max. User I/O Information, and LVDS Paris
Package
Pitch(mm)
Size (mm)
GW1NSR-4
GW1NSR-4C
QN48P
0.4
6 x 6
-
39(4)
MG64P
0.5
4.2 x 4.2
55(8)
55(8)
QN48G
0.4
6 x 6
-
39(4)
Note!
In this manual, abbreviations are employed to refer to the package types. See 1.3
Abbreviations and Terminology.
The JTAGSEL_N and JTAG pins cannot be used as I/O simultaneously. The data in
this table is when the loaded four JTAG pins (TCK, TDI, TDO, and TMS) are used as
I/O; When mode [2:0] = 001, JTAGSEL_N and the four JTAG pins (TCK, TDI, TDO,
and TMS) can be used as GPIO simultaneously, and the Max. user I/O plus one.

2 Overview
2.3 Power Pin
UG823-1.5E
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2.3 Power Pin
Table 2-2 GW1NSR Power Pins
VCC
VCCO0
VCCO1
VCCO2
VCCO3
VCCX
VSS
NC
VCCPLL
VCCP
VDDA
–
2.4 Pin Quantity
2.4.1 Quantity of GW1NSR-4/GW1NSR-4C Pins
Table 2-3 Quantity of GW1NSR-4/GW1NSR-4C Pins
Pin Type
GW1NSR-4/GW1NSR-4C
QN48P
(GW1NSR-4C)
QN48G
(GW1NSR-4C)
MG64P
I/O Single end/
Differential
pair/LVDS[1
BANK0
8/3/0
8/3/0
9/4/0
BANK1
10/5/0
10/5/0
28/14/0
BANK2
9/4/4
9/4/4
18/9/8
BANK3
11/5/0
11/5/0
0/0/0
Max. User I/O[2]
38
38
55
Differential Pair
17
17
37
True LVDS Output
4
4
8
VCC
2
2
1
VCCX
1
1
1
VCCO0
1
1
1
VCCO1
1
1
1
VCCO2
1
1
1
VCCO3
2
2
1
VSS
1
1
2
MODE0
0
0
0
MODE1
0
0
0
MODE2
0
0
0
MODE1/MODE2[3]
1
1
0
JTAGSEL_N
1
1
1
Note!
[1] Single end/ Differential I/O quantity include CLK pins, and download pins;
[2] The JTAGSEL_N and JTAG pins cannot be used as I/O simultaneously. The data
in this table is when the loaded four JTAG pins (TCK, TDI, TDO, and TMS) are used
as I/O;
[3] Pin multiplexing.