GOWIN DK START GW1N-LV9EQ144C6I5 V2.1 User manual

DK_START_GW1N-LV9EQ144C6I5_V2.1
User Guide
DBUG392-1.0E, 07/21/2021

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, Gowin, and GOWINSEMI are trademarks of Guangdong Gowin Semiconductor
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Disclaimer
GOWINSEMI assumes no liability and provides no warranty (either expressed or implied)
and is not responsible for any damage incurred to your hardware, software, data, or
property resulting from usage of the materials or intellectual property except as outlined in
the GOWINSEMI Terms and Conditions of Sale. All information in this document should be
treated as preliminary. GOWINSEMI may make changes to this document at any time
without prior notice. Anyone relying on this documentation should contact GOWINSEMI for
the current documentation and errata.

Revision History
Date
Version
Description
07/21/2021
1.0E
Initial version published.

Contents
DBUG392-1.0E
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Contents
Contents ...............................................................................................................i
List of Figures....................................................................................................iii
List of Tables......................................................................................................iv
1 About This Guide.............................................................................................1
1.1 Purpose .............................................................................................................................. 1
1.2 Related Documents ............................................................................................................1
1.3 Terminology and Abbreviations...........................................................................................1
1.4 Support and Feedback ....................................................................................................... 2
2 Introduction......................................................................................................3
2.1 Overview.............................................................................................................................3
2.2 Development Kit ................................................................................................................. 4
2.3 PCB Components ...............................................................................................................5
2.4 System Block Diagram ....................................................................................................... 5
2.5 Features.............................................................................................................................. 6
2.6 Development Board Description.........................................................................................7
3 Development Board Circuit ............................................................................9
3.1 FPGA Module .....................................................................................................................9
Overview ................................................................................................................................... 9
I/O BANK Introduction ..............................................................................................................9
3.2 Download............................................................................................................................9
3.2.1 Overview..........................................................................................................................9
3.2.2 USB Download Circuit ...................................................................................................10
3.2.3 Download Flow ..............................................................................................................10
3.2.4 Pinout............................................................................................................................. 10
3.3 Power Supply.................................................................................................................... 10
3.3.1 Overview........................................................................................................................10
3.3.2 Power System Distribution ............................................................................................ 11

Contents
DBUG392-1.0E
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3.3.3 Pins Distribution............................................................................................................. 11
3.4 Clock .................................................................................................................................12
3.4.1 Overview........................................................................................................................12
3.4.2 Clock ..............................................................................................................................12
3.4.3 Pinout............................................................................................................................. 12
3.5 LED ...................................................................................................................................12
3.5.1 Overview........................................................................................................................12
3.5.2 LED Circuit..................................................................................................................... 13
3.5.3 Pinout............................................................................................................................. 13
3.6 Switches ...........................................................................................................................13
3.6.1 Overview........................................................................................................................13
3.6.2 Switch Circuit .................................................................................................................13
3.6.3 Pinout............................................................................................................................. 14
3.7 Key....................................................................................................................................14
3.7.1 Overview........................................................................................................................14
3.7.2 Key Circuit .....................................................................................................................14
3.7.3 Pinout............................................................................................................................. 14
3.8 GPIO .................................................................................................................................15
3.8.1 Overview........................................................................................................................15
3.8.2 GPIO Circuit................................................................................................................... 15
3.8.3 Pinout............................................................................................................................. 16
3.9 MIPI/LVDS ........................................................................................................................18
3.9.1 Overview........................................................................................................................18
3.9.2 MIPI/LVDS Circuit ..........................................................................................................18
3.9.3 Pinout............................................................................................................................. 19
4 Consideration ................................................................................................22
5 Gowin Software..............................................................................................23

List of Figures
DBUG392-1.0E
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List of Figures
Figure 2-1 DK_START_GW1N-LV9EQ144C6I5_V2.1 Development Board...................................... 3
Figure 2-2 A Development Kit ............................................................................................................ 4
Figure 2-3 PCB Components............................................................................................................. 5
Figure 2-4 System Block Diagram .....................................................................................................5
Figure 3-1 FPGA USB Download Diagram........................................................................................10
Figure 3-2 Power System Distribution ............................................................................................... 11
Figure 3-3 Clock Circuit .....................................................................................................................12
Figure 3-4 LED Circuit .......................................................................................................................13
Figure 3-5 Switch Circuit.................................................................................................................... 13
Figure 3-6 Key Circuit Diagram..........................................................................................................14
Figure 3-7 GPIO Circuit .....................................................................................................................15
Figure 3-8 MIPI/LVDS Circuit.............................................................................................................18

List of Tables
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List of Tables
Table 1-1 Terminology and Abbreviations .......................................................................................... 1
Table 2-1 Development Board Description ........................................................................................ 7
Table 3-1 FPGA Download Pinout .....................................................................................................10
Table 3-2 FPGA Power Pinout ...........................................................................................................11
Table 3-3 FPGA Clock Pinout ............................................................................................................ 12
Table 3-4 LED Pinout .........................................................................................................................13
Table 3-5 Switch Circuit Pinout ..........................................................................................................14
Table 3-6 Key Circuit Pinout...............................................................................................................14
Table 3-7 J14 GPIO Pinout ................................................................................................................16
Table 3-8 J13 GPIO Pinout ................................................................................................................16
Table 3-9 J15 FPGA Pinout (IDES 16: 1 Supported) .........................................................................19
Table 3-10 J16 FPGA Pinout (IDES 16: 1 Supported) ....................................................................... 20
Table 3-11 J18 FPGA Pinout (IDES 16: 1 Supported) ....................................................................... 21

1 About This Guide
1.1 Purpose
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1About This Guide
1.1 Purpose
The DK_START_GW1N-LV9EQ144C6I5_V2.1 user manual consists
of the following four parts:
1. A brief introduction to the features and hardware resources of the
development board;
2. An introduction to the function, circuit, and pinout of each module;
3. Considerations for the use of development board;
4. An introduction to the usage of the FPGA development software.
1.2 Related Documents
The latest user guides are available on the GOWINSEMI Website. You
can find the related documents at www.gowinsemi.com:
1. DS100, GW1N series of FPGA Products Data Sheet
2. UG103, GW1N series of FPGA Products Package and Pinout Manual
3. UG801, GW1N-9 Pinout
4. UG290, Gowin FPGA Products Programming and Configuration Guide
5. SUG100, Gowin Software User Guide
1.3 Terminology and Abbreviations
The terminology and abbreviations used in this manual are as shown
in Table 1-1.
Table 1-1 Terminology and Abbreviations
Terminology and Abbreviations
Meaning
FPGA
Field Programmable Gate Array

1 About This Guide
1.4 Support and Feedback
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Terminology and Abbreviations
Meaning
SIP
System in Package
SDRAM
Synchronous Dynamic RAM
PSRAM
Pseudo static random access memory
CFU
Configurable Function Unit
CLS
Configurable Logic Slice
CRU
Configurable Routing Unit
LUT4
4-input Look-up Tables
LUT5
5-input Look-up Tables
LUT6
6-input Look-up Tables
LUT7
7-input Look-up Tables
LUT8
8-input Look-up Tables
REG
Register
ALU
Arithmetic Logic Unit
IOB
Input/Output Block
SSRAM
Shadow Static Random Access Memory
BSRAM
Block Static Random Access Memory
SP
Single Port
SDP
Semi Dual Port
DP
Dual Port
DSP
Digital Signal Processing
DQCE
Dynamic Quadrant Clock Enable
DCS
Dynamic Clock Selector
PLL
Phase-locked Loop
DLL
Delay-locked Loop
EQ144
EQFP144 package
1.4 Support and Feedback
Gowin Semiconductor provides customers with comprehensive
technical support. If you have any questions, comments, or suggestions,
please feel free to contact us directly by the following ways.
Website: www.gowinsemi.com
E-mail: [email protected]

2 Introduction
2.1 Overview
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2Introduction
2.1 Overview
Figure 2-1 DK_START_GW1N-LV9EQ144C6I5_V2.1 Development Board
The development board uses Gowin GW1N-9 FPGA devices. The
GW1N series of FPGA products are the first generation of the Gowin
LittleBee® family and it is an SIP chip. It has the characteristics of low
power consumption, instant-start, low cost, non-volatility, high security, rich
packages, convenient and flexible usage, etc., which can effectively reduce
the learning cost and help users quickly enter the design and development
field of programmable logic devices.
The development board offers abundant external interfaces, including
MIPI/LVDS interfaces, GPIO interfaces, etc. There are also sliding switch,
button switch, LED, clock, reset and other resources for developers or fans
to learn to use.

2 Introduction
2.2 Development Kit
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2.2 Development Kit
A development board suite includes the following items:
DK_START_GW1N-LV9EQ144C6I5_V2.1 development board
USB Data Line
Figure 2-2 A Development Kit
2
1
①DK_START_GW1N-LV9EQ144C6I5_V2.1
development board
②USB Data Line

2 Introduction
2.3 PCB Components
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2.3 PCB Components
Figure 2-3 PCB Components
2.4 System Block Diagram
Figure 2-4 System Block Diagram
4*LED2*SWITCH
OSC
50MHz
5Pairs
LVDS/MIPI
INPUT
2*BUTTON
10Pairs
LVDS/MIPI
OUTPUT
20PIN
GPIO
FPGA
Mini USB Interface
40PIN
GPIO
GW1N-
LV9EQ144C6/I5
5V LDO
1.2V/2.5V/3.3V

2 Introduction
2.5 Features
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2.5 Features
The structure and features of the development board are as follows:
1. FPGA
EQFP144 package
Up to 120 user I/O
Embedded flash, data not easily lost if power down
Abundant LUT4 resources
Multiple modes and capacities of B-SRAM
2. FPGA Configuration Modes
JTAG
AUTO BOOT
3. Clock resource
50MHz Clock Crystal Oscillator
4. Key switch and slide switch
Two key switches
Two slide switches
5. LED
One power indicator (green)
One DONE indicator (green)
Four LEDs (green)
6. Memory
1Mbit embedded Flash
7. MIPI/LVDS
5 pairs of MIPI/LVDS differential input; 10 pairs of MIPI/LVDS
differential output
8. GPIO
55 I/O expansion resources
9. LDO Power
Supports 3.3 V, 2.5 V, and1.2V.

2 Introduction
2.6 Development Board Description
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2.6 Development Board Description
Table 2-1 Development Board Description
No.
Name
Functional Description
Technical Condition
Note
1
FPGA
Core chip
–
–
2
Download
Support an USB
interface; Support
JTAG, AUTOBOOT
USB to JTAG chip integrated
on board
–
3
Power
Supply
3.3 V, 2.5V, and 1.2 V
output via LDO circuit
Input power: 5V
Provide power for FPGA,
download circuit and
other circuits via 5V to
3.3 V circuit;
Provide power for FPGA
via 5V to 2.5V circuit;
Provide power for FPGA
via 5 V–1.2 V circuit.
–
4
Switches
Available for testing
2
–
5
Key
Switches
Available for testing
2
–
6
LED
Test indicator, DONE
indicator, Power
indicator
Four Test indicators,
green
One DONE indicator,
green
One Power indicator,
green
–
7
Crystal
Oscillator
Provide 50MHz clock
for FPGA
Package5032
–
8
Memory
Provides abundant
Flash for design
1Mbit embedded Flash
–
9
GPIO
I/O for user to extend
and test
55
–
10
MIPI/LVDS
MIPI/LVDS, used for
testing
Five pairs of input, Ten pairs
of output
–
11
Protection
USB interface: ESD
protection
USB interface with ESD
protection: ±15kV
non-contact discharge and ±
8kV contact discharge;
–
12
Voltage
–
Input Voltage: 5V
–

2 Introduction
2.6 Development Board Description
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No.
Name
Functional Description
Technical Condition
Note
13
Humidity
–
95%
–
14
Temperature
–
Operating range: –20°~70°
–

3 Development Board Circuit
3.1 FPGA Module
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3Development Board Circuit
3.1 FPGA Module
Overview
For the resources of GW1N series of FPGA Products, see DS100,
GW1N Series of FPGA Products Data Sheet.
I/O BANK Introduction
For the I/O BANK, package, and pinout information, see UG103,
GW1N Series of FPGA Products Package and Pinout User Guide.
3.2 Download
3.2.1 Overview
The development board provides an USB download interface. The
bitstream file can be downloaded to the internal SRAM, or internal flash as
needed.
Note!
When downloaded to SRAM, the bitstream file will be lost if the device is powered
down, and it will need to be downloaded again after power-on.
If downloaded to flash, the bitstream file will not be lost if the device is powered down.

3 Development Board Circuit
3.3 Power Supply
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3.2.2 USB Download Circuit
Figure 3-1 FPGA USB Download Diagram
TMS_FTDI
TCK_FTDI
TDI_FTDI
TDO_FTDI
USB-to-JTAG
Chip
USB_D+
USB_D- 14
13
16
18
U1
U17
GW1N-
LV9EQ144C6I5
3.2.3 Download Flow
Please plug USB download cable into the USB interface (J6) of the
development board to download FPGA, and then open Programmer, click
SRAM mode or Embedded flash mode to download bit stream file to SRAM
or flash.
3.2.4 Pinout
Table 3-1 FPGA Download Pinout
Name
Pin No.
BANK
Description
I/O Level
TMS_FTDI
13
3
JTAG Signal
3.3V
TCK_ FTDI
14
3
JTAG Signal
3.3V
TDI_ FTDI
16
3
JTAG Signal
3.3V
TDO_ FTDI
18
3
JTAG Signal
3.3V
MODE0
144
3
Mode selection pin
3.3V
MODE1
143
3
Mode selection pin
3.3V
RECONFIG_N
20
3
RECONFIG_N
3.3V
DONE
21
3
DONE indicator
3.3V
READY
22
3
READY
3.3V
3.3 Power Supply
3.3.1 Overview
DC5V is input by USB interface. The TI LDO power supply chip is used
to step down voltage from 5V to 3.3V, 1.8V, and 1.2V, which can meet the
power demand of the development board.

3 Development Board Circuit
3.3 Power Supply
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3.3.2 Power System Distribution
Figure 3-2 Power System Distribution
USB
Interface
DC 5V Input
TPS7A7001
LDO
1.2V
TPS7A7001
LDO
3.3V
TPS7A7001
LDO
2.5V
USB-to-JTAG
（FT2232）
Key & LED& Reset
&
Switch & VCCO3
FPGA VCCO2
(LVDS)
FPGA VCCX &
VCCO0
& VCCO1
FPGA VCC
FPGA VCCO2 &
VCCO0
& VCCO1
(MIPI)
3.3.3 Pins Distribution
Table 3-2 FPGA Power Pinout
Name
Pin No.
BANK
Description
I/O Level
VCCO0
109, 127
0
I/O Bank Voltage
2.5V/1.2V
VCCO1
91, 103
1
I/O Bank Voltage
2.5V/1.2V
VCCO2
37, 55
2
I/O Bank Voltage
2.5V/1.2V
VCCO3
5, 19
3
I/O Bank Voltage
3.3V
VCCX
31、77
-
Auxiliary voltage
2.5V
VCC
1, 36, 73, 108
-
Core voltage
1.2V
VSS
2, 17, 33, 35, 53,
74, 89, 105, 107
-
GND
-

3 Development Board Circuit
3.4 Clock
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3.4 Clock
3.4.1 Overview
The development board provides a 50MHz crystal oscillator connected
to the PLL input pin. This can be employed as the input clock for the PLL in
FPGA. Frequency division and multiplication of PLL can provide clocks
required by users.
3.4.2 Clock
Figure 3-3 Clock Circuit
106
FPGA_CLK
U1
X2
GW1N-
LV9EQ144C6I5
3.4.3 Pinout
Table 3-3 FPGA Clock Pinout
Name
Pin No.
BANK
Description
I/O Level
FPGA_CLK
106
1
50MHz crystal oscillator input
2.5V/1.2V
3.5 LED
3.5.1 Overview
There are four green LEDs in the development board and users can
display the required status through the LED. In addition, two LEDs are
reserved to signify the power supply and FPGA loading status.
You can test the LEDs in the following ways:
When the FPGA corresponding pin output signal is logic low, the LED is
lit;
If the signal is high, LED is off.

3 Development Board Circuit
3.6 Switches
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3.5.2 LED Circuit
Figure 3-4 LED Circuit
LED1 100
LED2 101
LED3 102
LED4 104
VCC2P5
F_LED1
F_LED2
F_LED3
F_LED4
U1
GW1N-
LV9EQ144C6I5
3.5.3 Pinout
Table 3-4 LED Pinout
Name
Pin No.
BANK
Description
I/O Level
F_LED1
100
1
LED1
2.5V/1.2V
F_LED2
101
1
LED2
2.5V/1.2V
F_LED3
102
1
LED3
2.5V/1.2V
F_LED4
104
1
LED 4
2.5V/1.2V
3.6 Switches
3.6.1 Overview
Two Slide switches are incorporated into the development board.
These are used to control input during testing.
3.6.2 Switch Circuit
Figure 3-5 Switch Circuit
SW195
VCC2P5/
VCC1P2
U1
F_SW1
GW1N-
LV9EQ144C6I5
SW294
F_SW2