GOWIN Arora V 138K User manual

Arora Ⅴ138K FPGA Product
Programming and Configuration
Guide
UG704-1.0.2E, 10/31/2023

Copyright © 2023 Guangdong Gowin Semiconductor Corporation. All Rights Reserved.
is the trademark of Guangdong Gowin Semiconductor Corporation and is
registered in China, the U.S. Patent and Trademark Office, and other countries. All other
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the prior written consent of GOWINSEMI.
Disclaimer
GOWINSEMI assumes no liability and provides no warranty (either expressed or implied)
and is not responsible for any damage incurred to your hardware, software, data, or
property resulting from usage of the materials or intellectual property except as outlined in
the GOWINSEMI Terms and Conditions of Sale. GOWINSEMI may make changes to this
document at any time without prior notice. Anyone relying on this documentation should
contact GOWINSEMI for the current documentation and errata.

Revision History
Date
Version
Description
04/20/2023
1.0E
Initial version published.
05/06/2023
1.0.1E
The pin “DIN” updated to “MISO” in MSPI mode.
10/31/2023
1.0.2E
The formula for calculating the loading time of the
configuration file fixed.
IDCODE and POR Rails for GW5A-138 and GW5AS-
138 added.
25K configuration information removed.

Contents
UG704-1.0.2E
i
Contents
Contents .......................................................................................................................i
List of Figures ............................................................................................................iii
List of Tables ..............................................................................................................v
1 About This Guide ....................................................................................................1
1.1 Purpose...................................................................................................................................... 1
1.2 Related Documents ................................................................................................................... 1
1.3 Terminology and Abbreviations ..................................................................................................1
1.4 Support and Feedback............................................................................................................... 2
2 Glossary ..................................................................................................................3
3 Configuration Interfaces ........................................................................................5
3.1 Configuration Modes.................................................................................................................. 5
3.2 Configuration Pins......................................................................................................................6
3.3 Configuration Clock for Master Modes ....................................................................................13
3.4 JTAG Configuration Mode........................................................................................................ 14
3.4.1 Connection Diagram for the JTAG Configuration Mode .......................................................14
3.4.2 JTAG Configuration Timing...................................................................................................15
3.4.3 JTAG Configuration Process.................................................................................................15
3.5 SSPI.........................................................................................................................................27
3.5.1 Connection Diagram for SSPI Configuration Mode ..............................................................27
3.5.2 SSPI Configuration Timing....................................................................................................28
3.5.3 SSPI Configuration Instructions............................................................................................29
3.5.4 SRAM Configuration via SSPI ..............................................................................................32
3.5.5 Flash Programming via SSPI................................................................................................33
3.5.6 SRAM Configuration via SSPIx4 ..........................................................................................34
3.6 MSPI ........................................................................................................................................35
3.6.1 Connection Diagram for MSPI Configuration Mode .............................................................35
3.6.2 MSPI Configuration Timing ...................................................................................................37
3.6.3 MSPI .....................................................................................................................................37
3.7 CPU Configuration Mode .........................................................................................................39
3.7.1 Connection Diagram for CPU Configuration Mode...............................................................39
3.7.2 Configuration Timing.............................................................................................................40
3.7.3 Continuous Data Loading .....................................................................................................41
3.7.4 Non-continuous Data Loading ..............................................................................................41

Contents
UG704-1.0.2E
ii
3.8 SERIAL ....................................................................................................................................41
3.8.1 Connection Diagram for SERIAL Configuration Mode..........................................................42
3.9 Daisy Chain..............................................................................................................................43
3.9.1 Serial Daisy Chain ................................................................................................................43
3.9.2 Parallel Daisy Chain..............................................................................................................44
4 Configuration Details............................................................................................45
4.1 Configuration Notes .................................................................................................................45
4.2 Configuration Sequence ..........................................................................................................48
4.2.1 Power-Up Timing ..................................................................................................................49
4.2.2 Initialization ........................................................................................................................... 49
4.2.3 Configuration.........................................................................................................................50
4.2.4 Wake-up................................................................................................................................50
4.2.5 User Modes...........................................................................................................................50
4.3 Safety Precautions................................................................................................................... 51
4.4 Bitstream File Configuration ....................................................................................................52
4.4.1 Configuration Options ...........................................................................................................52
4.4.2 Configure Data Encryption....................................................................................................53
4.4.3 Configuration File Size..........................................................................................................62
4.4.4 Configuration File Loading Time ...........................................................................................63
4.5 SPI Flash Selection.................................................................................................................. 64
5 Status Register and Efuse Definition ..................................................................65
5.1 Status Register ........................................................................................................................ 65
5.2 OTP Efuse................................................................................................................................ 67
6 Multi Boot and Background Update ....................................................................68
6.1 Multi Boot Process ...................................................................................................................68
6.2 Background Upgrade and Hotboot .......................................................................................... 70

List of Figures
UG704-1.0.2E
iii
List of Figures
Figure 3-1 Configuring Pin Reuse...................................................................................................... 13
Figure 3-2 Configuration Clock Structure in Master Modes...............................................................13
Figure 3-3 Connection Diagram for JTAG Configuration Mode.........................................................14
Figure 3-4 Connection Diagram of JTAG Programming External Flash............................................ 14
Figure 3-5 JTAG Configuration timing................................................................................................15
Figure 3-6 TAP State Machine...........................................................................................................16
Figure 3-7 Instruction Register Access Timing ..................................................................................17
Figure 3-8 Data Register Access Timing ...........................................................................................18
Figure 3-9 Flow Chart of Reading ID Code State Machine ............................................................... 19
Figure 3-10 Access Timing of Reading ID Code Instruction-0x11 .....................................................20
Figure 3-11 Access Timing of Reading ID Code Data Register .........................................................20
Figure 3-12 SRAM Configuration Flow ........................................................................................... 22
Figure 3-13 Process View of Programming SPI Flash ......................................................................23
Figure 3-14 Timing diagram of JTAG-SPI Sending 0x06 (Arora series) ......................................... 24
Figure 3-15 Process of Program ming Flash in SVF Mode ............................................................... 24
Figure 3-16 OTP Configuration Flow ................................................................................................. 25
Figure 3-17 Process of reading OTP ................................................................................................. 26
Figure 3-18 SSPI Configuration Mode Connection Diagram..................................................................27
Figure 3-19 Multiple FPGA Connection Diagram...............................................................................27
Figure 3-20 Connection Diagram of Programming External Flash via SSPI.....................................28
Figure 3-21 SSPI Configuration Timing ............................................................................................. 28
Figure 3-22 Read ID Code Timing ..................................................................................................... 30
Figure 3-23 Write Enable (0x15) Timing ............................................................................................ 30
Figure 3-24 Write Disable(0x3A00) Timing........................................................................................ 30
Figure 3-25 Write Data (0x3B) Timing ...............................................................................................31
Figure 3-26 The Flow Chart of SRAM Configuration via SSPI .......................................................... 32
Figure 3-27 The Flow Chart of Flash Configuration via SSPI............................................................ 33
Figure 3-28 The Flow Chart of SRAM Configuration via QSSPI .......................................................34
Figure 3-29 QSSPI Write Data (0x6B) Timing ................................................................................... 35
Figure 3-30 Connection Diagram for MSPIx1 Configuration Mode ................................................... 35
Figure 3-31 Connection Diagram for MSPIx2 Configuration Mode ................................................... 36
Figure 3-32 Connection Diagram for MSPIx4 Configuration Mode ................................................... 36

List of Figures
UG704-1.0.2E
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Figure 3-33 MSPI Configuration Timing.............................................................................................37
Figure 3-34 The Flow Chart of MSPI Mode .......................................................................................38
Figure 3-35 Connection Diagram for CPU Mode...............................................................................39
Figure 3-36 CPU Mode Configuration Timing.................................................................................... 40
Figure 3-37 Continuous Data Loading Timing ................................................................................... 41
Figure 3-38 Non Continuous Data Loading Timing............................................................................41
Figure 3-39 Connection Diagram for SERIAL Mode..........................................................................42
Figure 3-40 SERIAL Configuration Timing.........................................................................................42
Figure 3-41 Diagram of Daisy-Chain ................................................................................................. 43
Figure 3-42 Diagram of Parallel Daisy-Chain..................................................................................44
Figure 4-1 Process of Power on ........................................................................................................45
Figure 4-2 Power Recycle Timing......................................................................................................46
Figure 4-3 Trigger Timing................................................................................................................... 46
Figure 4-4 GOWINSEMI FPGA Configuration Process .....................................................................48
Figure 4-5 POR Timing ...................................................................................................................... 49
Figure 4-6 Configuration Options....................................................................................................... 53
Figure 4-7 Encryption Key Setting Method ........................................................................................54
Figure 4-8 Setting the Decryption Key............................................................................................... 55
Figure 4-9 AES Security Configuration .............................................................................................. 56
Figure 4-10 Prepare...........................................................................................................................57
Figure 4-11 Read AES Key Flow .......................................................................................................58
Figure 4-12 Program AES Key Flow..................................................................................................59
Figure 4-13 Program AES Key2 Flow................................................................................................60
Figure 4-14 Lock AES Key Flow ........................................................................................................ 61
Figure 4-15 Bitstream Format generation.......................................................................................... 62
Figure 4-16 Process of Power on ......................................................................................................63
Figure 6-1 Multi-Configuration Flow...................................................................................................69

List of Tables
UG704-1.0.2E
v
List of Tables
Table 1-1 Terminology and Abbreviations .......................................................................................... 1
Table 2-1 Glossary .............................................................................................................................3
Table 3-1 Configuration Modes .......................................................................................................... 5
Table 3-2 Configuration Pin List (1 of 2) ............................................................................................ 6
Table 3-3 Configuration Pin List (2 of 2) ............................................................................................ 7
Table 3-4 Pin Definitions ....................................................................................................................8
Table 3-5 Pin Reuse Options ............................................................................................................. 11
Table 3-6 JTAG Configuration Timing Parameters ............................................................................15
Table 3-7 Arora V 138K FPGA IDCODE............................................................................................18
Table 3-8 Change of TDI and TMS Value in The Process of Sending Instructions ...........................19
Table 3-9 SSPI Configuration Timing Parameters .............................................................................29
Table 3-10 Configuration Instruction .................................................................................................. 29
Table 3-11 MSPI Configuration Timing Parameters........................................................................... 37
Table 3-12 CPU Configuration Timing Parameters............................................................................ 40
Table 3-13 SERIAL Configuration Timing Parameters.......................................................................42
Table 4-1 Timing Parameters of Power on Again and RECONFIG_N triggering for Arora Ⅴ FPGA
Products .............................................................................................................................................47
Table 4-2 Power Rails ........................................................................................................................49
Table 4-3 Arora Ⅴ series of FPGA Products Configuration File Size (Max.) ...................................... 62
Table 4-4 Loading Time in MSPI Mode.............................................................................................. 63
Table 4-5 SPI Flash Operation Instruction .........................................................................................64
Table 5-1 Status Register...................................................................................................................65
Table 5-3 OTP Definiton.....................................................................................................................67

1 About This Guide
1.1 Purpose
UG704-1.0.2E
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1About This Guide
1.1 Purpose
This guide mainly introduces general features and functions on
programming and configuration of Arora V FPGA products. It helps users
to use Gowin® FPGA products to their full potential.
1.2 Related Documents
The latest user guides are available on the GOWINSEMI website. You
can find the related documents at www.gowinsemi.com:
DS981, GW5AT series of FPGA Products Data Sheet
DS1103, GW5A series of FPGA Products Data Sheet
DS1104, GW5AST series of FPGA Products Data Sheet
DS1114, GW5AS-138 Data Sheet
UG982, GW5AT-138 Pinout
UG988, GW5A-138 Pinout
UG986, GW5AST-138 Pinout
UG1107, GW5AS-138 Pinout
1.3 Terminology and Abbreviations
The terminology and abbreviations used in this manual are as shown
in Table 1-1.
Table 1-1 Terminology and Abbreviations
Terminology and Abbreviations
Description
Background Programming
Programs the on-chip Flash without affecting
the current functions and I/O state.
Bitstream
The data of configuring the FPGA SRAM
Bscan
Boundary Scan
Configuration
The process of configuring the FPGA SRAM
area
CPU
Central Processing Unit
CRC
Cyclic Redundancy Check

1 About This Guide
1.4 Support and Feedback
UG704-1.0.2E
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Terminology and Abbreviations
Description
Edit Mode
The FPGA in Configuration mode or
Programming mode
EFlash/EmbFlash
Internal Flash Memory
FPGA
Field Programmable Gate Array
FS file
ASCII file including the configuration data
GPIO
General Purpose Input Output
I2C（I2C, IIC）
I2C
ID
Identification
IEEE
Institute of Electrical and Electronics Engineers
Internal Flash
Same with Embedded Flash
JTAG
Joint Test Action Group
LSB
Least Significant Bit (priority)
LUT
Look-up Table
MSB
Most Significant Bit (priority)
MSPI
Master Serial Peripheral Interface
Programming
The process of programming the Configuration
Data to the Embedded Flash or the External
Flash memory
SCL
Serial Clock
SDA
Serial Data
Security Bit
Security Bit (readback the SRAM to keep high
level)
SPI
Serial Peripheral Interface
SRAM
Static Random Access Memory
SSPI
Slave Serial Peripheral Interface
TAP
Test Access Port
User Mode
The corresponding logical function modes that
FPGA executes after the programming or
configuration is complete.
1.4 Support and Feedback
Gowin Semiconductor provides customers with comprehensive
technical support. If you have any questions, comments, or suggestions,
please feel free to contact us directly by the following ways.
Website: www.gowinsemi.com
E-mail: [email protected]

2 Glossary
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2Glossary
This chapter presents an overview of the terms that are commonly
used in the process of programming and configuring GOWIN FPGA
products to help users get familiar with the related concepts.
Table 2-1 Glossary
Glossary
Meaning
Program
Write the bitstream data generated by Gowin Software to the embedded
Flash or external SPI Flash of FPGA.
Configure
Load the bitstream data generated by Gowin software to the FPGA
SRAM via external interfaces or embedded Flash.
MODE[2:0]
A representation of the three MODE pin values associated with
GowinCONFIG.
MSPI
As a master device, FPGA is configured by reading bitstream from the
external Flash via SPI interface automatically.
SSPI Configuration
FPGA as a slave device, the bitstream data is written into the FPGA via
the SPI interface by the external master.
SERIAL Configuration
FPGA as a slave device, the bitstream data is written into the FPGA via
the serial interface by the external master.
CPU Configuration
FPGA as a slave device, the bitstream data is written into the FPGA via
the parallel interface (8-bit) by the external master.
MULTI BOOT
The derivative concept of MSPI refers to that FPGA reads bitstream data
from different addresses of external Flash. The loading address of the
latter bitstream data is written in previous bitstream data and the
configuration is completed by triggering RECONFIG_N to switch the data
stream file under the condition that the device power is on. All FPGA
products that support MSPI support this mode.
Remote Upgrade
After a FPGA starts to work, if an upgrade is required, first write bitstream
data to an embedded or external Flash through remote operation, and
then the FPGA reads the external Flash by triggering RECONFIG_N or
powering up again to complete the configuration.
Daisy Chain
FPGA devices are connected sequentially in a serial way. Devices can be
configured from the head of the chain in sequence according to the
connection order, and data can only be transmitted between adjacent
devices.
User Mode
Hands over control to users when the FPGA configuration has been
completed. Only in user mode, configuration pins can be reused as
GPIOs (Gowin Programmable I/O).

2 Glossary
UG704-1.0.2E
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Glossary
Meaning
Edit Mode
FPGA can be programmed and configured in this mode.
All configuration pins cannot be reused as GPIOs. The output of all
GPIOs is high-impedance state, except background programming.
ID CODE
Identification for the the Gowin FPGA device. Each series of devices has
an individual number.
USER CODE
Used to identify the FPGA device that used. The user code can be written
to the FPGA device through Gowin programmer. Up to 32-bit can be
supported.
Security Bit
A special design for the configuration data security of Gowin FPGA
product. After you write the bitstream with security bit to the device
SRAM, no one will be able to read back the data. Gowin Software sets a
security bit for the bitstream data of all FPGA products by default.
Encryption
Arora family of FPGA products support this feature. After the encrypted
bitstream is written into FPGA, the device will match the pre-stored key
automatically, and then decrypt and wake up the device after successful
matching. The device cannot work if the matching fails.

3 Configuration Interfaces
UG704-1.0.2E
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3Configuration Interfaces
3.1 Configuration Modes
Arora Ⅴ FPGA products (138K) offer four configuration interfaces.
Each configuration interface supports one or more configuration modes
and bus widths, as show in Table 3-1.
Table 3-1 Configuration Modes
Configuration Mode
MODE[2:0][1]
Bus Width
Description
Master SERIAL
000
x1
As a Master, FPGA reads data from external
devices via the DIN interface for
configuration.
MSPI[2]
001
x1, x2, x4
As a Master, FPGA reads data from an
external Flash (or other devices) via the SPI
interface for configuration..
SSPI[2] [3]
010
x1, x4
AroraⅤ series of FPGA products are
configured by external Host via SPI interface.
Master CPU
100
x8, x16, x32
As a Master, FPGA reads data from external
devices via the DIN interface for
configuration.
JTAG
XXX/101[4]
AroraⅤ series of FPGA products are
configured by external Host via JTAG
interface.
Slave CPU
110
x8, x16, x32
AroraⅤ series of FPGA products are
configured by external Host via DBUS
interface.
Slave SERIAL
111
x1
AroraⅤ series of FPGA products are
configured by external Host via DIN interface.
Note!
[1] Please refer to the related Pinout manuals for the status of the unbound MODE
pins.
[2] The SPI interfaces of the SSPI and MSPI modes are independent of each other.
[3] Arora Ⅴ FPGA products (138K) will automatically turn to SSPI mode after the
program is loaded successfully. If SSPI mode is not used, make sure that
SSPI_HOLDN has a pull-down resistor or SSPI_CSN has a pull-up resistor.
[4] The JTAG configuration mode is independent of the MODE [2:0] values; If the
MODE [2:0] value is 101, only the JTAG mode is available.

3 Configuration Interfaces
3.2 Configuration Pins
UG704-1.0.2E
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3.2 Configuration Pins
The programming and configuration pins can be used as configuration
pins and can be also reused as GPIOs. Users can configure the pins as
required. Users can also configure them according to their configuration
functions to meet specific requirements. Table 3-2 and Table 3-3 contain a
list of all the configuration pins of Gowin FPGA products together with the
details of the pins used in each configuration mode and the shared pins in
chip packages.
Note!
When configuration I/Os are reused, note that some configuration I/Os have status
requirements during power-on and configuration. Otherwise, the device programming
may be affected. When the number of common I/Os meets the requirement, it’s not
suggested to reuse the configuration I/Os.
Table 3-2 Configuration Pin List (1 of 2)
Pin Name
Bank
JTAG
(Only)
Slave
Serial
Master
Serial
Master SPI
Slave SPI
x1
x2
x4
x1
CFGBVS
10
√
√
√
√
√
√
√
MODE[2:0]
10
M[2:0]=101
M[2:0]=111
M[2:0]=000
M[2:0]=001
M[2:0]=001
M[2:0]=001
M[2:0]=010
RECONFIG_N
10
√
√
√
√
√
√
√
READY
10
√
√
√
√
√
√
√
DONE
10
√
√
√
√
√
√
√
TCK
10
TCK
TCK
TCK
TCK
TCK
TCK
TCK
TMS
10
TMS
TMS
TMS
TMS
TMS
TMS
TMS
TDI
10
TDI
TDI
TDI
TDI
TDI
TDI
TDI
TDO
10
TDO
TDO
TDO
TDO
TDO
TDO
TDO
CCLK
10
-
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
CFGUP
11
√
√
√
√
√
√
√
PUDC_B
3/4[1]
√
√
√
√
√
√
√
EMCCLK
3/4
-
-
EMCCLK
EMCCLK
EMCCLK
EMCCLK
-
CSI_B
3/4
-
-
-
-
-
-
-
DOUT_CSO_B
3/4
-
DOUT
DOUT
-
-
-
-
RDWR_B
3/4
-
-
-
-
-
-
-
MCSN
3/4
-
-
-
MCSN
MCSN
MCSN
-
D00_MOSI
3/4
-
-
-
MOSI
MOSI/D00
MOSI/D00
-
D01_DIN
3/4
-
DIN
DIN
D01
D01
D01
-
D02
3/4
-
-
-
-
-
D02
-
D03
3/4
-
-
-
-
-
D03
-
SSPI_CSN
3/4
-
-
-
-
-
-
SSPI_CSN
D05_SSPI_SI
3/4
-
-
-
-
-
-
SSPI_SI
D06_SSPI_CLK
3/4
-
-
-
-
-
-
SSPI_CLK
D07_SSPI_WPN
3/4
-
-
-
-
-
-
SSPI_WPN
D08_SSPI_SO
3/4
-
-
-
-
-
-
SSPI_SO
SSPI_HOLD
3/4
-
-
-
-
-
-
SSPI_HOLD

3 Configuration Interfaces
3.2 Configuration Pins
UG704-1.0.2E
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D04
3/4
-
-
-
-
-
-
-
D[09-15]
3/4
-
-
-
-
-
-
-
D[16-31]
3/4
-
-
-
-
-
-
-
Note!
[1] The pin is located in BANK4 in wirebond package and BANK3 in other packages.
Please refer to the related pinout guide for the detailed information.
Table 3-3 Configuration Pin List (2 of 2)
Pin Name
Bank
Master CPU
Slave CPU
Slave SPI
x8
x16
x1
X8
X16
X32
X4
CFGBVS
10
√
√
√
√
√
√
√
MODE[2:0]
10
M[2:0]=100
M[2:0]=100
M[2:0]=100
M[2:0]=110
M[2:0]=110
M[2:0]=110
M[2:0]=010
RECONFIG_N
10
√
√
√
√
√
√
√
READY
10
√
√
√
√
√
√
√
DONE
10
√
√
√
√
√
√
√
TCK
10
TCK
TCK
TCK
TCK
TCK
TCK
TCK
TMS
10
TMS
TMS
TMS
TMS
TMS
TMS
TMS
TDI
10
TDI
TDI
TDI
TDI
TDI
TDI
TDI
TDO
10
TDO
TDO
TDO
TDO
TDO
TDO
TDO
CCLK
10
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
CFGUP
11
√
√
√
√
√
√
√
PUDC_B
3/4
√
√
√
√
√
√
√
EMCCLK
3/4
EMCCLK
EMCCLK
EMCCLK
-
-
-
-
CSI_B
3/4
CSI_B
CSI_B
CSI_B
CSI_B
CSI_B
CSI_B
-
DOUT_CSO_B
3/4
CSO_B
CSO_B
CSO_B
CSO_B
CSO_B
CSO_B
-
RDWR_B
3/4
RDWR_B
RDWR_B
RDWR_B
RDWR_B
RDWR_B
RDWR_B
-
MCSN
3/4
-
-
-
-
-
-
-
D00_MOSI
3/4
D00
D00
D00
D00
D00
D00
-
D01_DIN
3/4
D01
D01
D01
D01
D01
D01
-
D02
3/4
D02
D02
D02
D02
D02
D02
-
D03
3/4
D03
D03
D03
D03
D03
D03
-
SSPI_CSN
3/4
-
-
-
-
-
-
SSPI_CSN
D05_SSPI_SI
3/4
D05
D05
D05
D05
D05
D05
SSPI_IO0
D06_SSPI_CLK
3/4
D06
D06
D06
D06
D06
D06
SSPI_CLK
D07_SSPI_WPN
3/4
D07
D07
D07
D07
D07
D07
SSPI_IO2
D08_SSPI_SO
3/4
-
D08
D08
D08
D08
D08
SSPI_IO1
SSPI_HOLD
3/4
-
-
-
-
-
-
SSPI_IO3
D04
3/4
-
D04
D04
D04
D04
D04
-
D[09-15]
3/4
-
D[09-15]
D[09-15]
-
D[09-15]
D[09-15]
-
D[16-31]
3/4
-
-
D[16-31]
-
-
D[16-31]
-
Note!
[1] The Slave SPI x4 mode does not support read back.

3 Configuration Interfaces
3.2 Configuration Pins
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The configuration pins are as shown in Table 3-4.
Table 3-4 Pin Definitions
Pin Name
Functional Description
CFGBVS
Config bank voltage selection signal.
As a configuration pin, it is an input pin. Set the drive strength of the configuration
pins according to the Config bank VCCIO.
When VCCIO > 1.8V, CFGBVS needs to be connected to 1 (VCCIO10); when VCCIO<=
1.8V, CFGBVS needs to be connected to GND.
Note!
Config banks include GW5AT-138/ GW5AST-138 Bank10, Bank3 in FlipChip packages,
and Bank4 in WireBond packages. For details, refer to the related Pinout manuals.
MODE
Configuration mode selection pin.
As the selection pin of configuration modes, MODE is an input pin that has internal
weak pull-up. The maximum bit width is 3 bits.
After FPGA powers up or a low pulse triggers RECONFIG_N, the device enters the
corresponding configuration mode in accordance with the MODE value. The same
MODE value of the different Gowin series of FPGA products may have different
configuration MODE. As the number of pins for each package is different, some
MODE pins are not all bonded out, and the unbound MODE pins are grounded by
default. Please refer to the corresponding PINOUT manual for further details.
When MODE pins are used as GPIOs, they can be used as an input or output type.
Note!
Note that when the MODE value changes, power-on again or providing one low pulse
for triggering RECONFIG_N is required for it to take effect.
RECONFIG_N
As a configuration pin, RECONFIG_N is an input pin that has an internal weak pull-
up. Active low, it is used to reconfigure the FPGA during programming configuration.
FPGA can't be configured if RECONFIG_N is set to low. Keep high-level during
power-on and configuration.
As a configuration pin, a low level signal with pulse width no less than 25ns is
required for GowinCONFIG to reload bitstream data according to the MODE setting
value. You can control the pin by writing logic to trigger the device to reconfigure as
required. In the case of user logic control, ensure that the pin is kept high during
power-on and configuration.
Only output type can be used as GPIO. To ensure a smooth configuration, set the
initial value of RECONFIG_N to high and cannot be external pulled down during the
power-on process
READY
Inout pins. Internal weak pull-up, open-drain output. Active-high. FPGA can be
configured only when the READY signal is pulled up.
It indicates that the FPGA can be configured or not. If the FPGA meets the
configuration condition, the READY signal is high. If the power-on or reset process
is incomplete, READY signal is low.
Users can delay the active configuration by pulling down the READY signal
externally.
As a GPIO, it can be reused as an input or output type. If READY is used as an
input GPIO, ensure that it’s not pulled down during the power-on and configuration
process. Otherwise, The configuration may not work properly.
DONE
Inout pins. Internal weak pull-up, open-drain output.
It indicates FPGA is configured successfully or not. DONE is pulled up after
successfully configuring.
As an output configuration pin, it indicates whether the FPGA configuration is
successful:

3 Configuration Interfaces
3.2 Configuration Pins
UG704-1.0.2E
9(70)
Pin Name
Functional Description
If DONE is high, the device has been awakened and enters into the working
state.
If DONE is low, the configuration process is incomplete or fails.
As an input configuration pin, the user can delay the wake up process by pulling
down the DONE signal externally.
When RECONFIG_N or READY signals are low, DONE signal also keeps low.
When configuring SRAM using JTAG circuit, it does not need to take DONE signal
into account.
As a GPIO, it can be used as an input or output type. If DONE is used as an input
GPIO, ensures that it is not pulled down externally during power-on and
configuration process. Otherwise, the FPGA will fail to enter the user mode after
configuration.
TCK
As a configuration pin, it is an input pin.
It is a serial clock input pin in the JTAG configuration mode. As a GPIO, it can be
used as an input or output type.
Note!
As a GPIO, ensures that the pin status is stable during the power-on and loading
process to prevent the JTAG command from being triggered by mistake.
TMS
As a configuration pin, it is an input pin with internal weak pull-up.
It is a serial input pin in JTAG configuration mode. As a GPIO, it can be used as an
input or output type.
TDI
As a configuration pin, it is an input pin with internal weak pull-up.
It is a serial data input pin in JTAG configuration mode. As a GPIO, it can be used
as an input or output type.
TDO
As a configuration pin, it is an output pin.
It is a serial data output pin in JTAG configuration mode. As a GPIO, it can be used
as an input or output type.
CCLK
As a configuration clock pin, CCLK runs the synchronous FPGA configuration
sequence in all modes except JTAG and SSPI mode.
For slave modes: CCLK is an input and requires connection to an external clock
source.
For master modes: The FPGA sources the configuration clock and drives CCLK as
an output.
Note!
CCLK is the key clock signal, so good signal integrity must be ensured.
PUDC_B
As a configuration pin, it is an input pin.
When PUDC_B is low, the internal pull-up resistors are enabled on all GPIOs during
device configuration.
When PUDC_B is high, the internal pull-up resistors are disabled on all GPIOs
during device configuration.
PUDC_B must be tied to VCCO3/4 or GND directly or via a 1 kΩ (or stronger)
resistor.
EMCCLK
As a configuration pin, it is an input pin. Used to configure the optional external
clock input in a master mode (versus the internal configuration oscillator).
For master modes: FPGA can optionally switch to use EMCCLK as the clock
source.
For JTAG and slave modes: EMCCLK is ignored and can be left unconnected.
CSI_B
As a configuration pin, it is an input pin. It is a chip selection input signal in the CPU
mode, active low.

3 Configuration Interfaces
3.2 Configuration Pins
UG704-1.0.2E
10(70)
Pin Name
Functional Description
For CPU master mode, tie to GND directly or via a 1 kΩ (or less) resistor.
For CPU slave mode: An external configuration controller can control CSI_B for
selecting the active FPGA on the bus, or in a daisy-chain configuration, connect to
the CSO_B pin of the upstream FPGA.
CSO_B
As a configuration pin, it is an output pin. It is a chip selection input signal in the
CPU mode. It connects to the CSI_B pin of the downstream FPGA in a daisy-chain
configuration.
DOUT
As a configuration pin, it is an output pin. DOUT is the data output for a serial
configuration daisy-chain.
For Serial and SPI (x1 only) modes: Connect to the DIN of the downstream FPGA in
a serial configuration daisy-chain, as the data input of the following device.
RDWR_B
As a configuration pin, it is an input pin.
As a Read/Write enable selection pin in CPU mode: it refers to Read when
RDWR_B is high and Write when RDWR_B is low. As a GPIO, it can be used as an
input or output type.
MCSN
As a configuration pin, it is an output pin.
It is a chip selection signal in MSPI configuration mode, active low. As a GPIO, it
can be used as an input or output type.
D00/MOSI
As a configuration pin, it is an output pin. Connects to SI pin of the external Flash.
The SPIx2 x4 line is bidirectional.
Serial data output pin in MSPI configuration mode.
As a GPIO, it can be used as an input or output type.
D01/MISO
As a configuration pin, it is an input pin. Connects to SO pin of the external Flash.
The SPIx2 x4 line is bidirectional.
Serial data input pin in MSPI configuration mode.
As a GPIO, it can be used as an input or output type.
D02/WPn
As a configuration pin, it is an output pin. The SPIx4 line is bidirectional.
MSPI write protection pin: When the output is high, the MSPI operation is valid; When
the output level is low, the MSPI operation is invalid. The VCCIO of the corresponding
bank can be pulled up through the 4.7k resistor.
As a GPIO, it can be used as an input or output type.
D03/HOLDn
As a configuration pin, it is an output pin, internal weak pull-up. The SPIx4 line is
bidirectional.
MSPI clock lock pin, active low. The VCCIO of the corresponding bank can be pulled
up through the 4.7k resistor.
As a GPIO, it can be used as an input or output type.
DIN
As a configuration pin, it is an input pin. It is a serial data input pin.
For Serial and MSPI modes: DIN receives serial data from the data source and
collects data at the CCLK rising edge in the default configuration.
For CPU modes, DIN is a multi-function pin that functions as the D01 data pin. As a
GPIO, it can be used as an input or output type.
D0~D31
Inout pins.
CPU mode: D0~D31 are data in/out pins. The FPGA will automatically detect the
data width of x8, x16, or x32.
As a GPIO, it can be used as an input or output type.
SSPI_CSN
As a configuration pin, it is an input pin. The VCCIO of the corresponding bank can be
pulled up through the 4.7k resistor. It is a chip selection signal in the SSPI
configuration mode, active low. As a GPIO, it can be used as an input or output
type.

3 Configuration Interfaces
3.2 Configuration Pins
UG704-1.0.2E
11(70)
Pin Name
Functional Description
SSPI_CLK
As a configuration pin, it is an input pin.
It is a clock input pin of SSPI configuration mode. As a GPIO, it can be used as an
input or output type.
SSPI_SI
As a configuration pin, it is an input pin. It is a serial data input pin in the SSPI
configuration mode. As a GPIO, it can be used as an input or output type.
SSPI_SO
As a configuration pin, it is an output pin. It is a serial data output pin in the SSPI
configuration mode. As a GPIO, it can be used as an input or output type.
SSPI_HOLDn
As a configuration pin, it is an input pin. The VCCIO of the corresponding bank can be
pulled up through the 4.7k resistor.
A clock holding pin in SSPI mode, active-high. As a GPIO, it can be used as an
input or output type.
SSPI_WPN
As a configuration pin, it is an input pin. The VCCIO of the corresponding bank can be
pulled up through the 4.7k resistor.
A write protection pin in SSPI mode: SSPI is valid when the input is high, SSPI is
invalid when the input is low.
As a GPIO, it can be used as an input or output type.
Configuration Pin Multiplexing
To maximize the utilization of I/O, Gowin FPGA product support for
setting the configuration pins as GPIO pins. Before any configuration
operation is performed on all series of Gowin FPGA products after power
up, all related configuration pins are used as configuration pins by default.
After successful configuration, the device enters into user mode and
reassigns the pin functions according to the multiplex options selected by
the user.
Note!
When setting the pin reuse options, ensure the external initial connection state of the pins
does not affect the device configuration.
The reuse options for the configuration pins are detailed in Table 3-5.
Table 3-5 Pin Reuse Options
Name
Options
Description
JTAG PORT
Default Status
TMS, TCK, TDI, and TDO are dedicated
configuration pins.
Set as GPIOs
TMS, TCK, TDI, and TDO are used as GPIOs
after configuration.
CPU PORT
Default Status
CSI_B, CSO_B, RDWR_B, D[0-31], and
CCLK are dedicated configuration pins.
Set as GPIOs
CSI_B, CSO_B, RDWR_B, D[0-31], and
CCLK are used as GPIOs after configuration.
SSPI PORT
Default Status
SSPI_CSN, SSPI_CLK, SSPI_SI, SSPI_SO,
SSPI_HOLD, and SSPI_WPN are dedicated
configuration pins.
Set as GPIOs
SSPI_CSN, SSPI_CLK, SSPI_SI, SSPI_SO,
SSPI_HOLD, and SSPI_WPN are used as
GPIOs after configuration.
MSPI PORT
Default Status
MCSN, MISO, MOSI, D02, D03, and CCLK
are dedicated configuration pins.

3 Configuration Interfaces
3.2 Configuration Pins
UG704-1.0.2E
12(70)
Name
Options
Description
Set as GPIOs
MCSN, MISO, MOSI, D02, D03, and CCLK
are used as GPIOs after configuration.
SERIAL
Default Status
DIN, DOUT, and CCLK are dedicated
configuration pins.
Set as GPIOs
DIN, DOUT, and CCLK are used as GPIOs
after configuration.
RECONFIG_N
Default Status
Dedicated configuration pins.
Set as GPIOs
Used as GPIO output after configuration.
READY
Default Status
Dedicated configuration pins.
Set as GPIOs
Used as GPIOs after configuration.
DONE
Default Status
Dedicated configuration pins.
Set as GPIOs
Used as GPIOs after configuration.
Note!
The JTAG_SEL_N signal can be used to configure JTAG pins as GPIOs. As a GPIO,
ensures that the TCK/TMS is stable during the power-on and programming process to
prevent the JTAG command from being triggered by mistake.
Pin Reuse Configuration
Users can configure pin reuse via Gowin Software.
1. Open the corresponding project in Gowin Software;
2. Select “Project > Configuration > Dual-Purpose Pin” in the menu bar,
as shown in Figure 3-1;
3. Check the corresponding options to set the pin reuse.