GOWIN JESD204B User manual

Gowin JESD204B IP
User Guide
IPUG1019-1.0E, 05/25/2023

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Revision History
Date
Version
Description
05/25/2023
1.0E
Initial version published.

Contents
IPUG1019-1.0E
i
Contents
Contents ...............................................................................................................i
List of Figures....................................................................................................iii
List of Tables......................................................................................................iv
1 About This Guide.............................................................................................1
1.1 Purpose .............................................................................................................................. 1
1.2 Related Documents ............................................................................................................1
1.3 Terminology and Abbreviations........................................................................................... 1
1.4 Support and Feedback .......................................................................................................2
2 Function Introduction......................................................................................3
2.1 Overview.............................................................................................................................3
2.2 Features.............................................................................................................................. 3
2.3 Resource Utilization............................................................................................................4
3 Functional Description....................................................................................5
3.1 System Block Diagram .......................................................................................................5
3.2 Receiver.............................................................................................................................. 6
3.3 Port List............................................................................................................................... 7
3.3.1 TX Core Interface ............................................................................................................7
3.3.2 RX Core Interface .......................................................................................................... 10
3.4 Interface Timing ................................................................................................................13
3.4.1 TX Core Interface ..........................................................................................................13
3.4.2 RX Core Interface .......................................................................................................... 14
3.5 Register Description .........................................................................................................14
4 Design Considerations..................................................................................25
4.1 Line Rate ..........................................................................................................................25
4.2 Clock .................................................................................................................................25
4.2.1 Core Clock (core clk) .....................................................................................................25
4.2.2 Reference Clock ............................................................................................................25
4.2.3 Configuration Clock (cfg clk).......................................................................................... 25
4.2.4 SerDes PCS Clock ........................................................................................................26
4.2.5 Generic Clock Scheme ..................................................................................................26
4.3 Reset ................................................................................................................................26

Contents
IPUG1019-1.0E
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4.3.1 Bus Reset Port...............................................................................................................26
4.3.2 Reset Core Logic via Pins ............................................................................................. 26
4.3.3 Reset Core Logic via Registers .....................................................................................27
4.3.4 SerDes Related Reset ...................................................................................................27
4.3.5 Reset Flow.....................................................................................................................27
4.4 Subclass ...........................................................................................................................27
4.5 SYSREF ...........................................................................................................................28
4.5.1 SYSREF Timing............................................................................................................. 28
4.5.2 SYSREF Always ............................................................................................................28
4.5.3 SYSREF on Initial Link Established...............................................................................28
4.5.4 SYSREF on Link Resynchronization .............................................................................29
4.5.5 SYSREF Delay ..............................................................................................................29
4.6 Minimum Deterministic Latency Support ..........................................................................30
4.7 Link Test Mode.................................................................................................................. 31
4.7.1 Continuous K28.5 Characters .......................................................................................31
4.7.2 Continuous ILA Sequence .............................................................................................31
4.7.3 Continuous D21.5 Characters .......................................................................................31
4.7.4 RPAT..............................................................................................................................31
4.7.5 JSPAT ............................................................................................................................31
4.8 Real-time Configuration ....................................................................................................31
4.9 Data Interface ...................................................................................................................32
5 Interface Configuration .................................................................................33
6 Reference Design ..........................................................................................37
6.1 Applications.......................................................................................................................37
6.2 Reference Design ............................................................................................................. 38
6.2.1 Hardware Platforms .......................................................................................................38
6.2.2 Implementation Diagram ............................................................................................... 39
6.2.3 Bus Protocol and Address .............................................................................................40
6.3 On-Board Testing..............................................................................................................41
6.3.1 Operation Description ....................................................................................................41
6.3.2 Operation Steps.............................................................................................................41
7 File Delivery ...................................................................................................44
7.1 Documentation..................................................................................................................44
7.2 Design Source Code (Encryption) ....................................................................................44
7.3 Reference Design ............................................................................................................. 44

List of Figures
IPUG1019-1.0E
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List of Figures
Figure 3-1 Transmitter Block Diagram ...............................................................................................5
Figure 3-2 Receiver Block Diagram ................................................................................................... 6
Figure 3-3 Gowin JESD204B IP TX Port Diagram.............................................................................7
Figure 3-4 Gowin JESD204B IP RX Core Port Diagram ...................................................................10
Figure 3-5 Write Timing Diagram of Configuration Interface .............................................................13
Figure 3-6 Read Timing Diagram of Configuration Interface ............................................................. 13
Figure 3-7 F=2 K=32, TX Data Interface Timing................................................................................14
Figure 3-8 F=2 K=32, RX Data Interface Timing ...............................................................................14
Figure 4-1 Generic Clock Scheme..................................................................................................... 26
Figure 4-2 Minimum Deterministic Latency Block Diagram ............................................................... 30
Figure 4-3 Data Stream Interface Data Format ................................................................................. 32
Figure 5-1 Open SerDes IP ...............................................................................................................33
Figure 5-2 Gowin JESD204B IP Configuration Interface 1................................................................34
Figure 5-3 Gowin JESD204B IP Configuration Interface 2................................................................35
Figure 5-4 jesd204b: JESD204B_Top ...............................................................................................36
Figure 5-5 Generated Files ................................................................................................................ 36
Figure 6-1 Connection Diagram of FPGA and ADC........................................................................... 37
Figure 6-2 Connection Diagram of FPGA and ADC........................................................................... 37
Figure 6-3 Platforms Diagram............................................................................................................38
Figure 6-4 Block Diagram of Reference Design ................................................................................ 39
Figure 6-5 Capture DDS Data............................................................................................................43

List of Tables
IPUG1019-1.0E
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List of Tables
Table 1-1 Terminology and Abbreviations ..........................................................................................1
Table 2-1 Gowin JESD204B IP Overview ..........................................................................................3
Table 2-2 Resource Utilization of Gowin JESD204B IP.....................................................................4
Table 3-1 I/O List of TX Core .............................................................................................................8
Table 3-2 I/O List of RX Core ............................................................................................................. 11
Table 3-3 Gowin JESD204B IP Registers..........................................................................................14
Table 3-4 Version [Offset:0x004]........................................................................................................ 15
Table 3-5 Reset [Offset:0x008] ..........................................................................................................16
Table 3-6 ILA Support [Offset:0x00C] ................................................................................................16
Table 3-7 Scrambling [Offset:0x010].................................................................................................. 16
Table 3-8 SYSREF Handling [Offset:0x014] ...................................................................................... 16
Table 3-9 Test Modes [Offset:0x018].................................................................................................. 17
Table 3-10 F_and_K [Offset:0x01C]...................................................................................................17
Table 3-11 Subclass Mode [Offset:0x020].......................................................................................... 17
Table 3-12 Sync Status [Offset:0x024]............................................................................................... 18
Table 3-13 Link Error Status (Lines 0 to 7) [Offset:0x028]................................................................. 18
Table 3-14 Alarm Status [Offset:0x02C]............................................................................................. 18
Table 3-15 RXBUF_DELAY (RX ONLY) [Offset:0x030] ..................................................................... 19
Table 3-16 ERR_REPORT (RX ONLY) [Offset:0x034] ......................................................................19
Table 3-17 LINK_DEBUG (RX ONLY) [Offset:0x034] ........................................................................19
Table 3-18 ERR_CLEAR [Offset:0x040] ............................................................................................20
Table 3-19 Lane ID [Offset: lane0-0x080, lane1-0x084 ……lane3-0x08C] .......................................20
Table 3-20 ILA Config Data 0 [Offset: lane0-0x0C0, lane1-0x100 …… lane3-0x180]....................... 20
Table 3-21 ILA Config Data 1 [Offset: lane0-0x0C4, lane1-0x104 …… lane3-0x184]....................... 20
Table 3-22 ILA Config Data 2 [Offset: lane0-0x0C8, lane1-0x108 …… lane3-0x188]....................... 20
Table 3-23 ILA Config Data 3 [Offset: lane0-0x0CC, lane1-0x10C …… lane3-0x18C]..................... 21
Table 3-24 ILA Config Data 4 [Offset: lane0-0x0D0, lane1-0x110 …… lane3-0x190] ....................... 21
Table 3-25 ILA Config Data 5 [Offset: lane0-0x0D4, lane1-0x114 …… lane3-0x194] ....................... 21
Table 3-26 ILA Config Data 6 [Offset: lane0-0x0D8, lane1-0x118 …… lane3-0x198] ....................... 22
Table 3-27 ILA Config Data 7 [Offset: lane0-0x0DC, lane1-0x11C …… lane3-0x19C] .....................22
Table 3-28 Test Mode Error Count [Offset: lane0-0x0E0, lane1-0x120 …… lane3-0x1A0] ..............23
Table 3-29 Link Error Count [Offset: lane0-0x0E4, lane1-0x124 …… lane3-0x1A4].........................23

List of Tables
IPUG1019-1.0E
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Table 3-30 Test Mode ILA Count [Offset: lane0-0x0E8, lane1-0x128 …… lane3-0x1A8] .................23
Table 3-31 Test Mode Multiframe Count [Offset: lane0-0x0EC, lane1-0x12C . lane3-0x1AC] ..........24
Table 3-32 Buffer Adjust [Offset: lane0-0x0F0, lane1-0x130 …… lane3-0x1B0] ..............................24
Table 6-1 Register Definition.............................................................................................................. 40
Table 7-1 Documents List ..................................................................................................................44
Table 7-2 Design Source Code List of Gowin JESD204B IP ............................................................. 44
Table 7-3 Gowin JESD204B IP RefDesign Folder List ......................................................................44

1 About This Guide
1.1 Purpose
IPUG1019-1.0E
1(45)
1About This Guide
1.1 Purpose
The purpose of Gowin JESD204B IP User Guide is to help you learn
the features and usage of Gowin JESD204B IP by providing the
descriptions of functions, GUI, and reference design, etc.
1.2 Related Documents
The latest user guides are available on the GOWINSEMI Website.
You can find related documents at www.gowinsemi.com.cn/en/
SUG100, Gowin Software User Guide
DS981, GW5AT series of FPGA Products Data Sheet
DS1104, GW5AST series of FPGA Products Data Sheet
1.3 Terminology and Abbreviations
Table 1-1 shows the abbreviations and terminology used in this
manual.
Table 1-1 Terminology and Abbreviations
Terminology and Abbreviations
Meaning
APB
Advanced Peripheral Bus
CGS
Code Group Sync
DDS
Direct Digital Frequency Synthesizer
FPGA
Field Programmable Gate Array
ILAS
Initial channel alignment sequence
IP
Intellectual Property
LMFC
Local Multi-Frame Clock
SerDes
Serializer/Deserializer

1 About This Guide
1.4 Support and Feedback
IPUG1019-1.0E
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1.4 Support and Feedback
Gowin Semiconductor provides customers with comprehensive
technical support. If you have any questions, comments, or suggestions,
please feel free to contact us directly using the information provided below.
Website: www.gowinsemi.com
E-mail: [email protected]