GOWIN JESD204B User manual

Gowin JESD204B IP
User Guide
IPUG1019-1.0E, 05/25/2023

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contact GOWINSEMI for the current documentation and errata.

Revision History
Date
Version
Description
05/25/2023
1.0E
Initial version published.

Contents
IPUG1019-1.0E
i
Contents
Contents ...............................................................................................................i
List of Figures....................................................................................................iii
List of Tables......................................................................................................iv
1 About This Guide.............................................................................................1
1.1 Purpose .............................................................................................................................. 1
1.2 Related Documents ............................................................................................................1
1.3 Terminology and Abbreviations........................................................................................... 1
1.4 Support and Feedback .......................................................................................................2
2 Function Introduction......................................................................................3
2.1 Overview.............................................................................................................................3
2.2 Features.............................................................................................................................. 3
2.3 Resource Utilization............................................................................................................4
3 Functional Description....................................................................................5
3.1 System Block Diagram .......................................................................................................5
3.2 Receiver.............................................................................................................................. 6
3.3 Port List............................................................................................................................... 7
3.3.1 TX Core Interface ............................................................................................................7
3.3.2 RX Core Interface .......................................................................................................... 10
3.4 Interface Timing ................................................................................................................13
3.4.1 TX Core Interface ..........................................................................................................13
3.4.2 RX Core Interface .......................................................................................................... 14
3.5 Register Description .........................................................................................................14
4 Design Considerations..................................................................................25
4.1 Line Rate ..........................................................................................................................25
4.2 Clock .................................................................................................................................25
4.2.1 Core Clock (core clk) .....................................................................................................25
4.2.2 Reference Clock ............................................................................................................25
4.2.3 Configuration Clock (cfg clk).......................................................................................... 25
4.2.4 SerDes PCS Clock ........................................................................................................26
4.2.5 Generic Clock Scheme ..................................................................................................26
4.3 Reset ................................................................................................................................26

Contents
IPUG1019-1.0E
ii
4.3.1 Bus Reset Port...............................................................................................................26
4.3.2 Reset Core Logic via Pins ............................................................................................. 26
4.3.3 Reset Core Logic via Registers .....................................................................................27
4.3.4 SerDes Related Reset ...................................................................................................27
4.3.5 Reset Flow.....................................................................................................................27
4.4 Subclass ...........................................................................................................................27
4.5 SYSREF ...........................................................................................................................28
4.5.1 SYSREF Timing............................................................................................................. 28
4.5.2 SYSREF Always ............................................................................................................28
4.5.3 SYSREF on Initial Link Established...............................................................................28
4.5.4 SYSREF on Link Resynchronization .............................................................................29
4.5.5 SYSREF Delay ..............................................................................................................29
4.6 Minimum Deterministic Latency Support ..........................................................................30
4.7 Link Test Mode.................................................................................................................. 31
4.7.1 Continuous K28.5 Characters .......................................................................................31
4.7.2 Continuous ILA Sequence .............................................................................................31
4.7.3 Continuous D21.5 Characters .......................................................................................31
4.7.4 RPAT..............................................................................................................................31
4.7.5 JSPAT ............................................................................................................................31
4.8 Real-time Configuration ....................................................................................................31
4.9 Data Interface ...................................................................................................................32
5 Interface Configuration .................................................................................33
6 Reference Design ..........................................................................................37
6.1 Applications.......................................................................................................................37
6.2 Reference Design ............................................................................................................. 38
6.2.1 Hardware Platforms .......................................................................................................38
6.2.2 Implementation Diagram ............................................................................................... 39
6.2.3 Bus Protocol and Address .............................................................................................40
6.3 On-Board Testing..............................................................................................................41
6.3.1 Operation Description ....................................................................................................41
6.3.2 Operation Steps.............................................................................................................41
7 File Delivery ...................................................................................................44
7.1 Documentation..................................................................................................................44
7.2 Design Source Code (Encryption) ....................................................................................44
7.3 Reference Design ............................................................................................................. 44

List of Figures
IPUG1019-1.0E
iii
List of Figures
Figure 3-1 Transmitter Block Diagram ...............................................................................................5
Figure 3-2 Receiver Block Diagram ................................................................................................... 6
Figure 3-3 Gowin JESD204B IP TX Port Diagram.............................................................................7
Figure 3-4 Gowin JESD204B IP RX Core Port Diagram ...................................................................10
Figure 3-5 Write Timing Diagram of Configuration Interface .............................................................13
Figure 3-6 Read Timing Diagram of Configuration Interface ............................................................. 13
Figure 3-7 F=2 K=32, TX Data Interface Timing................................................................................14
Figure 3-8 F=2 K=32, RX Data Interface Timing ...............................................................................14
Figure 4-1 Generic Clock Scheme..................................................................................................... 26
Figure 4-2 Minimum Deterministic Latency Block Diagram ............................................................... 30
Figure 4-3 Data Stream Interface Data Format ................................................................................. 32
Figure 5-1 Open SerDes IP ...............................................................................................................33
Figure 5-2 Gowin JESD204B IP Configuration Interface 1................................................................34
Figure 5-3 Gowin JESD204B IP Configuration Interface 2................................................................35
Figure 5-4 jesd204b: JESD204B_Top ...............................................................................................36
Figure 5-5 Generated Files ................................................................................................................ 36
Figure 6-1 Connection Diagram of FPGA and ADC........................................................................... 37
Figure 6-2 Connection Diagram of FPGA and ADC........................................................................... 37
Figure 6-3 Platforms Diagram............................................................................................................38
Figure 6-4 Block Diagram of Reference Design ................................................................................ 39
Figure 6-5 Capture DDS Data............................................................................................................43

List of Tables
IPUG1019-1.0E
iv
List of Tables
Table 1-1 Terminology and Abbreviations ..........................................................................................1
Table 2-1 Gowin JESD204B IP Overview ..........................................................................................3
Table 2-2 Resource Utilization of Gowin JESD204B IP.....................................................................4
Table 3-1 I/O List of TX Core .............................................................................................................8
Table 3-2 I/O List of RX Core ............................................................................................................. 11
Table 3-3 Gowin JESD204B IP Registers..........................................................................................14
Table 3-4 Version [Offset:0x004]........................................................................................................ 15
Table 3-5 Reset [Offset:0x008] ..........................................................................................................16
Table 3-6 ILA Support [Offset:0x00C] ................................................................................................16
Table 3-7 Scrambling [Offset:0x010].................................................................................................. 16
Table 3-8 SYSREF Handling [Offset:0x014] ...................................................................................... 16
Table 3-9 Test Modes [Offset:0x018].................................................................................................. 17
Table 3-10 F_and_K [Offset:0x01C]...................................................................................................17
Table 3-11 Subclass Mode [Offset:0x020].......................................................................................... 17
Table 3-12 Sync Status [Offset:0x024]............................................................................................... 18
Table 3-13 Link Error Status (Lines 0 to 7) [Offset:0x028]................................................................. 18
Table 3-14 Alarm Status [Offset:0x02C]............................................................................................. 18
Table 3-15 RXBUF_DELAY (RX ONLY) [Offset:0x030] ..................................................................... 19
Table 3-16 ERR_REPORT (RX ONLY) [Offset:0x034] ......................................................................19
Table 3-17 LINK_DEBUG (RX ONLY) [Offset:0x034] ........................................................................19
Table 3-18 ERR_CLEAR [Offset:0x040] ............................................................................................20
Table 3-19 Lane ID [Offset: lane0-0x080, lane1-0x084 ……lane3-0x08C] .......................................20
Table 3-20 ILA Config Data 0 [Offset: lane0-0x0C0, lane1-0x100 …… lane3-0x180]....................... 20
Table 3-21 ILA Config Data 1 [Offset: lane0-0x0C4, lane1-0x104 …… lane3-0x184]....................... 20
Table 3-22 ILA Config Data 2 [Offset: lane0-0x0C8, lane1-0x108 …… lane3-0x188]....................... 20
Table 3-23 ILA Config Data 3 [Offset: lane0-0x0CC, lane1-0x10C …… lane3-0x18C]..................... 21
Table 3-24 ILA Config Data 4 [Offset: lane0-0x0D0, lane1-0x110 …… lane3-0x190] ....................... 21
Table 3-25 ILA Config Data 5 [Offset: lane0-0x0D4, lane1-0x114 …… lane3-0x194] ....................... 21
Table 3-26 ILA Config Data 6 [Offset: lane0-0x0D8, lane1-0x118 …… lane3-0x198] ....................... 22
Table 3-27 ILA Config Data 7 [Offset: lane0-0x0DC, lane1-0x11C …… lane3-0x19C] .....................22
Table 3-28 Test Mode Error Count [Offset: lane0-0x0E0, lane1-0x120 …… lane3-0x1A0] ..............23
Table 3-29 Link Error Count [Offset: lane0-0x0E4, lane1-0x124 …… lane3-0x1A4].........................23

List of Tables
IPUG1019-1.0E
v
Table 3-30 Test Mode ILA Count [Offset: lane0-0x0E8, lane1-0x128 …… lane3-0x1A8] .................23
Table 3-31 Test Mode Multiframe Count [Offset: lane0-0x0EC, lane1-0x12C . lane3-0x1AC] ..........24
Table 3-32 Buffer Adjust [Offset: lane0-0x0F0, lane1-0x130 …… lane3-0x1B0] ..............................24
Table 6-1 Register Definition.............................................................................................................. 40
Table 7-1 Documents List ..................................................................................................................44
Table 7-2 Design Source Code List of Gowin JESD204B IP ............................................................. 44
Table 7-3 Gowin JESD204B IP RefDesign Folder List ......................................................................44

1 About This Guide
1.1 Purpose
IPUG1019-1.0E
1(45)
1About This Guide
1.1 Purpose
The purpose of Gowin JESD204B IP User Guide is to help you learn
the features and usage of Gowin JESD204B IP by providing the
descriptions of functions, GUI, and reference design, etc.
1.2 Related Documents
The latest user guides are available on the GOWINSEMI Website.
You can find related documents at www.gowinsemi.com.cn/en/
SUG100, Gowin Software User Guide
DS981, GW5AT series of FPGA Products Data Sheet
DS1104, GW5AST series of FPGA Products Data Sheet
1.3 Terminology and Abbreviations
Table 1-1 shows the abbreviations and terminology used in this
manual.
Table 1-1 Terminology and Abbreviations
Terminology and Abbreviations
Meaning
APB
Advanced Peripheral Bus
CGS
Code Group Sync
DDS
Direct Digital Frequency Synthesizer
FPGA
Field Programmable Gate Array
ILAS
Initial channel alignment sequence
IP
Intellectual Property
LMFC
Local Multi-Frame Clock
SerDes
Serializer/Deserializer

1 About This Guide
1.4 Support and Feedback
IPUG1019-1.0E
2(45)
1.4 Support and Feedback
Gowin Semiconductor provides customers with comprehensive
technical support. If you have any questions, comments, or suggestions,
please feel free to contact us directly using the information provided below.
Website: www.gowinsemi.com
E-mail: [email protected]

2 Function Introduction
2.1 Overview
IPUG1019-1.0E
3(45)
2Function Introduction
2.1 Overview
JESD204B is a high-speed serial interface used to connect Analog-to-
Digital Converters (ADCs) and Digital-to-Analog Converters (DACs) to
logic devices. The IP implements the data link layer functions in the
JESD204B protocol, including Code Group Sync (CGS), Initial Lane
Alignment Sequence (ILAS), user data output, etc. This IP currently only
supports subclass 1.
Table 2-1 Gowin JESD204B IP Overview
Gowin JESD204B IP
Logic Resource
Please refer to Table 2-2
Delivered Doc.
Design Files
Verilog (encrypted)
Reference Design
Verilog
TestBench
Verilog
Test and Design Flow
Synthesis Software
GowinSynthesis
Application Software
Gowin Software (V1.9.9.Beta-1 and above)
Note!
For the devices supported, you can click here to get the information.
2.2 Features
Supports up to four lanes per core
Supports initial lane alignment
Supports scrambling and descrambling
Supports 1-256 octets per frame
Supports 1-32 frames per multiframe
Supports subclass 1
The configuration interface supports real-time parameter modification
The IP core can be configured to TX, RX, and TX & RX modes

2 Function Introduction
2.3 Resource Utilization
IPUG1019-1.0E
4(45)
2.3 Resource Utilization
JESD204B IP can be implemented by Verilog. Its performance and
resource utilization may vary when the design is employed in different
devices, or at different densities, speeds, or grades. Take GW5AT series
as an instance, and the resource utilization is as shown in Table 2-2.
Table 2-2 Resource Utilization of Gowin JESD204B IP
Number
of lanes
Type
Resource Utilization
Register
LUT
ALU
BSRAM
SSRAM
1
TX & RX
2358
2633
636
1
19
2
TX & RX
4066
4634
1032
2
38
4
TX & RX
7482
8479
1826
4
76
1
TX
822
1141
274
0
19
2
TX
1224
1800
432
0
38
4
TX
2028
3150
750
0
76
1
RX
1537
1506
362
1
0
2
RX
2843
2854
600
2
0
4
RX
5455
5512
1076
4
0

3 Functional Description
3.1 System Block Diagram
IPUG1019-1.0E
5(45)
3Functional Description
3.1 System Block Diagram
Transmitter
The transmitter of JESD204B is as shown in Figure 3-1 .
Figure 3-1 Transmitter Block Diagram
tx_ilas
data_src data_swap
tx_lane0
RPAT GEN
lmfc_ctrl
tx_lane1
Cfg register
SYNC/SYSREF
Cfg Inf JSPAT GEN
Data Stream TO SERDES
INTERFACE
The number of lanes supported by JESD204B TX Core can be
configured, and the module tx_lane will be automatically instantiated
internally for each additional lane.
The tx_lane module includes:
tx_ilas module: Used to generate the initial lane alignment sequence
data_scr module: Used for data scrambling
data_swap module: Used to replace octets at the end of frame or
multiframe according to certain rules
Other modules:
RPAT module: RPAT generator
JSPAT Module: JSPAT generator

3 Functional Description
3.2 Receiver
IPUG1019-1.0E
6(45)
tx_lmfc_ctrl module: Used to generate a local multiframe clock for
subclass 1
Cfg_register module: Used to configure and monitor internal registers
3.2 Receiver
The receiver of JESD204B is as shown in Figure 3-2 .
Figure 3-2 Receiver Block Diagram
data_desrcdata_swap
rx_lane0
lmfc_ctrl
rx_lane1
Cfg register
SYSREF
Cfg Inf
FROM SERDES
INTERFACE
rxflag_gen
rx_ilas_inf
Data Stream
SYNC
Lane0
Lane1
Lane
align
rx_err_monitor
rx_test_mode
The number of lanes supported by JESD204B RX Core can be
configured, and the module rx_lane will be automatically instantiated
internally for each additional lane.
The rx_lane module includes:
rxflag_en module: Used to generate the flags for start of frame, end of
frame, end of multiframe, and special characters
rx_ilas_inf module: Used to capture ILAS
data_swap module: Used to replace octets at the end of frame or
multiframe according to certain rules
data_descr module: Used for data descrambling
rx_test_mode module: Error counters for SerDes RX data in test mode
rx_err_monitor module: Error counters for SerDes data, ILAS, and
data fields in normal mode
Other modules:
Lane_align module: Data buffer for all lanes; when all lanes have
received ILAS, the buffer is released at the same time.
tx_lmfc_ctrl module: Used to generate a local multiframe clock for
subclass 1
Cfg_register module: Used to configure and monitor internal registers

3 Functional Description
3.3 Port List
IPUG1019-1.0E
7(45)
3.3 Port List
Gowin JESD204B IP TX core and RX core interfaces are independent
of each other and described separately below.
3.3.1 TX Core Interface
The IO ports of the Gowin JESD204B IP TX core are shown in Figure
3-3.
Figure 3-3 Gowin JESD204B IP TX Port Diagram

3 Functional Description
3.3 Port List
IPUG1019-1.0E
8(45)
Table 3-1 I/O List of TX Core
Signal Name
I/O
Description
tx_rst_i
IN
TX core reset
1: Reset
0: Operating
tx_core_clk_i
IN
TX core clock, frequency = line rate/40.
tx_cfg_clk_i
IN
Bus configuration clock, free-running clock.
tx_cfg_rstn_i
IN
Bus configuration reset
tx_cfg_addr_i
IN
Bus configuration address
tx_cfg_sel_i
IN
Bus configuration selection
tx_cfg_ena_i
IN
Bus configuration enable
tx_cfg_wr_i
IN
Bus I/O signal
1：Write
0：Read
tx_cfg_rdata_o[31:0]
OUT
Read data
tx_cfg_wdata_i[31:0]
IN
Write data
tx_cfg_rdy_o
OUT
Ready signal
tx_cfg_strb_i[3:0]
IN
Write strobe signal, fixed to 4’hf
tx_sysref_i
IN
SYSREF input, this signal is required when
configured as subclass 1.
tx_sync_n_i
IN
JESD204B defines a synchronous signal
as a low-level active synchronous request
signal, so the signal remains low until the
comma alignment is complete and high
when ILA and normal data are requested.
tx_data_ready_o
OUT
TX core ready to receive TX data
tx_data_sof_o
OUT
Start of frame boundary indication; this
signal is 4 bits, and is used to indicate the
frame first byte position in tx_data in the
clock cycle.
When tx_data_sof = 0001, the first
byte of the frame is located in bits [7:0]
of the tx_data word, and the next 3
bytes are located in bits [31:8].
When tx_data_sof = 0010, the first
byte is located in bits [15:8] of the
tx_data word and the next 2 bytes are
in bits [31:16]; bits [7:0] contain the
end of the previous frame.
When tx_data_sof = 0100, the first
byte is located in bits [23:16] of the
tx_data word and the next byte is in
bits [31:24]; bits [15:0] contain the end
of the previous frame.
When tx_data_sof = 1000, tx_data
contains the last 3 bytes of the
previous frame in bits [23:0] and the
first byte of the new frame is in bits
[31:24].
Note! Multiple bits of tx_data_sof can be

3 Functional Description
3.3 Port List
IPUG1019-1.0E
9(45)
Signal Name
I/O
Description
asserted in the same cycle, depending on
the bytes per frame (e.g., F = 1,
tx_data_sof = 1111).
tx_data_eof_o
OUT
End of frame boundary indication; this
signal is 4 bits, and is used to indicate the
frame last byte position in tx_data in the
clock cycle.
tx_data_somf_o
OUT
Start of multiframe boundary indication; the
position of the first byte of each multiframe
is encoded in the same way as
tx_data_sof.
tx_data_eomf_o
OUT
End of multiframe boundary indication; the
position of the last byte of each multiframe
is encoded in the same way as
tx_data_eof.
tx_data_i[32*N[1]-1:0]
IN
TX data; least significant byte is transmitted
first.
tx_tdata[31: 0] data is transmitted through
serial lane 0.
tx_tdata[63:32] data is transmitted through
serial lane 0.
tx_tdata[((N + 1) × 32) - 1:(N × 32))] data is
transmitted through serial channel N.
tx_debug_o[36*N[1]-1:0]
OUT
Debugging Interface
SerDes-related interfaces
gt_q0_qpll0_ok_o
OUT
Quad0 QPLL0 is locked; there is no this pin
if Quad0 QPLL0 is not used.
gt_q0_qpll1_ok_o
OUT
Quad0 QPLL1 is locked; there is no this pin
if Quad0 QPLL1 is not used.
gt_q1_qpll0_ok_o
OUT
Quad1 QPLL0 is locked; there is no this pin
if Quad1 QPLL0 is not used.
gt_q1_qpll1_ok_o
OUT
Quad1 QPLL1 is locked; there is no this pin
if Quad1 QPLL1 is not used.
gt_cpll_ok_o[N -1:0]
OUT
CPLL lock flag per lane
gt_fabric_rstn_i
IN
PMA reset of the lane connected to the
core
gt_pcs_tx_clk_o
OUT
Lane PCS TX clock; if it is multilane, the
first lane PCS TX clock is output by default.
gt_pcs_tx_rst_i
IN
TX PCS reset of the lane connected to the
core
gt_tx_fifo_wrusewd_o[5*N[1]
-1:0]
OUT
The used write data in lane TX FIFO
Note!
[1] N in the table means the number of lanes.

3 Functional Description
3.3 Port List
IPUG1019-1.0E
10(45)
3.3.2 RX Core Interface
The IO ports of the Gowin JESD204B IP RX core are shown in Figure
3-4.
Figure 3-4 Gowin JESD204B IP RX Core Port Diagram

3 Functional Description
3.3 Port List
IPUG1019-1.0E
11(45)
Table 3-2 I/O List of RX Core
Signal Name
I/O
Description
rx_rst_i
IN
RX core reset
1: Reset
0: Operating
rx_core_clk_i
IN
RX core clock, frequency = line
rate/40.
rx_cfg_clk_i
IN
Bus configuration clock, free-running
clock.
rx_cfg_rstn_i
IN
Bus configuration reset
rx_cfg_addr_i
IN
Bus configuration address
rx_cfg_sel_i
IN
Bus configuration selection
rx_cfg_ena_i
IN
Bus configuration enable
rx_cfg_wr_i
IN
Bus I/O signal
1：Write
0：Read
rx_cfg_rdata_o[31:0]
OUT
Bus read data
rx_cfg_wdata_i[31:0]
IN
Bus write data
rx_cfg_rdy_o
OUT
Bus ready signal
rx_cfg_strb_i[3:0]
IN
Bus strobe signal, fixed to 4’hf.
rx_sysref_i
IN
SYSREF input, this signal is required
when configured as subclass 1.
rx_sync_o
OUT
JESD204B defines a synchronous
signal as a low-level active
synchronous request signal, so the
signal remains low until the comma
alignment is complete and high when
ILA and normal data are requested.
rx_data_valid_o
OUT
RX data ready
rx_data_sof_o [3:0]
OUT
Start of frame boundary indication;
this signal is 4 bits, and is used to
indicate the frame first byte position
in rx_data in the clock cycle.
When rx_data_sof = 0001, the
first byte of the frame is located
in bits [7:0] of the rx_data word,
and the next 3 bytes are located
in bits [31:8].
When rx_data_sof = 0010, the
first byte is located in bits [15:8]
of the rx_data word and the next
2 bytes are in bits [31:16]; bits
[7:0] contain the end of the
previous frame.
When rx_data_sof = 0100, the
first byte is located in bits [23:16]
of the rx_data word and the next
byte is in bits [31:24]; bits [15:0]
contain the end of the previous
frame.

3 Functional Description
3.3 Port List
IPUG1019-1.0E
12(45)
Signal Name
I/O
Description
When rx_data_sof = 1000,
rx_data contains the last 3 bytes
of the previous frame in bits
[23:0] and the first byte of the
new frame is in bits [31:24].
Note! Multiple bits of rx_data_sof can
be asserted in the same cycle,
depending on the bytes per frame
(e.g., F = 1, rx_data_sof = 1111).
rx_data_eof_o [3:0]
OUT
End of frame boundary indication
This signal is 4 bits, and is used to
indicate the position of last frame
byte in rx_data in the clock cycle.
rx_data_somf_o [3:0]
OUT
Start of multiframe boundary
indication; the position of the first
byte of each multiframe is encoded in
the same way as rx_data_sof.
rx_data_eomf_o [3:0]
OUT
End of multiframe boundary
indication; the position of the last
byte of each multiframe is encoded in
the same way as rx_data_eof.
rx_data_o [N[1]*32-1:0]
OUT
RX data; least significant byte is
received first.
The RX data for serial lane 0 is
rx_data[31: 0]
The RX data for serial lane 0 is
rx_data[63: 32]
The RX data for serial lane N is
tx_tdata[((N + 1) ×32) - 1:(N ×32))]
rx_data_err_o [N[1]*4-1:0]
OUT
Byte error; This signal indicates there
is a single byte error in the data
stream. For example, a four-lane
interface has four 32-bit data
streams; the error signal is 16 bits,
and the 15th bit of the error signal
corresponds to the most significant
byte of lane 3, and 0th bit
corresponds to the least significant
byte of lane 0.
rx_debug_o [44*N[1]-1:0]
OUT
Debugging Interface
SerDes-related interfaces
gt_q0_qpll0_ok_o
OUT
Quad0 QPLL0 is locked; there is no
this pin if Quad0 QPLL0 is not used.
gt_q0_qpll1_ok_o
OUT
Quad0 QPLL1 is locked; there is no
this pin if Quad0 QPLL1 is not used.
gt_q1_qpll0_ok_o
OUT
Quad1 QPLL0 is locked; there is no
this pin if Quad1 QPLL0 is not used.
gt_q1_qpll1_ok_o
OUT
Quad1 QPLL1 is locked; there is no
this pin if Quad1 QPLL1 is not used.
gt_cpll_ok_o[N[1]-1:0]
OUT
CPLL lock flag per lane
gt_fabric_rstn_i
IN
PMA reset of the lane connected to