GOWIN RiscV AE350 SOC User manual

Gowin RiscV_AE350_SOC Quick Start
Manual
MUG1030-1.0E, 10/31/2023

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Revision History
Date
Version
Description
10/31/2023
1.0E
Initial version published.

Contents
MUG1030-1.0E
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Contents
Contents ...............................................................................................................i
List of Figures....................................................................................................iii
List of Tables.......................................................................................................v
1 About This Manual...........................................................................................1
1.1 Purpose .............................................................................................................................. 1
1.2 Terminology and Abbreviation ............................................................................................ 1
1.3 Support and Feedback .......................................................................................................2
2 Hardware Design .............................................................................................3
2.1 Hardware Target ................................................................................................................. 3
2.2 Software Version................................................................................................................. 3
2.3 Reference Design ............................................................................................................... 3
2.4 Related Documents ............................................................................................................3
2.5 Design Flow ........................................................................................................................3
2.6 Detailed Design ..................................................................................................................4
2.6.1 Create a Project...............................................................................................................4
2.6.2 IP Design ......................................................................................................................... 4
2.6.3 User Design ..................................................................................................................... 8
2.6.4 Constraints.....................................................................................................................10
2.6.5 Configuration ................................................................................................................. 11
2.6.6 Synthesis .......................................................................................................................13
2.6.7 Place & Route................................................................................................................13
2.6.8 Download.......................................................................................................................14
3 Software Design.............................................................................................16
3.1 Software Version............................................................................................................... 16
3.2 Reference Design ............................................................................................................. 16

Contents
MUG1030-1.0E
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3.3 Related Documents ..........................................................................................................16
3.4 Detailed Design ................................................................................................................16
3.4.1 Create a Software Project .............................................................................................16
3.4.2 Configure a Software Project.........................................................................................19
3.4.3 Target Configuration ......................................................................................................25
3.4.4 Build a Software Project ................................................................................................ 26
3.4.5 Download a Software Project ........................................................................................ 27
3.4.6 Debug a Software Project..............................................................................................28

List of Figures
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List of Figures
Figure 2-1 RiscV_AE350_SOC IP Core ............................................................................................5
Figure 2-2 Instruction Memory Configuration .................................................................................... 6
Figure 2-3 Data Memory Configuration ............................................................................................. 6
Figure 2-4 GPIO Configuration .......................................................................................................... 7
Figure 2-5 UART2 Configuration .......................................................................................................8
Figure 2-6 RiscV_AE350_SOC IP Design .........................................................................................9
Figure 2-7 PLL_ADV IP Design ......................................................................................................... 10
Figure 2-8 Synthesis Configuration.................................................................................................... 12
Figure 2-9 Place & Route Configuration ............................................................................................ 12
Figure 2-10 Synthesize ......................................................................................................................13
Figure 2-11 Place & Route ................................................................................................................. 14
Figure 2-12 Download Configuration ................................................................................................. 15
Figure 3-1 Create Project… ...............................................................................................................17
Figure 3-2 C Project ........................................................................................................................... 18
Figure 3-3 Select Configurations .......................................................................................................18
Figure 3-4 Build Settings....................................................................................................................19
Figure 3-5 Select Andes C Compiler > Directories ............................................................................ 20
Figure 3-6 Select Andes C Compiler > Optimization ......................................................................... 21
Figure 3-7 Select Andes C Compiler > Debugging............................................................................ 21
Figure 3-8 Select Andes C Compiler > Miscellaneous ...................................................................... 22
Figure 3-9 Select LdSaG Tool > General...........................................................................................23
Figure 3-10 Select Andes C Linker > General ................................................................................... 24
Figure 3-11 Select Objcopy (object content copy) > General ............................................................ 25
Figure 3-12 Target Configuration ....................................................................................................... 26
Figure 3-13 Build a New Project ........................................................................................................ 26

List of Figures
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Figure 3-14 Download Configuration ................................................................................................. 27
Figure 3-15 Build Mode Configuration ............................................................................................... 28
Figure 3-16 Create Debug Configuration...........................................................................................29
Figure 3-17 Select Debug Configurations > Startup .......................................................................... 29
Figure 3-18 Start Debugging..............................................................................................................30

List of Tables
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List of Tables
Table 1-1 Terminology and Abbreviations .......................................................................................... 1
Table 2-1 Physical Constraints for JTAG in Reference Design.......................................................... 10

1 About This Manual
1.1 Purpose
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1About This Manual
1.1 Purpose
This manual describes how to quickly create, configure, download,
and debug hardware projects and software projects using Gowin
RiscV_AE350_SOC Hardware Reference Design and Software
Programming Reference Design as examples, and is designed to help
users quickly learn the software and hardware development methods of
Gowin RiscV_AE350_SOC, to save development time and improve
development efficiency.
1.2 Terminology and Abbreviation
Table 1-1 shows the abbreviations and terminology used in this
manual.
Table 1-1 Terminology and Abbreviations
Meaning
Meaning
GPIO
Gowin Programmable IO
IDE
Integrated Development Environment
MCU
Micro Controller Unit
RISC-V
Reduced Instruction Set Computer V
SaG
Scattering and Gathering
SOC
System on Chip
UART
Universal Synchronous and Asynchronous Receiver/Transmitter

1 About This Manual
1.3 Support and Feedback
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1.3 Support and Feedback
Gowin Semiconductor provides customers with comprehensive
technical support. If you have any questions, comments, or suggestions,
please feel free to contact us directly using the information provided below.
Website: www.gowinsemi.com
E-mail: [email protected]

2 Hardware Design
2.1 Hardware Target
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2Hardware Design
2.1 Hardware Target
DK-START-GW5AT138 V2.0
-GW5AST-LV138FPG676AES
-GW5AST-138B
2.2 Software Version
Tested software version: Gowin Software Gowin_V1.9.9 Beta-3.
2.3 Reference Design
…\ref_design\FPGA_RefDesign\DK_START_GW5AT138_V2.0\ae350
_demo。
2.4 Related Documents
MUG1031, Gowin RiscV_AE350_SOC Hardware Design Reference
Guide
SUG100, Gowin Software User Guide
SUG940, Gowin Design Timing Constraints User Guide
SUG935, Gowin Design Physical Constraints User Guide
SUG502, Gowin Programmer User Guide.
2.5 Design Flow
Gowin RiscV_AE350_SOC IP design flow is shown below:
1. Use IP Core Generator tool in Gowin Software to configure and
generate RiscV_AE350_SOC IP design.
2. Configure the PLL_ADV IP option to generate a PLL_ADV IP design to

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provide clocking resources for the RiscV_AE350_SOC IP using IP
Core Generator.
3. In the hardware design, instantiate the RiscV_AE350_SOC IP,
instantiate the PLL_ADV IP, add other user logic designs, and connect
the modules to form a complete top-level design.
4. Use the physical constraints tool FloorPlanner in Gowin Software to
add physical constraints with the reference to the development board.
5. Use the timing constraints tool Timing Constraints Editor in Gowin
Software to add timing constraints with the reference to the software
timing analysis report.
6. Configure synthesis, Place & Route, and bitstream options.
7. Run the synthesis tool GowinSynthesis to synthesize
RiscV_AE350_SOC hardware design and generate the netlist file.
8. Run the Place & Route tool to generate the bitstream files.
9. Run Programmer to download the bitstream file.
2.6 Detailed Design
2.6.1 Create a Project
Double-click to open Gowin Software and create a new FPGA design
project.
For example:
Series: GW5AST
Device: GW5AST-138
Device Version: B
Package: FCPBGA676A
Speed: ES
Part Number: GW5AST-LV138FPG676AES
2.6.2 IP Design
Use IP Core Generator tool in Gowin Software to configure and
generate RiscV_AE350_SOC IP design.
Select "Soft IP Core > Microprocessor System > Hard-Core-MCU >
RiscV AE350 SOC 1.0" under IP Core Generator tab to open
RiscV_AE350_SOC IP Core, as shown in Figure 2-1.

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Figure 2-1 RiscV_AE350_SOC IP Core
Configure the corresponding functions, such as Instruction Memory,
Data Memory, GPIO and UART2, according to the application
requirements.
Instruction Memory
Double click to open "Instruction Memory".
Select "Embedded Instruction Memory" to enable the system
embedded SPI Flash Memory, as shown in Figure 2-2.

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Figure 2-2 Instruction Memory Configuration
Data Memory
Double click to open "Data Memory".
Select "Embedded Data Memory" to enable the system embedded
DDR3 memory, as shown in Figure 2-3.
Figure 2-3 Data Memory Configuration

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GPIO
Double click to open "GPIO".
Select "Enable GPIO" and "Enable GPIO I/O Ports" to enable GPIO
and GPIO "INOUT" ports, as shown in Figure 2-4.
Figure 2-4 GPIO Configuration
UART2
Double click to open "UART2".
If select "Enable UART2" is selected, UART2 is enabled, as shown in
Figure 2-5.

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Figure 2-5 UART2 Configuration
2.6.3 User Design
RiscV_AE350_SOC IP Design
Use IP Core Generator tool in Gowin Software to configure
RiscV_AE350_SOC IP, then click "OK", as shown in Figure 2-6.

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Figure 2-6 RiscV_AE350_SOC IP Design
PLL_ADV IP Design
Configure the PLL_ADV IP option to generate a PLL_ADV IP design
to provide clocking resources for the RiscV_AE350_SOC IP using IP Core
Generator.
Select "Hard Module > CLOCK > PLL_ADV 1.0" under IP Core
Generator tab, and configure and generate the PLL_ADV IP according to
the clock configuration in the reference design, as shown in Figure 2-7.
For example: PLL_ADV IP for RiscV_AE350_SOC core:
Clkout0: DDR clock
Clkout1: CORE clock
Clkout2: AHB clock
Clkout3: APB clock
Clkout4: RTC clock
PLL_ADV IP for RiscV_AE350_SOC DDR3 Memory:
Clkout0: DDR3 input clock
Clkout2: DDR3 memory clock

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Figure 2-7 PLL_ADV IP Design
Note!
RiscV_AE350_SOC's core clock is provided by "PLL_R[0] > clkout1" directly; it is
necessary to use "clkout1" of PLL_ADV IP to generate the core clock.
The DDR3 Memory clock of RiscV_AE350_SOC is provided by "PLL_L[0] > clkout2",
it is recommended to use "clkout2" of PLL_ADV IP to generate the DDR3 Memory
clock.
User Design
In the top module of hardware design, instantiate the
RiscV_AE350_SOC IP, instantiate the PLL_ADV IP, add other user logic
designs, and connect the modules to form a complete hardware design.
2.6.4 Constraints
Physical Constraint
Use the physical constraints tool FloorPlanner in Gowin Software to
add physical constraints with the reference to the development board.
For example, the connection for the JTAG interface of the reference
design DK-START-GW5AT138 V2.0 DVK Board with AICE-MINI+ is as
shown in Table 2-1.
Table 2-1 Physical Constraints for JTAG in Reference Design
JTAG Interface
DVK Board
AICE-MINI+
GND
J3-8
P3
TMS
J3-3
P4

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JTAG Interface
DVK Board
AICE-MINI+
TCK
J3-4
P6
VREF (3.3V)
J3-7
P7
TRST
J3-5
P10
TDO
J3-6
P11
TDI
J60-3
P12
Note!
RiscV_AE350_SOC's core clock is provided by "PLL_R[0] > clkout1" directly; it must
constrain the location of this PLL_ADV IP to "PLL_R[0]". For example, INS_LOC
"u_Gowin_PLL_AE350/PLL_inst" PLL_R[0].
The DDR3 Memory clock of RiscV_AE350_SOC is provided by "PLL_L[0] > clkout2",
it is recommended to constrain the location of this PLL_ADV IP to "PLL_L[0]". For
example, INS_LOC "u_Gowin_PLL_DDR3/PLL_inst" PLL_L[0]
Timing Constraints
Use the timing constraints tool Timing Constraints Editor in Gowin
Software to add timing constraints with the reference to the software
timing analysis report.
2.6.5 Configuration
Synthesis Configuration
Configure synthesis option based on the actual requirements of the
hardware design, as shown in Figure 2-8.
For example:
Top Module/Entity: ae350_demo_top
Verilog Language: System Verilog 2017

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Figure 2-8 Synthesis Configuration
Place & Route Configuration
Configure Place & Route option based on the actual requirements of
the hardware design, as shown in Figure 2-9.
For example, Dual-Purpose Pin: Use SSPI, MSPI and CPU as regular
IO.
Figure 2-9 Place & Route Configuration