Haier L42A9-AK User manual



L42A9-AK

No. Functions
1Screen size 42 inches(LG-PHILIPS) 26 Mute YES 2Aspect ratio 16:9 27 )URQWFDUG YES 3Brightness 500cd/m2 28 6LGH$9LQSXW YES 4Contrast Ratio(Darkroom) 800:1 29 6LGH86% YES
5Resolution 1366×768 30 DVI YES
6 Response Time˄ms) 10 31 YPvPr/YCbCr YES 7Angel of view 176o32 VGA YES
8Color displa
y
16.7M 33 AV input YES
9NO.of preset channels 256 34 AV output YES
10 OSD language (QJOLVK 35 S-video jack input YES 11 7RXFKNH\ Yes 36 (DUSKRQHRXWSXW YES 12 3D decoder Yes 37 RF input YES
13 3D comb filter Yes 38 PC automatic adjust YES 14 DNR Yes 39 Semitransparent menu YES 15 3A Window Yes 40 &KLOG/RFN YES 16 Color system PAL/AV NTSC/SECAM 41 Time of sleep timer(MINS) 240Min
17 Audio system DK,BG,IˈM/N 42 NO. of built-in speakers 2
18 AV stereo Yes 43 NO. of outer speakers 11
19 Surrounding sound Yes 44 Audio output power(Built-in)(W) 2*5W
20 NICAM Yes 45 Total power input˄W˅250W
21 0XVLFǃ7KHDWHUǃ6WDQGDUGǃ3HUVRQDO 0XVLFǃ7KHDWHUǃ6WDQGDUGǃ3HUVRQDO 46 Voltage range˄V˅AC150V~AC240V
22 Bass,Teble YES 47 Power frequency˄Hz˅50~60Hz
23 Balance YES 48 Approval None 24 Ear phone YES 49 Suitable market (J\SW
25 :RRI YES
)HDWXUHV
No. Functions /$$.

WARNING
*To avoid electric hazards, it is strongly suggested that the back cover not be opened, as
there is no any accessory inside the casing.
*If necessary, please contact authorized after-sales services.
*A lighting flash mark in a triangle: Apotentially hazardous situation, which, if not avoided,
could result in serious injury by high voltage.
*An exclamation mark in a triangle: Major part or accessory of which technical specifications
must be followed if it is to be replaced.
Warning:
To avoid fire or electric hazards, never place your television receiver in an area
with heavy moisture. Attention should be paid to avoid accidental scratches or
impacts onto the LCD screen.
WARNING
RISK OF ELECTRIC SHOCK
DO NOT OPEN
Caution:
Please read this manual carefully before using your television and keep this
manual in a good place for future reference.
To achieve the best performance of your television, read this User's Manual
carefully and properly store it for future reference.
Information of screen displays and figures in the User's Manual may vary due
to technical innovations.
Caution:
Unauthorized disassembly of this product is prohibited.
2. Safety precautions
TO REDUCE THE RISK OF ELECTRIC SHOCK DO NOT REMOVE COVER (OR BACK). NO
USER SERVICEABLE PARTS INSIDE. REFER TO QUALIFIED SERVICE PERSONNEL.

The product should be tightly fixed to avoid
drop damages and even fire.
To avoid fire hazards, do not use this
product under direct sunlight or closely
to heat sources.
Do not locate the product close to water
or oil, which may cause fire hazards.
Unplug the power supply and antenna of
the product when there is a rainstorm,
especially
Thunderstorm.
Do not use damaged or worn electric plugs
and keep electric cord away from heat sources
to avoid electric shocks or fire hazards.
Do not connect excessive sockets in parallel
or share the same socket by multiple plugs
to avoid fire hazards.
The product must be placed on a solid and
stable surface to avoid collapse.
Unauthorized disassembly of the television
is prohibited to avoid electric shocks or fire
hazards. Contact
authorized after-sales
service if technical
service is needed.
Keep the product away from a transformer
or heat source to avoid fire hazards.
Disconnect the product from power supply
and contact authorized after-sales service
if abnormal sound is heard in the product.

3. Images of Module and Circuit Boards
,PDJHVRIPDLQERDUGVXEDVVHPEO\
2. Images of tuner board subassembly

3. Images of USB board subassembly

4. Key IC Description& Trouble Shooting Guide
A: MAIN CHIP SUMMARY
U11 M30620: 16-BIT CMOS SINGLE-CHIP MICROCOMPUTER
The single-chip microcomputer operate using sophisticated instructions featuring a high level of instruction
efficiency. With 1M bytes of address space, they are capable of executing instructions at high speed. In addition,
this microcomputer contains a multiplier and DMAC which combined with fast instruction processing capability.
U1 SVP-EX52: VIDEO DECODER+DE-INTERLACE+SCALE
The SVP_EX-52 video processor is a highly integrated system on a chip device, targeting the converging
HDTV-ready and PC-ready and LCD TV, PDP TV, and DLP TV applications where high precision processing of
video and data are the requirements. SVP_EX-52 contains dual-purposed triple 10-bit high-precision and
high-speed video ADCs for both PC and video inputs, a high performance 5th generation multi-format 3D digital
comb video decoder that supports NTSC, PAL and SECAM, an HDTV sync separator, motion adaptive
de-interlacing engine, and the video format conversion engine,
U4 MST3788: 8-bit Analog and HDCP Interface for Advanced Digital Displays
The MST3788 integrates both analog interfaces and HDCP compliant receivers for enabling advanced
digital display devices such as digital TVs, plasma displays, LCD TVs and projectors to receive and display.
Compliant with the HDCP 1.0 specification, the MST3788 enables consumer electronic devices to receive
uncompressed, high quality, digital video HD content over a single, low-cost DVI cable.
UA11 MSP3450G: AUDIO DECODER
The MSP 34x0G family of single-chip Multistandard Sound Processors covers the sound processing of all
analog TV-Standards worldwide,
U3 K4D263238F: 128M DDR SDRAM
UA4 TPA3004: The TPA3004D2 is a 12-W (per channel) efficient,Class-D audio amplifier
fordrivingbridged-tied stereospeakers. The TPA3004D2 can drive stereo speakers as low as
4. The high efficiency of the TPA3004
eliminates the need for external heatsinks when playingmusic.Stereo speaker volume is
controlled with a dc voltage applied to the volume control terminal offering a rangeof gain
from ¨C40 dB to 36 dB. Line outputs, for driving external headphone amplifier inputs, are also
dc voltage controlled with a range of gain from ¨C56 dB to 20 dB. An integrated 5-V regulated
supply is provided for powering an external headphone amplifier.
UA5 74HC4052 : The 74HC4052 is high-speed Si-gate CMOS devices and are pin
compatible with the HEF4052B. They are specified in compliance with JEDEC standard no.
7A. The 74HC4052 is dual 4-channel analog multiplexers or demultiplexers with common
select logic. Each multiplexer has four independentinputs/outputs (pins nY0 to nY3) and a
common input/output (pin nZ). The common channel select logics include two digital select
inputs (pins S0 and S1) and an active LOW enable input (pin E). When pin E = LOW, oneof
the four switches is selected (low-impedance ON-state)with pins S0 and S1. When pin E =
HIGH, all switches arein the high-impedance OFF-state, independent of pins S0 and S1.

U8 SAA7117: The SAA7117(A)E/H is a consequent derivate of SAA7118 X-VIP
multistandard video decoder. In addition to its predecessor, it provides 10 bit A/D-
conversion, enhanced PAL/NTSC comb filtering, more versatile VBI data processing,support
of High Definition component video, picture improvement processing, and more robustness
with VCR-type signals.
B: Debug flow-chart
AC ON
Power board: NO
STANDBY +5V FOUND
Initialization:
YES
Powerfailure
Nonintegrity
GOOD
Whether alternating current
input
System Reset
Power On
+9V +12V +5V
+2.5V +3.3V +1.8V
FOUND
*Repair power board.
*Replace fuse.
*Check dc-dc circuit
and LDO circuit.
SvpEx Reset
Svpex E0 Good
SvpEx E0 error
*SvpEx no ack.
* SvpEx communicate with
MCU was wrong.
InitAppHas Accomplish
PICTURE DISPLAY
*Vs on
+60 +190 FOUND
*SvpEx communicate with
DDR was wrong.

Troubleshooting
For the sake of time and cost, it is strongly recommended that you check out
the problem byyourself according to the instructions listedhereunder before
contacting the after-sales service for technical assistance.
Note: Production of the screen requires high and precision technologies. However,
there might be some dark or bright (red, blue or green) spots, or some anomalistic stripes or
spots. This is not defect. If the TV set is used in an area 2,400 meters above the sea level where
the air pressure is below 750hpa, the picture on the screen may be affected and a muffled sound
might be produced. These phenomena might happen in the area 1,500 meters above the sea
level. This is resulted from difference between air pressures inside and outside the display. This
is not a defect covered by the limited warranty.
NOTE
Design and specifications are subject to change without notice.
The dimension in this manual is a approximation.
Note: Do not leave the television with static picture in an extended period as it may
result in residual image on your television screen.
ProblemPossibleremedies
Picture too big or small
One speaker failure
Slight sound from display
Turn on the power supply;
Properly plug theTV set to the powersocket;
Check to see if the power cable of other appliance is
plugged in the TV set. Make sure that the power cable
of the TV set is properly connected.
No picture,
no sound
Good picture,
no sound
Depress the volume button;
Check out theaudio frequency input signals.
Failure of remote
controller
Check to see if the remote controller display
receiving window are blocked by other objects and
if batteries are properly loaded.
No color,weak
color or poorpicture
Designate the item of color from the Picture menu
and depress the volume button;
Keep the display and VCR separate a reasonable space;
Activate some functions to store picture brightness;
Make sure that the display and signal source are
available and turned on.
Excessive brightness
or darkness Adjust brightness orcontrast.
Adjust the setupof sizes.
Balance the sound in the menu.
It is a normal phenomenon.

5 5
4 4
3 3
2 2
1 1
D D C C B B A A
SVP-EX
M30620SPGP
4M X32 DDR
5.Signal Flowing Chart
PQFP256
TV_PIP
FB
SVIDEO_1
HS, VS, CLK
CVBS_OUT 2Vp_p
SCART RGB
HS,VS, CLK
HS,VS, CLK
24-bit Data
24-Bit Digital Port
PRELIMINARY
SAA7117A
SCART1
SCART RGB
SCART
COMPOSITE
24-bit Data
SCART_FB
HDMI: MST 3388
Component 1
With 75 ohm
pull down
PC RGB PC_HS/VS
PC
IN_1
16-bit Data
CVBS_TV
SVIDEO_1
TV_PIP
DATA[7:0]
I2C
ADDRESS[18:0]
Differential Output
LVDS Output
CVBS_TV
FLASH MEMORY
TUNER IC OPTION
TV AND AUDIO DECODER
MAIN BOARD
TV&AUDIO BOARD
VIDEO AMP
DIGITAL
AUDIO
SCART_FB
SCART RGB
SCART RGB
SCART2
SCART
COMPOSITE
SCART RGB
CVBS_OUT 2Vp_p
I2C
CVBS1
AUDIO D/A AMP
AUDIO SW
SIF
PC AUDIO
AV AUDIO
YUV AUDIO
Component 2
30TR04C LCD TV_MAIN C-03 Block Diagram
)X]K R X :D O D V H\ 7HFK QRORJ \ /LPLW HG &RPSDQ\
C
830Tuesday, September 27, 2005
Title Size Document Number Rev Date: Sheet of

6.BUSControl Adjustment
To enter factory menu you can follow the steps:
1. Press V- to minish the voice value to 0.
2. Press “menu” on the TVset,you will see the list on the screen.
3.Press “menu”on the remote control, the list on the screen will disappear.
4.PressĀV-āthree seconds,then you will enter the factory menu
FactoryMenu
WhiteBalance
CR BlackBalance R value{0-255} def 0
CG BlackBalance G value{0-255} def 0
CB BlackBalance B value{0-255} def 0
WDRWhiteBalance R value{0-255} def 141
WDGWhiteBalance G value{0-255} def 141
WDBWhiteBalance B value{0-255} def 161
ColorTemp
Warm Offset ZRUNRQWKHUDQJHRIDGMXVWLQJ&5˖&5İ:DUP
GreenOffsetZRUNRQWKHUDQJHRIDGMXVWLQJ&5˖&5İ:DUP
ColdOffsetZRUNRQWKHUDQJHRIDGMXVWLQJ&5˖&5İ:DUP
1RWH˖<RXFDQSUHVV99WRDGMXVWwhite banlance and colortemperature
SetUp
Panel
Type1/Type2 The style of the panel
TunerPara
VL The value of VL{0-ffff} def 2288H
VH The value of VL{0-ffff} def 0C80H
UVH The value of VL{0-ffff} def 2288H
Device
Eeprom debug the parameter of the Eeprom
Svp debug the parameter of the Svp
7117 debug the parameter of the 7117
3288 debug the parameter of the 3788
Msp3450debug the parameter of the Msp3450
PinDect
SVideoDect Low/High Svideo check the low voltage level and the high voltage level
PhoneDect Low/High earphone check the low voltage level and the high
voltage level
Note : The parameters in this item are default value in system.
Feature
TimeJump On/Off

Favorite On/Off
FlyProg On/Off
Lock On/Off
SaveMode On/Off
HDM On/Off
USB On/Off
Sync On/Off
Video (work on with “MPPIP” and “MPSource” in the setting menu)
Video Bright
Contrast Bright value{0-100} def 85
Bright Bright value{0-100} def 90
Saturation Bright value{0-100} def 90
Hue Bright value{0-100} def 0
Sharp Bright value{0-100} def 60
Backlight Bright value{0-100} def 90
Video Stand
Contrast Stand value{0-100} def 80
Bright Stand value{0-100} def 70
Saturation Stand value{0-100} def 80
Hue Stand value{0-100} def 0
Sharp Stand value{0-100} def 50
BackLight Stand value{0-100} def 80
Video Soft
Contrast Soft value{0-100} def 80
Bright Soft value{0-100} def 75
Saturation Soft value{0-100} def 80
Hue Soft value{0-100} def 0
Sharp Soft value{0-100} def 50
BackLight Soft value{0-100} def 70
Saving Bright
Brightness value{0-100} def 80
Contrast value{0-100} def 70
Saving Normal
Brightness value{0-100} def 60
Contrast value{0-100} def 55
Saving Gray
Brightness value{0-100} def 50
Contrast value{0-100} def 50
Saving Dark
Brightness value{0-100} def 30
Contrast value{0-100} def 30
Video2
Max Min
ContrastMax value {0-63} def 38 (Tv,Av,Sav,Ypbpr)
Contrast Min value {0-63} def 10 (Tv,Av,Sav,Ypbpr)
Bright Max value {-128-127} def +31 (Tv,Av,Sav,Ypbpr)
BrightMin value {-128-127} def -42 (Tv,Av,Sav,Ypbpr)
Tv Satu Max value {0-127} def 45(Tv)

Tv Satu Min value {0-127} def 0(Tv)
BackLight Max value {0-100} def 50
BackLight Min value {0-100} def 0
Pc MaxMin
Pc Contrast Max value {0-255} def 90
Pc Contrast Min value {0-255} def 0
Pc Bright Max value {0-255} def 95
Pc Bright Min value {0-255} def 0
Hd Pc SatuMax value {0-127} def 120
HdPcSatuMin value {0-127} def 0
AvSatuMax value {0-127} def 85
AvSatuMin value {0-127} def 0
Dvi MaxMin
Dvi Contrast Max value (0-255) def 65
Dvi Contrast Max value (0-255) def 0
Dvi Bright Max value (0-255) def 160
Dvi Bright Min value (0-255) def 160
Note : Brightness and contrast numerical value range adjusting.<RXFDQSUHVV99WR
DGMXVWthem,
Audio
Audio Music
120Hz value(-50-50) def 40
500Hz value(-50-50) def 40
1.5KHz value(-50-50) def 30
5KHz value(-50-50) def 15
10KHz value(-50-50) def 15
Audio Theater
120Hz value(-50-50) def 45
500Hz value(-50-50) def 45
1.5KHz value(-50-50) def 45
5KHz value(-50-50) def 40
10KHz value(-50-50) def 40
Audio Standard
120Hz value(-50-50) def 15
500Hz value(-50-50) def 15
1.5KHz value(-50-50) def 15
5KHz value(-50-50) def 10
10KHz value(-50-50) def 10
Audio Set 1
Vol Min value(0-127) def 0
Vol Max value(0-127) def 105
Prescale FmAm value(0-127) def 120
Prescale Nicam value(0-127) def 120
Prescale Scart value(0-127) def 120
Prescale IIS1 value(0-127) def 16
Prescale IIS2 value(0-127) def 16
WooferMode value {Super,Normal} def Super

Audio Set 2
BalanceMode value{Linear,Logarith} def Linear
AvcDecaytime Spatial Effect High-Pass Gain
SurroundMode Value {Auto,Max,2/3,1/3,Min} Def Auto
HighResolution
ClippingMode
Woofer Prescale work when TralWoofer is open
WooferMode work when TralWoofer is open
Audio Set 3
Vol10 value (0-127) def 50
Vol20 value (0-127) def 80
Vol30 value (0-127) def 90
Vol50 value (0-127) def 100
RealWoofer on/off of the real and dummy woofer
Audio Set 4
HeadVolMin value (0-127) def 0
HeadVol10 value (0-127) def 50
Head Vol 20 value (0-127) def 75
HeadVol30 value (0-127) def 85
HeadVol10 value (0-127) def 95
Head Vol Max value (0-127) def 100
Audio2
Saving Noise
Vol ume
Balance
120Hz
500Hz
1.5KHz
5KHz
10KHz
Saving Normal
Vol ume
Balance
120Hz
500Hz
1.5KHz
5KHz
10KHz
Saving Quiet
Vol ume
Balance
120Hz
500Hz
1.5KHz
5KHz
10KHz
Note: Audio numerical value range adjusting

Setting
MPPIP
Only MP works
MP Source
DV_TV,DV_AV,DV_SAV,Ts_HDTV,Ts_PC,DVI
Marching to the value of Video Mode onTV,AV,SAV,HDTV,PC,DVI,such as
Video Bright, Video Stand, Video Soft
PIP Source no work
Factory on/off of the factory systerm
IAP IIC upgrading on-line
BusOff
EepReset Eeprom initializes
Note: When you leave the “FactoryMenu”,please make sure that the
Ā
Factory
ā
item is off.


7Circuit diagram





5 5
4 4
3 3
2 2
1 1
D D C C B B A A
PRELIMINARY
Connector for Amtel AT76C112 Video Output
PWMGPIOP_17
I2C Address:
7C/7D
Not
Populated
I2C Address:
7E/7F
MPU has
separated
Address/Data
MPU has
Data/Address
multiplex
if not a test pad, an enlarged via underneath the chip or exposed trace. Possible DQS MCLK exposed trace, DQ enlarged via
OUTPUT
MPUGPIO0 MPUCS0N
INPUT
MPUGPIO1 *CS1N MPUGPIO2 MPUGPIO3
0 0
0 0 1
1 11
1 1 1
11 1
11
1
11
1
0
0
0
0
*CS1N is not a input or output pin CS1N=0: SVP-EX CPU access enabled CS1N=1:SVP-EX CPU access disabled
For EX52 to use this table
33RX4 TO 100RX4
33RX4 TO 100RX4
30TR04C2 LCD TV_MAIN C2 SVP-EX 1 of 2
B
330Tuesday, June 06, 2006
Title Size Document Number Rev Date: Sheet of
MA0
MA4
MA3
MA7
MA6
MA11
MA10
MA2
MA9
MA1
MA5
MA8
DQS3
DQS2
DQS1
DQS0
DQM0 DQM1 DQM2 DQM3
AD7 AD6 AD5
AD2 AD3
AD4
AD0 AD1
SDA_EX SCL_EX
SCL_EX SDA_EX
P_17
MPUCS0N
MPUCS0N
MPUGPIO4
MPUGPIO4
MPUGPIO1 MPUGPIO0
MPUGPIO1
MPUGPIO2 MPUGPIO3
MPUGPIO0
P_17
MD19 MD4 MD1 MD18 MD11 MD30 MD15 MD10 MD9 MD6 MD2 MD28 MD3 MD14 MD5 MD20 MD0 MD25 MD12 MD31 MD13 MD21 MD16 MD24 MD26 MD8 MD17 MD22 MD29 MD23 MD7 MD27
A0
A7
A3
A2
A1
A6
A4
A5
MPUGPIO0
MD[0..31]
MA[0..11]
DQS[0..3]
DQM[0..3]
CAS# RAS# CS0#
CLKE BA0 BA1
MVREF MCLK0# MCLK0
A[0..7]
AD[0..7]
RD_EX WR ALE INT#
RST_SVP
WE#
BRT_CNTL
P_39
3V_SDA 3V_SCL
CS
FIELD
MPUGPIO0
E_PWM
VDDMQ
VDDMQ
VDDM VCC
VDDH3_3 VDDH3_3
VD3_3
VDDH3_3
VDDMQ
5V-1_CPU
C6 100nF
RP1
100Rx4
1 2 3 4
8 7 6 5
RP2 100Rx4
1 2 3 4
8 7 6 5
C4
68pF
R17 0R
R21
1K
R8 0R_DNS
FB35 150_Ohm_600mA
1 2
C3 100pF
R16
1K
C5 68pF
RP43
100Rx4
1
2
3
4
8
7
6
5
R19
10K_DNS
R10 68R
R20
10K_DNS
R1 1K5
R6 10R
R15
10K_DNS
C305 100nF
R9 68R
C306 100nF
C307 100nF
C308 100nF
C309 100nF
R5 4K7
+
C1
10uF/16V
C310 100nF
RP42
100Rx4
1
2
3
4
8
7
6
5
C312 100nF
Q1
MMBT3904
1
2 3
R2 4K7
C316 100nF
C2 100nF
C314 100nF
TP24 TP_T_C30
C315 100nF
C317 100nF
C313 100nF
C318 100nF
C320 100nF
C311 100nF
R18 10K
C319 100nF
SVP-EX [256]
(1 of 2)
U1A
SVP-EX_256
73 75 76 78 84 86 88 90 91 93 94 96
102 104 106 108 148 150 152 154 160 162 163 165 166 168 170 172 178 180 181 183
79 97
159 177
82
100
156
174
109
111
112
114
115
117
118
120
122
123
125
126
130
131
133
135
137
138
140
142 144 145 147
193
191
139
141
179
171
161
153
136
134
124
119
103
95
85
77
173
169
155
151
132
129
121
116
105
101
87
83
81
80
13 12 15 16 14 203 202 201 200 197 196 195 194 216 217 218 219 220 18 17
98
99
157
158
176
175
190
189
188
192
206
207
208
209
210
211
212
213
MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 MD8 MD9 MD10 MD11 MD12 MD13 MD14 MD15 MD16 MD17 MD18 MD19 MD20 MD21 MD22 MD23 MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31 DQM0 DQM1 DQM2 DQM3
DQS0
DQS1
DQS2
DQS3
MA11
MA10
MA9
MA8
MA7
MA6
MA5
MA4
MA3
MA2
MA1
MA0
MCK0
MCK0#
CS0#
CS1#
RAS#
CAS#
MVREF
WE#
CLKE
BA0 BA1
MPUGPIO0
MPUGPIO1
VDDR
VSSR
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VSSM
VSSM
VSSM
VSSM
VSSM
VSSM
VSSM
VSSM
VSSM
VSSM
VSSM
VSSM
VDDM
VSSM
RESET
TESTMODE
V5SF
SDA
SCL
A_D7 A_D6 A_D5 A_D4 A_D3 A_D2 A_D1 A_D0
RD#
WR#
ALE
MPUCS0N
INT#
FLD/IO
P_17
VSSM
VDDM
VDDM
VSSM
VSSM
VDDM
MPUGPIO2
MPUGPIO3
MPUGPIO4
NC
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
TPYY TP_T_C30 TPXX TP_T_C30
R7
10K
R12 10K
R13 4K7

5 5
4 4
3 3
2 2
1 1
D D C C B B A A
PRELIMINARY
Place this resistor close to EX chip
Place this resistor close to EX chip
Place this resistor close to EX chip
Place 75 ohm resistors close to SVP-EX
30TR04C2 LCD TV_MAIN C2 SVP-EX 2 of 2
B
430Tuesday, June 06, 2006
Title Size Document Number Rev Date: Sheet of
P_29
P_33
P_48
P_30
P_35
P_37
P_25
P_52
P_45
P_44
P_46
P_39
P_51
P_36
P_40
P_31
P_49
P_26
P_24
P_38
P_28
P_50
P_41
P_27
P_34
P_47
P_32
P_42
P_43
P_53
P_54
P_55
P_56
P_57
P_59
P_58
P_60
P_62
P_61
P_63
P_64
DIN23 DIN22 DIN21 DIN20
CVBS1 CVBS3
CVBS_OUTN
AIN_N3
CVBS_OUTP
PB_B2 CVBS2
CVBS1 CVBS3 CVBS2
C
PR_R1_G PB_B2 PB_B1_G PR_R2 Y_G2 Y_G2_G Y_G1 PR_R1 PR_R2_G PB_B1 Y_G1_G PB_B2_G
P_47 P_24 P_32 P_46 P_41 P_39 P_44 P_25 P_45 P_38 P_52 P_35 P_34 P_49 P_26 P_40 P_29 P_51 P_37 P_33 P_27 P_36 P_30 P_50 P_28 P_31 P_48 P_43 P_42 P_55 P_53 P_54 P_58 P_56 P_57 P_61 P_59 P_60 P_64 P_62 P_63
PR_R1_G
AIN_N1
CVBS2_G CVBS3_G
AIN_N2 PR_R2_G
PB_B2_G
AIN_N3
Y_G1_G Y_G2_G PB_B1_G
CVBS1_G
VREFN_1
VREFN_3
VREFP_1
VREFP_3
VREFN_2
VREFP_2
AVSS_ADC1
VREFN_2 VREFP_1 VREFN_3 VREFP_3 VREFN_1 VREFP_2
PAVDD1
PAVDD2
PDVDD
AVDD_ADC1
AVDD_ADC2
AVDD_ADC3
PAVDD
VDDL
VDDH
VSSL
VSSH
PDVDD
PAVDD1
PAVDD
PLF2
PAVSS1
PAVDD2
VDDL
VSSL
MLF1
AVDD_ADC3 AVDD_ADC2 AVDD_ADC1
AVSS_ADC1
PAVSS2
PAVSS1
PAVSS
PDVSS
AVSS_ADC3
AVSS3_BG_ASS
AVSS_ADC2
CVBS_OUTP
PDVSS PAVSS
PAVSS2
PLF2 MLF1
VDDH
AVDD3_AVSP2
AVDD3_AVSP2
AVSS3_BG_ASS AVSS_ADC3
AVSS_ADC3
AVSS_ADC2
AVSS_ADC2 AVSS_ADC1
PR_R1 Y_G1 PR_R2 PB_B1
C
Y_G2 AIN_N2
CVBS2_G
C_G
CVBS3_G CVBS1_G
AIN_N1
C_G
VSSH
CVBS_OUTN
DIN[0..23]
CVBS2_G CVBS1_G
CVBS
CVBS3_G
C_G Y/V1_M Y/C_C_M TV_IN
PB_B1_G VGA_BIN_G HD_PB VGA_RIN HD_PR VGA_GIN_G VGA_BIN Y_G1_G VGA_GIN VGA_RIN_G PR_R1_G HD_Y
P_50 P_31 P_44 P_40 P_51 P_30 P_37 P_24 P_38 P_34 P_27 P_41 P_28 P_32 P_33 P_26 P_29 P_36 P_49 P_39 P_35 P_48 P_47 P_25 P_46 P_52 P_45 P_43 P_42 P_53 P_55 P_54 P_56 P_58 P_57 P_59 P_61 P_60 P_62 P_64 P_63
CVBS_OUT_G CVBS_OUT_EX
VGA_VSIN VGA_HSIN
DHS_2EX DVS_2EX
DE_2EX
VD1_8
AGND AGNDAGND
VD1_8
AGNDAGND
VA1_8 VA1_8 VA1_8
AGND
VD1_8
VDDH3_3
AGND
VDDA3.3
VL1_8
VL1_8 VL1_8
3V3_SB
AGND
VDDA3.3
C29 100nF
R27 75R
C51
100nF
C36
10uF/16V
C23
100nF
C18
100nF_DNS
C27 100nF
C31 100nF
FB7
150_Ohm_600mA
1 2
C9 100nF
R30 75R_DNS
C43
10uF/16V
C40 100nF
R24 0R_DNS
C24 100nF
C16
100nF_DNS
C33 30pF
C42 2700pF
FB10
150_Ohm_600mA
1 2
Y1 14.318MHz
R31 75R
C49 100nF
C44 100nF
C39 10uF/16V
C20 100nF
R37
1K
C35 2700pF
C54 100nF
C321 100nF
C322 100nF
C32 10uF/16V
C34 100nF
C323 100nF
C324 100nF
C26
20pF
FB4
150_Ohm_600mA
1 2
C45 100nF
C41 10uF/16V R25 0R_DNS
R121 1K2 R125 1K5
C30 10uF/16V
C15 100nF
FB6 150_Ohm_600mA
1 2
R29 75R
FB9 150_Ohm_600mA_DNS
1 2
C71
100nF
R35 1K
FB5
150_Ohm_600mA
1 2
R33 75R
C220
10uF/16V
R36
1K
C13 100nF
C47 100nF
C11 100nF
C21
100nF
C50 10uF/16V
C12 100nF
SVP-EX [256]
(2 of 2)
U1B
SVP-EX_256
1
256
255
254
253
252
241
240
239
238
249 248 247 246 245 244 243 242 236 237
235
234
230
229
228
227
232 233 231
224
223
222
221
226 225
215 214
205
204
182 167 164 149 146 143
128
127
113 110 107
92 89 74
19
20
21 22 23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
40
41
9 8 3 6
10 11
7
5
4
2
38
39
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67 68 69 70 71 72
184 185
186
187
198 199 251 250
XTALO
XTALI
PAVSS
PAVDD
PDVSS
PDVDD
VREFP_1
VREFN_1
AVSS_ADC1
AVDD_ADC1
AIN_N3
Y_G2
AIN_N2
Y_G1
AIN_N1
CVBS3 CVBS2 CVBS1
CVBS_OUTP
CVBS_OUTN
AVSS3_BG_ASS
AVDD3_AVSP2
VREFP_2
VREFN_2
AVSS_ADC2
AVDD_ADC2
PB_B1 PB_B2
C
VREFP_3
VREFN_3
AVSS_ADC3
AVDD_ADC3
PR_R2 PR_R1
VSSC VDDC
VSSH
VDDH
VSSC VDDC VSSC VDDC VSSC VDDC
VDDL
VSSL
VDDC VSSC VDDC VSSC VDDC VSSC
VDDH
VSSH
H
V
DE
P_24
P_25
P_26
P_27
P_28
P_29
P_30
P_31
P_32
P_33
P_34
P_35
P_36
P_37
P_40
P_41
VDDC VSSC MLF1 PLF2
AIN_HS
AIN_VS
PAVSS2
PAVDD2
PAVSS1
PAVDD1
P_38
P_39
P_42
P_43
P_44
P_45
P_46
P_47
P_48
P_49
P_50
P_51
P_52
P_53
P_54
P_55
P_56
P_57
P_58
P_59
P_60
P_61
P_62
P_63
P_64
VDDH
VSSH
VDDC VSSC DIN23 DIN22 DIN21 DIN20 VDDC VSSC
VDDH
VSSH
VDDC VSSC VDDC VSSC
C55 100nF
FB36 150_Ohm_600mA
1 2
FB2
150_Ohm_600mA
1 2
C38 100nF
C7 100nF
R28 75R_DNS
C53
100nF
R32 75R
C56 100nF
C22 100nF
R26 75R-->100pF
C8 100nF
C57 100nF
C64 10uF/16V
C58 100nF
C59 100nF
C10 100nF
C60 100nF
R22 75R_DNS
R34 75R
C61 100nF
C48 10uF/16V
FB1
150_Ohm_600mA
1 2
C62 100nF
C19
100nF
C14 100nF
R23 75R
FB3 150_Ohm_600mA
1 2
C52
100nF
C37 100nF
C17
100nF_DNS
C46 10uF/16V
C63 100nF
FB8
150_Ohm_600mA
1 2
C25
20pF

5 5
4 4
3 3
2 2
1 1
D D C C B B A A
PRELIMINARY
EX42 EX52
P_24 AVSS33_3 PLL_VCC P_25 AVDD33 PLL_GND P_26 IRSET TXOUT3+ P_27 AVSS33_2 TXOUT3- P_28 B_OUT TXCLK+ P_29 G_OUT TXCLK- P_30 P_31 P_32 P_33 P_34 P_35 P_36
R_OUT TXOUT2+ VM TXOUT2- AVSS33_1 LVDSGND ADVDD33 LVDSVCC HS/O TXOUT1+ HSD/O TXOUT1- HFLB/O TXOUT0+
P_37 P_38 P_39 P_40 P_41 P_42 P_43 P_44 P_45 P_46
VS/O TXOUT0-
LVDSVDDP GPO/O VDDC VSSC
VDDC VSSC DIN19/I DIN18/I
P_47 P_48 P_49 P_50
DIN17/I DIN19/I DIN16/I DIN14/I DIN13/I DIN12/I
DIN18/I DIN17/I DIN16/I DIN15/I DIN14/I DIN13/I
P_51 P_52 P_53 P_54 P_55 P_56 P_57 P_58 P_59 P_60 P_61 P_62 P_63 P_64
CLK/I DIN7/I DIN6/I DIN5/I DIN4/I DIN3/I DIN2/I DIN1/I DIN0/I
DIN15/I
DIN15/I CLK/I DIN7/I DIN6/I DIN5/I DIN4/I DIN3/I DIN2/I DIN1/I DIN0/I NC NC DIN8/I DIN9/I DIN11/I DIN10/I VSSH VDDH
DIN8/I DIN9/I DIN10/I DIN12/I DIN11/I VSSH VDDH
CONNECTOR
Label "LVDS" in silk screen.
panel Power for PVDD
Digital Input Connector
30TR04C2 LCD TV_MAIN C2 SVP-EX Pin Configuration
B
530Tuesday, June 06, 2006
Title Size Document Number Rev Date: Sheet of
VDDC DIN13 TXOUT3+ TXOUT3- TXOUT2- LVDSVDDP TXOUT0+ VSSH TXOUT2+ DIN16 DIN12 LVDSGND TXCLK- TXOUT1- TXCLK+ DIN14 PLL_VCC VSSC TXOUT0- DIN15 PLL_GND VDDH TXOUT1+ LVDSVCC DIN17 DIN18 DIN19
VDDC
PLL_VCC
LVDSVDDP
LVDSVCC
DIN1 DIN9 DIN3 DIN6 DIN10 DIN7 DIN2 DIN8 DIN4 DIN11 DIN5 DIN0
DIN21 DIN6 DIN15 DIN22 DIN16 DIN18 DIN1 DIN3 DIN19 DIN4 DIN14 DIN13 DIN2 DIN7 DIN17 DIN11 DIN20 DIN23 DIN9 DIN8 DIN5 DIN10 DIN12
DIN0
TXOUT1--
TXOUT3--
TXCLK-
TXCLK++
TXOUT1-
TXOUT0++ TXOUT2+
TXCLK--
TXOUT0+
TXOUT3+ TXOUT2-
TXOUT2+
TXOUT0-
TXOUT3-
TXOUT2-TXOUT0--
TXOUT1++ TXCLK+
TXOUT3++
TXOUT1+
PLL_GND LVDSGND VSSC
TXOUT1++ TXOUT2++
TXOUT0--
TXCLK++ TXOUT0++ TXOUT3++
TXCLK-- TXOUT1-- TXOUT3-- TXOUT2--
3V_SCL
3V_SDA
DIN22
DIN16
DIN4
DIN19
DIN14 DIN5
DIN18 DIN11
DIN6 DIN15
DIN1
DIN21
DIN10
DIN12
DIN0 DIN3 DIN2
DIN13
DIN9
DIN7 DIN20
DIN17 DIN8
DIN23
P_24 P_25 P_30 P_28 P_26 P_27 P_29 P_35 P_33 P_31 P_32 P_34 P_40 P_38 P_36 P_37 P_39 P_48 P_46 P_44 P_45 P_47 P_41 P_51 P_49 P_50 P_52 P_42 P_43 P_58 P_53 P_59 P_54 P_62 P_55 P_60 P_61 P_56 P_57 P_63 P_64
PANEL_PWR
DIN[0..23]
CLK_2EX
3V_SDA
3V_SCL
CLK_2EX
DHS_2EX DVS_2EX DE_2EX
GPIO_CD
GPIO_CE
RST#
SCART_EN
VD3_3
VD1_8
VCC
3V3S
12V
PVDD
PVDD
VCC_USB
PVDD
3V3S PVDD
R41 10K
RP9 33Rx4_DNS
1 2 3 4
8 7 6 5
LP3 DLP31DN900ML4
1 2 3 4
8 7 6 5
CP3 10pFx4
1 2 3 4 5
6 7 8
U2 CEM9435A
1 2 3 4
8 7 5 6
S1 S2 S3 G
D1 D2 D4 D3
C73
100nF
R46 1K
C70 100nF
CP6 10pFx4
1 2 3 4 5
6 7 8
RP4 33Rx4_DNS
1 2 3 4
8 7 6 5
C65 100nF
CN1 12X2 2mm
1 3 5 7 9 11 13 15 17 19 21 23
2 4 6 8
10 12 14 16 18 20 22 24
R278 2K2
C66
22uF/16V
R52 68R
R50 33R_DNS
CP4 10pFx4
1 2 3 4 5
6 7 8
R47 0R_DNS
C72 100nF
RP7 33Rx4_DNS
1 2 3 4
8 7 6 5
CN2
1MM FPC CONNECTOR_DNS
12 34 56 78 910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
CP1 10pFx4
1 2 3 4 5
6 7 8
R38 0R
RP3 33Rx4_DNS
1 2 3 4
8 7 6 5
R39 0R R40 0R_DNS R42 0R_DNS R43 0R_DNS R44 0R_DNS R58 0R_DNS R14 0R_DNS
CP2 10pFx4
1 2 3 4 5
6 7 8
C68 100nF
R49 10K
R53 68R_DNS
Q2
MMBT3904
1
2 3
R51 68R_DNS
R54 68R_DNS
LP1 DLP31DN900ML4
1 2 3 4
8 7 6 5
C69 100nF
LP2 DLP31DN900ML4
1 2 3 4
8 7 6 5
CP5 10pFx4
1 2 3 4 5
6 7 8
R55 68R
R425 0R-->1K5
RP5 33Rx4_DNS
1 2 3 4
8 7 6 5
R48 10K
C475 1nF->47nF
C67 100nF
RP8 33Rx4_DNS
1 2 3 4
8 7 6 5
RP6 33Rx4_DNS
1 2 3 4
8 7 6 5

5 5
4 4
3 3
2 2
1 1
D D C C B B A A
SDRAM DECOUPLING CAPACITORS
PRELIMINARY
MEMORY DECOUPLING SCHEME
DDR_B2
DDR VDDMQ / VDDM de-caps
Each MD trace must be equal length. Each DQS trace must be equal length.
30TR04C2 LCD TV_MAIN C2 DDR
B
630Tuesday, June 06, 2006
Title Size Document Number Rev Date: Sheet of
DQ19 DQ16 DQ17 DQ18 DQ6 DQ3 DQ4 DQ7 DQ5 DQ1 DQ0 DQ2 DQ30 DQ28 DQ31 DQ29 DQ26 DQ27 DQ25 DQ24 DQ14 DQ15 DQ13 DQ10 DQ9 DQ8 DQ11 DQ12 DDQS
DQS2 DQS3
DQS0
DQS1
MCLK0
MA6-
DQ9 DQ25 DQ26
MCLK0#
MCLK0
DQM3- DQ8 DQ14 DQ27
DQ22 DQ21
DQ15
DQ3
MA11-
MA2-
DQ30
MA0-
MA3-
MA9-
DQ11
MCLK0#
MA4-
DQM0- DQM1-
DQ10 DQ13 DQ28 DQ31 DQM2-
MA5-
MA7-
MVREF
MA1-
MA8-
DQ17
DQ24
DQ18
DQ12
MA10-
DQ29DQ2
DDQS DQ0 DQ1 DQ4 DQ5 DQ6 DQ7 DQ16 DQ19 DQ20 DQ23
CAS#-
MA0-
CLKE- RAS#-
MA7- MA3-
CS0#- BA0-
MA2- MA1- MA5-
BA1- WE#-
MA4- MA6-
DQM2- DQM0- DQM3- DQM1-
DQM3 DQM0 DQM1 DQM2
MA2 MA8MA8-
MA11- MA9-
MA6 MA4 MA9 MA1 MA0
MA10- MA10
MA11 MA7 MA5 MA3
MD11 MD31 MD17
DQ22
MD27 MD29 MD22 MD16 MD19
DQ20
MD4 MD30 MD1 MD8 MD18 MD2 MD23 MD6 MD14 MD9
DQ23
MD13 MD26 MD20 MD21 MD28 MD25 MD0 MD5 MD15 MD10 MD7
DQ21 MD3
MD24 MD12
MD[0..31] DQS[0..3]
MCLK0#
MCLK0
CS0# BA0 RAS#
DQM[0..3]
CAS# WE# BA1
MVREF
CLKE
MA[0..11]
VDDM
VDDMQ VDDMQVDDMQ VDDM
VDDMQ
VDDM
VDDMQ
VDDMQ
RP12 33Rx4
1 2 3 4
8 7 6 5
C83 100nF
C300 100nF
C82 100nF
C89 100nF
R282 0R
RP11 33Rx4
1 2 3 4
8 7 6 5
C80 100nF
R62 1K
C78
10uF/16V
RP37 33Rx4
1 2 3 4
8 7 6 5
C84 100nF
C88 100nF
R56
51R
C79 10uF/16V
C87 100nF
RP13 33Rx4
1 2 3 4
8 7 6 5
C299 100nF
R57
51R
4M X 32 DDR
U3
TC59S6432CFT_4
53
55
28
26
27
25
23 56 24 57
31
32
33
34
47
48
49
50
51
45
36
29
30
94
54
87 88 90 43
2 8 14 22 59 67 73 58
15
35
65
97 98
100
1 3 4 6 7
60 61 63 64 68 69 71 729
10 12 13 17 18 20 21
74 75 77 78 80 81 83 84
5
11
62
52
70
76
16
46
66
79
96
95 86
99
92
82
19
85
38 39 40 89 41 42 44 91
37
93
CKE
CLK
CS
CAS
RAS
WE
DM0 DM1 DM2 DM3
A0
A1
A2
A3
A4
A5
A6
A7
A8/AP
A9
A10
BA0
BA1
DQS
CLK
NC NC NC NC
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
VREF
VDD
VDD
VDD
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
DQ8 DQ9
DQ10 DQ11 DQ12 DQ13 DQ14 DQ15DQ16
DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
VSSQ
VSSQ
VSSQ
MCL
VSSQ
VSSQ
VSS
VSS
VSS
VDDQ
VDD
VDDQ VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
NC NC NC NC NC NC NC DNC
A11
NC
C301 100nF
C303 100nF
C75 100nF
C81 100nF
C85 100nF
RP17 33Rx4
1 2 3 4
8 7 6 5
C76 100nF
RP38 33Rx4
1 2 3 4
8 7 6 5
RP14 33Rx4
1 2 3 4
8 7 6 5
RP36 33Rx4
1 2 3 4
8 7 6 5
C86 100nF
RP10 33Rx4
1 2 3 4
8 7 6 5
C77 10uF/16V
C74 100nF
RP39 33Rx4
1 2 3 4
8 7 6 5
R60 15R-->33R
R63 1K
RP15 33Rx4
1 2 3 4
8 7 6 5
C91 100nF
RP40 33Rx4
1 2 3 4
8 7 6 5
RP41 33Rx4
1 2 3 4
8 7 6 5
RP16 33Rx4
1 2 3 4
8 7 6 5