
I . I)roc_l t-,ti I fleficry
l"i1 op-.craticn5 prIformed by ihe DS?000 circuitty are deternrined
by sc(rirl,r'ri ial stcps in the 1,.:, r. erl prcgra . Thir Prcgranl, v"iliclr c()niains all
necessarv insiruclions for the tricrcpr,rt:cs-.or, li a(irltained in Pro'lrartlrlabic
ile ai-0rly Henrory (PRoM) . Iar1y DS20C0r LonL;ri]r 1-(rui J,;'pe 2;CS tra:.rirl(. PllC11i,
while the neu,Jesl versions conr-ain ar single masl.-1;i-C1t r;rrrr:rabit: R0l'1 T;oica1
sL!!rout incs ihal arc slorcd in lhe KSR PR0il arr; l<er'iboard (iacod;nq, charar:ler
siorage, speeC clranlie. c.-.de conversion, stal us iriocessor, :nd test flle:sage
generation. The p i-,.,,g rail irifcrmation stored in ircntory devicc.' is L-ften referred
to as "sof tr^riii-e" to distinguish it from the harcj-r.iired or "lrard,.'areI part cf
the system. The software in the DS2000 is iirstalleC in pluq-in !ockets,
as:,uring simpii replacernent if future sof i!i.lr.i-' upcli]le! aie rraLlc a"railable .
2. Text 5 toraqe liemory
The DS2000 KSR Iogic board conlains 3 kilobytc , of R.tndom-Acces:l
to store all text in the vicleo bul-fr:r (1728 cira;ac*.er:)
hidden buffer. six static RAl"1 lCs (each 1k x E l-.its)
whether it is being dispiayed or stored ;n the
Menro-y (RAM) , wh j ch
along l.rith the text
are used to store al
s used
n the
text,
h idden i i-ansm i t buffer.
3. z*80 cPU
The D0TCLK siqnal f rorn the CRT Controller is divided do!',/n to
generate the Z-80 clock and IIT signals. The fr equency of the non-maskable
interrupt is 2.1328 kHz, pr-oviding an interval of approximateiy 0.47 mS betv/een
NMls. The DS2000 software prograrq is interrupLed each time an N14l occurs,
providing a regular time-referenced "stopping point".
Two_Algna I s interface the Z-80
BUSEN. The H0LD signal is generated by
This signal goes to the BUSRQ input on
being performed and then removes itself
along with another Z-80 control signal
are used to enable or select al I ancil
from the l..1R2000 board is connected to
CPU with the CRT Controller: H0LD and
the CRTC to request control of the buses.
the Z-80, which completes the instruction
from the buses by tri-stating (going
-- ll0 Request (l0Rq) -- and address 'l ines
lary devices. The INTRP contrcl line
the maskable interrupt (tUf) on the Z-80.
to a high impedance) at all address- and data - bus connections. After the Z-80
has gone tri-state, it acknov./ledges the bus request with a BuSAR signal that is
used to enable the CRTC as a BUS Enable (AFSEN) signal.
Additionai control signals from the Z-80 are used to create Memory
write (tlEyWR), Memory nead (MElln) , t/O wri te -(10!ln), and l/0 nead (l0RD). These,
r.3 INPUT/OUTPUT SECT ION
(A b lock diagram depicting
is contained in Fiq. 1.4.)
Keyboa rd
ln the DS2000 KSR, the
memory device. Performing a part of
software, the Z-80 scans the keyboard
of the data lines, representing a key
the l/0 section circuitry in the DS2000
keyboard is treated as a read-only type
the main service routine in the system
natrix looking for a logic zero on one
press oo a specific key. lf a key press
4