Hal Communications DS2000 User manual

HAL DS2OOO KSR VIDEO DISPLAY TERI1INAL
CUSTOMER MAINTENANCE MANUAL
Copyright O 1981 by HAL Communications Corp., Urbana, lllinois. Printed in the
United States of America. Al l Rights Reserved. Contents of this publ ication
may not be reproduced in any form without the written permission of the copyright
owne r.
|4arch, 198l Pr int ing
PRINTEO IN U,S.A.

DS2OOO KSR CUSTOIV]ER IVIAINTENANCE IVIANUAL
P reface:
This DS2000 Customer Maintenance Manual provides technical information
about the circuitry of the DS2000 KSR terminal and presents a step-by-step
troubleshooting guide. The DS2000 has been designed in a modular arrangement,
and the troubleshooting guide is designed to isolate problems to specific
boards whenever possible. When the defective module is located, please contact
the factory (or authorized HAL distributor) so that arrangements can be made fo!"
repair of the module, This approach should expedi te repairs of units and reduce
the danger of shipping damage that might occur if the entire terminal were
returned for repair. Since special test fixtures are required to test circuitry
on each board, it is highly recommended that repair of the boards themselves
be left to the factory or authorized-distributor technicians,
This manual is organized in six sections, presenting a discussion of the
circuitry, disassembly procedures, specifications and limitations, trouble-
shooting, adjustments and options, and schematic diagrams. lt is recommended
that you give all sections at least a cursory reading before beginning any
Les ts or measuremenLs.
The troubleshooting flow diagram has been prepared to utilize on-screen
symptoms and l,z0 tests, minimizing the amount of external test equipment
required. A good 20,000 ohms-per-volt VOM may be the only piece of test equjp-
ment you need! An oscilloscope is not required by the procedures given, but
may prove usefu I .
Problems with the D52000 can be placed in three general categories: those
due to internal component failures, those due to a hostile environment, and
those due to operator nisunderstanding. As with al1 electronic equipment,
some failure of internal circuitry may occur, particularly during the first
few weeks of operation, However, the factory "burn-in" testing and the
conservative design of the DS2000 have shown this mode of failure to be rare.
Equipment failures due to application of improper l/0 connections or
voltages, lightning strikes, or a hostiie environment (water or excess heat) ,
vary with the user. Experience has shown thbt the DS2000 problems can often
be traced to these sources.
Experience has also shown that improper operator understanding of the many
features of the DS2000 is often interpreted as an equipment malfunction. Please
double check your operating procedures before 'rdigging-intorr the troubleshooting
checks -- you may save yourself a lot of time and effort! lf you discover
a potentially confusing instruction in any of the manuals, please let us at
the factory know so that future versions may be ammended. Use this DS2000
Customer l',laintenance Manual in conjunction with your DS2000 0peratorrs Manual
and 0peratorrs Guide.
ltt

DS2OOO KSR VIDEO DISPLAY TERIvlINAL
CusromrR lVlRtuteunucr MRuunl
CONTENTS:
PREFACE. ttt
SYSTEI.I DESCR I PT I ON I
l.l System Block Diagram. I
1.2 CPU/Memory Sect ion . 1
l. P rog ram Memory. 4
2. Text Storage Memory 4
3. Z-BO CPU. . 4
1.3 lnput/Output Section. 4
l. Keyboa rd. 4
2. f/0 Connections . .. .7
3. Receive Loop Detect . 7
I.4 Video Generator Section . 7
1.5 Audio Input lnterface Section (MR2000) .10
2. DISASSEMBLY OF THE DS2OOO.
2.1 Introduction.
2.2 Remova I of MR2000
2.3 Removal of Power Supply
2.4 Removal of Logic Board.
2.5 Reassembly of DS2000 KSR. 13
2
4.
I/O SPECIFICATIONS AND LIMITATIONS .I5
TROUBLESHOOTING PROCEDURES FOR THE DSzOOO KSR. .17
4.1 lnitial Connector Check .17
l+,2 Returning Equ i pment .17
4.3 Using The Flow Chart. .19
4.4 Troubleshooting Guide .19
2. Typ ica I Display?. .20
3. Loop, KOS and C\,/ Lines Key 0K?. .20
4. RX Morse 0K?. .21
5. Bell Tone 0K? .22
6. 0ther Problems.... ,22
4.5 RF- lnduced Problems ,22
\-6 Minimizing Rf-Related Problems/Antenna Seiect .26
ADJUSTMENTS AND OPT I ONS. ,29
5,I Sidetone Adjustments. .29
5-2 0ptional Sidetone output. .29
5.3 Modification for Operation/50-Hz Line Frequency .32
5.\ Modification for 0peration/69-Charact. Video Line .32
ILLUSTRAT IONS. .35
5.1 Table of Contents - lllustration Section.
E
6. .35

F I GU RES :
.I KSR Subassembly-0riented Block Diagram I
.Z DS20OO/MR2000 Block Diagram (functional). . . . .3
.3 CPU/Memory Section of DS2000 Circuitry, .5
.4 l/0 Section of D52000 Circuitry . 6
.5 Block Diagram of Video Section of DS2000. B
.6 Block Diagram of MR2000 Circuitry 9
3.
4.
Chassis Position for lnstallation/Removal of MR2000
DS2000 l/0 Connections.
Troubleshooting Flow Chart.
2
6
8
4..2
4.3
5.1
E,)
c1
5.4
o.l
o.z
6.3
6.4
6.5
6.6
o. t
6.8
6.9
6. i0
6.1r
Cable Arrangements and Use of Ferrite Materials to Reduce RF. .24
Simple RF-Bypass and Brute-Force Methods of RF El imination. .25
Location of Jumpers, Sidetone Vol. Pot and C, R", Rg. .30
DS2000 Sidetone Oscillator Component Selection Chart. .31
Location of Optional Sidetone-Output Circuit Pad rrSrr. .32
Location of Optional Sidetone-Output Connector Pin 3. .3\
CPU/Memory Schematic Diagram (A-1352) .36
lnput/0utput Schematic Diagram (A-,|353) .37
Video Generator Schematic Diagram (4-1354) .38
Power Supply Schematic Diagram (A-1355) .39
MR2000 Audio lnput lnterface (A-1354) .40
DS2000 External View of Complete Unit . .41
Cabinet Top Removed From Lower Chassis, . .\2
Lower Chassis with Top Section (logic board) Removed. .\3
Top View of Logic Board, Showing Keyboard ,44
Bottom View of Power Supply Board .\5
View of Back Side of MR2000 Board, Pot C E Connector .\6

THE DS2OOO KSR COIvll4UNICATIONS TERI4INAL
1. SYSTElvl DESCRIPTION
Circuitry of the DS2000 KSR is contained primarily on three printed
circuit boards (two, excluding the MR2OOO option). These are the power supply
board, the logic board, and the MR2000 Morse receive board, Fig. l.l shows
the basic interconnections between these subassemblies. Each subassembly has
a numerical designation, which is used to identify it. These designations
appear on each pc board to help make identification easier.
l.l System lllock Diagram
Fi9. 1.2 contains a functional block diagram of the entire KSR,
including the MR2000 option. Like other HAL terminals, the DS2O00 is designed
around a dedicated microcomputer, the heart of which is a type Z-80 B-bit
microprocessor lC. The Z-80, along with i ts associated anci I lary devices,
controls all KSR operations. The kinds of devices directly interfaced with
the Z-80 in the DS2000 are as follows: Read-0nly Memory (i,Ou), Random-Access
ttemory (RAM), Cathode-Ray-Tube Control Ier (CRT Control ter or CntC), Keyboard
Matrix, lnput/0utput (l/0) lnrerface Circuitry, and the MR2000 Morse Receive
Circuitry. Other devices, such as the line buffer, character generator, and
video combining circuitry, are interfaced directly with the CRT controller,
which can directiy access memory, as necessary, during video display routines.
Communication between the Z-80 and its ancillary devices is through
the bi-directional data bus, address bus, and control signals such as l/0
Read/write and Memory Read/write. Operation of the z-80 central processing unit
(CPU) requires that a multitude of commands, data and address information be
communicated on a common mul ticonductor data bus. A system of tri-state
buffer/driver devices actuated by commands from the Z-80 and gRT Controller,
along wi th two types of interrupts, ensure that inter-device communications
are carried out properly on this rrparty line,r, The two types of interrupts
used on the z-80 CPU are software maskable (lNT) and non-maskable (Ntii-).
Maskable interrupts can be " i g no reTil-6!--il-e CpU if rhey happen at other than
specific times during program execution, whereas non--maskable interrupts must
be serviced by the CPU as soon as it completes the current.program instruction
being executed. lnterrupts will be discussed in more detail when the circuitry
that generates them is analyzed.
The DS2000 KSR operates differently than all previous HAL amateur
terminals in that the Z-80 shares control of the address and control buses
with the 8350 CRT Controller, ln this system, the CRTC is said to be operating
in Direct-Memory Access (OUn) mode when it takes control of the buses from
the Z-80 CPU. How this system operates is explained in more detail in the
sections of text that deal with the CpU and CRTC.
1.2 CPUIMEMORY SECT ION
The CPU/Memory section of the
form in Fi9. 1.3, and schematical ly in KSR circuitry is shown in block-diagram
Fis.6.l.

VIDEO OUT
I/O LINES:
LOO P
CW KEYING
K0s
MORSE AF INPUT
FlG. 1.1 -- Block diagram of pc-board interconnections in DS2000.
POWER
SUPPLY
(D 1 r43)
PRO CESSO R/VID EO
BOARD WITH KEYBOARD
(D 1 139A)
MR2()OO MORSE AUDIO
INTEBFACE
(D 1 146)

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I . I)roc_l t-,ti I fleficry
l"i1 op-.craticn5 prIformed by ihe DS?000 circuitty are deternrined
by sc(rirl,r'ri ial stcps in the 1,.:, r. erl prcgra . Thir Prcgranl, v"iliclr c()niains all
necessarv insiruclions for the tricrcpr,rt:cs-.or, li a(irltained in Pro'lrartlrlabic
ile ai-0rly Henrory (PRoM) . Iar1y DS20C0r LonL;ri]r 1-(rui J,;'pe 2;CS tra:.rirl(. PllC11i,
while the neu,Jesl versions conr-ain ar single masl.-1;i-C1t r;rrrr:rabit: R0l'1 T;oica1
sL!!rout incs ihal arc slorcd in lhe KSR PR0il arr; l<er'iboard (iacod;nq, charar:ler
siorage, speeC clranlie. c.-.de conversion, stal us iriocessor, :nd test flle:sage
generation. The p i-,.,,g rail irifcrmation stored in ircntory devicc.' is L-ften referred
to as "sof tr^riii-e" to distinguish it from the harcj-r.iired or "lrard,.'areI part cf
the system. The software in the DS2000 is iirstalleC in pluq-in !ockets,
as:,uring simpii replacernent if future sof i!i.lr.i-' upcli]le! aie rraLlc a"railable .
2. Text 5 toraqe liemory
The DS2000 KSR Iogic board conlains 3 kilobytc , of R.tndom-Acces:l
to store all text in the vicleo bul-fr:r (1728 cira;ac*.er:)
hidden buffer. six static RAl"1 lCs (each 1k x E l-.its)
whether it is being dispiayed or stored ;n the
Menro-y (RAM) , wh j ch
along l.rith the text
are used to store al
s used
n the
text,
h idden i i-ansm i t buffer.
3. z*80 cPU
The D0TCLK siqnal f rorn the CRT Controller is divided do!',/n to
generate the Z-80 clock and IIT signals. The fr equency of the non-maskable
interrupt is 2.1328 kHz, pr-oviding an interval of approximateiy 0.47 mS betv/een
NMls. The DS2000 software prograrq is interrupLed each time an N14l occurs,
providing a regular time-referenced "stopping point".
Two_Algna I s interface the Z-80
BUSEN. The H0LD signal is generated by
This signal goes to the BUSRQ input on
being performed and then removes itself
along with another Z-80 control signal
are used to enable or select al I ancil
from the l..1R2000 board is connected to
CPU with the CRT Controller: H0LD and
the CRTC to request control of the buses.
the Z-80, which completes the instruction
from the buses by tri-stating (going
-- ll0 Request (l0Rq) -- and address 'l ines
lary devices. The INTRP contrcl line
the maskable interrupt (tUf) on the Z-80.
to a high impedance) at all address- and data - bus connections. After the Z-80
has gone tri-state, it acknov./ledges the bus request with a BuSAR signal that is
used to enable the CRTC as a BUS Enable (AFSEN) signal.
Additionai control signals from the Z-80 are used to create Memory
write (tlEyWR), Memory nead (MElln) , t/O wri te -(10!ln), and l/0 nead (l0RD). These,
r.3 INPUT/OUTPUT SECT ION
(A b lock diagram depicting
is contained in Fiq. 1.4.)
Keyboa rd
ln the DS2000 KSR, the
memory device. Performing a part of
software, the Z-80 scans the keyboard
of the data lines, representing a key
the l/0 section circuitry in the DS2000
keyboard is treated as a read-only type
the main service routine in the system
natrix looking for a logic zero on one
press oo a specific key. lf a key press
4

FROM CR]
OOT CLK
cRr2
*l TO CRTC
t0 R0
ADD. BUS DATA BUS
EKBSW
(T0 r/0 sEcTt0N)
MEMB
INTRP
(FBOM MB2O()t))
MEMW
IO RD
IOWR
r0 R0
FlG. 1.3 -- CPUlMemory section of DS2000 circuitry.
BUSAK
E[-usRo
CLK
2"80
Nmi
m
DECODE/SELECT
D E CO D E/SE LECT

BDAUX
E KBSW
AODRESS
LiNES
FROIV] I/O CI]NNECTOR
Ao
ro-WE
)
I
t
) T0 r/0 c0NNEcroR
I
I
)
TO SPEAKEB
FlG. 1.4 -- l/0 section of DS2000 circuitry,
cJ7
:)
od
F
o
DRIVERS CONTROL & SHIFT
KEYSWITCH ES
DRIVEBS KEYB OA R D
MAT R IX
BX IOOP
D ETECT
DECODE TX LOOP
KEYING
vo
LATCH CW KEYING
BELL TONE

is detected during the matrix scan, the program instructs the CpU to rrread
auxilliary'r by enabling the HIIIT control line. When this line is enabled
(active low) , the SHIFT and CTRL key switches are l/O read via two of the data
lines, The practical effect of this operation is that the keyboard is continually
being scanned for keypresses, and that when one is detected, the CPU checks to
see if it was combined with a SHIFT or CTRL keypress. The software keyboard-
decoding routine then assembles this information to determine the desired
characte r or funct ion.
2.
to gene ra te
the p rope r
bell-tone,
l/0 Connect ions
'The I /o I,/ r i te (JbIJ-wR) s i gna I
an enable for the l/0 latch
level s, as determined by the
cw-keying and TX-loop keying
Receive-Loop De te ct
is combined with address I ine CA6
used to set the various l/0 ports to
data received from the data bus. The
circuits are all driven by this latch.
3.
The output from the RX-loop detection circuit is fed to the same
drivers that place the keyboard-matrix information on the data bus. Thus, the
RX loop is read for high or low condition each time the keyboard is scanned.
r.4 V I DEO GENERATOR SECT ION
Fig. l.! shows the video generator section of the 052000 circuitry
in block diagram form. The main cornponent in the video circuitry is the
8350 CRTl,ontroller, which is interfaced with the CPU through control signals
such as H0LD and BUSEN (bus enable). Since the CRTC is capable of operating
in Direct-Memory Access (OltA) mode, there must be some way to remove the Z-80
CPU from the address and data buses when the CRTC requires them to do its job.
'hen the 8350 requires the next Iine of video information for storage in the
line buffer, it sends a HOLD command to the CPU, which sees this as a bus
request. After the Z-80 completes the instruction being performed, it tri-states
effectively removing itseif from the buses, and acknowledges CRT bus controi
by sending a bus enable (BUSEN)signal to rhe CRTC. The 8350 rhen accesses
memory to obtain the necessary text for the line buffer, When it is finished
using the address bus, the CRTC removes tf'" IbII- command, returning control to
the CPU. Since the CRTC and CPU use the IIID and BGEI- commands to "agree" as
to which device has control of the address bus, it might be said that they
,shake hands, via Lhese two lines. The I6LD and EISEI' commands are therefore
referred to as "handshaking'r signals.
When the CRTC addresses memory, the ASCII codes for the next character
row to be TV scanned are loaded into the line buffer, which feeds display
data to the character generator. The generator receives several timing
signals from the CRTC, as well as the DCTCLK signal. \.,/hen a new character row
of codes has been loaded, the character generator outputs the dot patterns for
the top scan line of the character row, fol lowed by the patterns for the
successive scan lines in the character row until the complete row is displayed.
Then, the next character row is loaded, and displayed scan-line by scan-line
as explained above. This continues until the entire contents of memory have
been loaded and displayed, after which the process is repeated.

ADDRESS BUS
DATA B US
CBT
CONTROLLER
50/60 Hz
NE BUFFE
DELAY
1CHR,
CHARACTE B
G EN EBATO B
R EVE RSE
VID EO MBIN E
CU BSO R
DOT CLK
BUSEN HOLD
JUMPER
DISPLAY
DATA B R IG HT/D IM
CO MPOSITE
VIDEO OUT
r- b-
* sotmn,
FIG. 1.5 -- Block diagram of video section of DS2000,

AF IN
800 Hz
CLOCK
cA3
IoW-F
CLOCK
INTBP
CA2, CAs, IORD
f = 7700-8600 Hz
COUNTER & INTERRUPT RESET
CO UNTER
OVERF LOW
NOTE: POTS B, C, F, AND L
ARE PRESET AT THE HAL
FACTO RY AND SHOU LD
NEED NO ADJUSTMENT.
O N/O FF
TRANSITION
TIMING & CW DATA
(TO DATA BUS)
DOUBLY
BA LAN CED
MIXER
POT B
BAND.PASS
FILTER
(fc=9000 Hz)
PLL
TONE
DECOD ER
(9000 Hz)
POT F
CAR R IER
OSCI LLATO R
LOW PASS
FILTER
(48 Hz) SLICEB EDGE
D ETE CTO R
15-B rT
COUNTER INTE R R UPT
LATCH
MULTIPLEX &
8US DRIVER
Flc. 1.6 -- Block diagram of l'1R2000 circuitry.

The serial stream of video (dot/no dot) information from the character
generator is inverted when a CURS0R signal is present, providing a reversed
character (black on white) at the position of the xmit cursor. output video
from this stage is combined with sync-signals in the video combiner, where
bright/dim .ontrol is supplied, as derived from display data line seven (DD7).
A delay in the bright/dim control line synchronizes the control with the video
informat ion.
A line-frequency control pin on the CRTC is connected through a
rrpull-up'i resistor to +5 volts (logic one) for 50-Hz operation. For 50-Hz
operation, this'l ine should be jumpered to ground, providing a logic zero
(lumpei 'rB" -- see section 5.3).
I .5 AUD IO INPUT IIITERFACE SECT ION (MR2OOO)
A block diaqram depicting the Morse audio processing circuitry in
the MR2000 is contained in Fig. 1.5. The circuitry is shown schematically
in Fig. 6.5. lncoming audio is heterodyned with the local oscillator, with
the sum of the two frequencies going through band-pass filtering.centered at
9000-Hr, Band-pass filter output is fed to a phase-locked looP (PLL) tone
decoder that is designed to detect ! kHz input signals' PLL output is low-
pass filtered before passing through a slicer stage, where the on-off keying
information is "squared uprr for use by the microprocessor. An edge detector
generates an output for each transition (leading edge or trailing edge). These
transitions are used to generate interrupts (lH-fRp)to tf,e processor. \{hen the
processor receives an trufhp command, it generates l0RD and selects address lines
two and three. These enable a multiplexer/dus driver used to place cw key-on/
key-off information (oAfA) and timing bits on the data bus. The local
oscillator generates a clock signal that is gated to a l5-bit counter that
provides the timing bits to the data bus. lOWR combined with address iine three
resets both the interrupt latch and the counter, while overflow from the counter
generates an INTRP command to the processor.
The balance of the KSR circuitry is contained on the power supply board
and in the cabinet wiring. This portion of the DS2000 is shown schematically
rn l-rg. b.q.
10

?. 'l ln the even t
)DISASSEMBLY OF THE DS2OOO
that you need to open the KSR cabinet to check voitages,
perform any other servicing function, BE SURE T0 READ THE
FIRST:
check connectors, or
FOLLO\,'I NG I NFORMATI ON
* >'.
,, WARN I NG ! )k
,t ALWAYS UNPLUG THE PoWER CoRD 7t
,.. FROM THE AC PO\,JER SOURCE BEFORE *
* OPEIIING THE KSR CABINET FOR ,K
;! SERVICING. *
Before beginning any disassembly of the DS2000 KSR, first disconnect
all external equipment by unplugging the l/0 connector, Morse AF input connector
(if MR2000 is installed) and the coaxial connector attached to the video output.
Turn off the KSR power switch and disconnect the captive line cord from AC power
source. Place the KSR on a protected work surface and remove the four phillips-
head screws that secure the KsR top section to the bottom chassis. Each of these
screws should have an internal-star lockwasher on it (early version KSRs rnay be
missing these lockwashers -- contact the factory or your distributor to obtain
these if your unit does not have them). Set the hardware aside and lift the
KSR top section straight up and off of the bottom chassis and lay it keyboard-
side down on the protected work surface. Use caution to ensure that none of the
interconnecting cables are strained during this operation.
2.2 Removal of the MR2000 l'lorse Receive Board
To remove the MR2000 from the KSR, set the bottom chassis of the DS2000
on its side with the bottom facing away from you (see Fig. 2.1). Unplug the
ribbon-cable DIP header plug from the socket on the DS2000 logic board, and
disconnect the powe r connectors (six-pin Holex) connecting the MR2000 to the
power supply board. Next, remove the 6-32 hardware (four sets of screw, spacer,
lockwasher and locknut) that secure the board to the 0S2000 bottom chassis.
Now the 14R2000 board can be removed from the 052000.'
z. tRemoval of the Power Supply Board
To remove the power supply board from the 052000, unscrew the four
phi llips-head screws that attach the board to the four stand-off sPacers on the
bottom chassis. Then disconnect the two cables going to the MR2000 and KSR logic
boards, disconnect the cable going to the transformer, and disconnect the cab'le
going to the pass transistor mounted on the rear panel. The power supply board
should now be free of the DS2000 bottom chassis.
2.4 Removal of the Logic Board
To remove the KSR 'logic board from the DS2000 top cover, unplug the DIP
header plug from the socket on the logic board, and unplug the power supply cable.
l'l

Flc. 2.1 -- Chassis Position for installation/removal of MR2000'
12

Next, remove the l/0 connector from the DS2000 rear panel by pressing the
retaining f'laps in (toward the connector shell) so that the connector shell
pops out through the hole in the chassis. Then fold the retaining flaps back
the other direction and feed the cable and connector back through the back-panel
hole to the inside. Now the top cover should be completely disconnected from
the bottom chassis. Remove the four screws that attach the 'logic board to
the top cover. Put them aside along with the four internal-star lockwashers
used between the pc board and stand-off spacer at each screw Iocation.
2 .5. Reassembly of the DS2000 KSR
ln general, any subassembly of the KSR that has been removed can be
reinstalled in the KSR chassis by following the above instructions in reverse
order. The following are special instructions concerning instal lation of
certa i n subassemblies.
l. [./hen instal I ing the l'1R2000, use caution when plugging the Dlp
header into the DIP socket on the logic board. Be sure that all of the pins
are Iined up with the socket holds before pressing the header into place. Also
be sure that the header is oriented properly with respect to the sosket (match
the colored dots, or align the beveled corners).
2. When installing the logic board i'n the KSR top cover, initially
do not tighten the four retaining screws all the way. Turn the top cover over
and inspect the key tops to ensure that they all actuate freely. lf some of
the key tops rub against the edges of the keyboard cut-out, adjust the spacing
by moving the keyboard assembiy slightly. When the proper spacing is achieved,
tighten the four retaining screws completely. Check key tops again to ensure
that they do not bind against the metal cover cut-out edges when they are
dep res sed.
13

3, ]/O SPECIFICATIONS AND L]IlITATIOI\S
Before making any connections to the DS2000 KSR (other than standard
RTTY or C\,/ interfacing as outl ined in the Ownerrs Manual) review the foilowing
specifications.
'! ;'r
., CAUT I 0N ! ,,i
;1 IMPROPER CONNECTIONS MADE *
,, TO KSR I/O PORTS MAY CAIJSE ,,.
,,! DAMAGE TO INTERNAL PARTS- ,K
lnput/0utput Data: (See Fig.3.l)
Loop current input (pins 1 and 4 on l/0 connector)
200 V max i mum.
120 mA maximum, lB mA minimum.
Morse audio input (pins I and 2 on audio connector)
10 V RMS maximum; 0.5 to 1.0 V P-P optimum.
Morse keying outputs (pins 7 and 9 on l/0 connector)
Transistor switches to ground, keying positive (cathode)
and negative (grid-block) voltage circuits simultaneously.
Rating: +150 VDC; l!0 mA maximum.
KOS output (pin 6 on l,/0 connector)
Transistor switch to ground, keying positive voltage circuits.
Rating: +200 VDC; 100 mA maximum.
Video output (s0-239 UHF connector)
75-ohm, 1.0 V P-P composite video output, compatible with
EIA RS-170 standards; peak video bandwidth = 5.1 l.1Hz (8-MHz
video bandwidth monitor recommended for good resolution).
15

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@o@
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TRANSM IT LOOP
RECEIVE LOOP
BAUDOT
OR
ASCII
I +lI
o-l
3 +-lI
4 -)
5 GND
6 KOS
7 CATH
8 GND
9 GRID
ODE KE
- BLOCK
INPUT,/OUTPUT CONNECTOR
Y OUT (POSITIVE)
KEY OUT (NEGATIVE)
PTIONAL SIDETONE OUT
(sEE SECTTON 5.2)
ROUND
uoto lN
l/0 connect ions .
MORSE AUOIO C ONN ECT OR
-- DS 2000
FlG. 3.r
16