Hal Communications MCEM-8080 User manual

MCEM-BOBO
MIC OCOMPUTER
SYSTEM

HAL MCEM-8080 MICROCOMPUTER SYSTEM
TECHNICAL MANUAL
*************************************************************
WARRANTY
The HAL Communications Corp. MCEM-8080 Microcomputer System is fully
guaranteed against defects in materials and workmanship for a period
of one year. Should repair or replacement parts be required
t
notify
HAL Communications torp. promptly. Please do not return your unit to
the factory for repair or adjustment until you have received a written
return authorization.
HAL Communications assumes no responsibility for the repair or replace-
ment of parts or units which have been damaged t abused
t
improperly
installed
t
or modified and reserves the right to change the design of
this equipment without incurring obligation to incorporate such changes
into existing units. Operation of this equipment with improper power
supply voltages (as described in this manual) will invalidate the
warranty.
**************************************************************
Copyright ~ 1976 by HAL Communications Corp.t Urbana, Illinois. Printed
in the United States of America. All rights reserved. Contents of this
publication may not be reproduced in any form without th~ written permis-
sion of the copyright owner.
April, 1976 Printing

MCEM-8080 MICROCOMPUTER SYSTEM
CONTENTS:
I.
SYSTEM COMPONENTS. . . ..... .
1.1
SOSOA Microprocessor ... .
1.2 Processor Control Circuitry.
1.3 Random Access Memory ...•
1.4 Read Only Memory ..•..•
1.5 Serial Input/Output (I/O) .
1.6 Parallel Data Input/Output. .
1.7
Bus Indicators and Control ..
1.S Connectors used on the MCEM-SOSO ••
2. INSTALLATION OF THE MCEM-SOSO ..... .
2.1
Initial Installation ...... .
2.2 Connection of Serial Input/Output Devices.
2.3 Connection of Power Supplies to the MCEM.
2.4 Connection of Parallel I/O Devices ..
2.5 I/O Connector Pin Assignments .•
2.6 Universal Processor Bus Connector
3. OPERATION OF THE MCEM-SOSO
3.1 Software Monitor ..
3.2 Monitor Subroutines
4. SYSTEM ADDRESS ASSIGNMENTS .•..
4.1 Random Access Memory (RAM) ..
4.2 Read On 1y Memory (ROM). • . . .
4.3 Input/Output (I/O) Assignments.
5. OPERATING HINTS .......•.
5.1 Power-on Start Up . . . . . .
5.2 Changing the Monitor Mode
.
5.3 Manually Writing a Memory Location.
5.4 Manually Jumping to a Program Address ...•.
5.5 ~anual1y Writing to an Output Port ..
5.6 Using the Break-point Register for Debug.
5.7 Using the E and R Commands for Debugging.
6.
PROGRAM EXAMPLES .
7.
SOFTWARE MONITOR LISTINGS.
8. CIRCUIT BOARD LAYOUT AND SCHEMATIC DIAGRAMS ..
9. APPENDiCES .......•............. ~
A. PROM, EPROM, ROM Connections and Markings.
B. Input/Output Jumper Connections ..•..
C. Addition of INTREQ, RESIN, and BUS EN to the UPB .
D. S080A Assembly Language Coding Forms ..
i i
..
.
.
1-1
1-1
1-1
1-1
1-2
1-2
1-3
1-3
1-5
2-1
2-1
2-1
2-9
2-9
2-10
2-12
3-1
3-1
3-5
. 4-1
4-1
4-1
4-2
5-1
5-1
5-2
5-3
5-3
5-4
5-4
5-4
6-1
7-1
S-l
9-1
9-1
9-6
9-10
9-12

TABLES:
Table 2.1
Table 2.2
Table 2.3
Table 2.4
Table 2.5
Table 2.6
ILLUSTRATIONS:
Figure 1. I
Figure 2. I
Figure 2.2
Figure 2.3
Figure ?4
Figure 2.5
Figure 8.1
Figure 8.2
Figure 8.3
Figure 8.4
Figure 8.5
Figure A. I
Figure A.2
Figure A.3
Figure A.4
Figure B.l
Figure B.2
Figure B.3
Figure C. 1
ASCI I Character Code •.
Baudot Character Code. .
Oscillator Frequency and Period.
Power Requirements and Connections
I/O Connections .••.......
Universal Processor Bus Connections.
MCEM-8080 Microcomputer System ..
EIA -RS-232C Serial I/O (standard jumpers).
Dual current loop serial I/O ..•
Single current loop serial I/O ..
Bit assignment and timing for parallel output.
Bit assignment and timing for parallel input
MCEM-8080 circuit board layout .•
Schematic drawing conventions .•.•
MCEM-8080 CPU Interface / Control.
MCEM-8080 Processor Memory . . •
MCEM-8080 Input/Output Interface
Memory jumpers for 3624-4 PROMs.
Memory jumpers for 8704 EPROM ...•
Memory jumpers for 8708 or 8308 ROMs
PROM color coding. . ....
EIA -RS-232C Serial I/O Jumper Locations.
Dual current loop serial I/O Jumper Locations.
Single current loop serial I/O Jumper Locations.
Addition of RESIN, BUSEN, and INTREQ to UPB •.•.
iii
2-2
2-3
2-5
2-9
2-10
2-12
iv
2-6
2-7
2-8
2-11
2-11
8-2
8-3
8-4
8-5
8-6
9-2
9-3
9-4
9-5
9-7
9-8
9-9
9-11

INTRODUCTION
The HAL MCEM-8080 Microcomputer System is a single printed-circuit
board computer that can be used for program development or for specific
control applications. The MCEM-8080 is designed around the Intel 8080A
single chip, 8-bit, N-channel microprocessor integrated circuit. The
MCEM-8080 printed circuit board contains the microprocessor IC,- its timing
and control circuitry. both Read Only Memory (ROM) and Random Access
Memory (RAM) integrated circuitry, and timing and control for Input / Out-
put (I/O) interfacing. Other accessories such as additional RAM, Keyboard/
Video Display unit, tape cassette memory, and power suppl ies can be used
with the basic MCEM circuit board. This manual discusses ONLY the basic
MCEM-BOBO board - the operation of the accessories is discussed in separate
manuals furnished with each unit.
The MCEM-8080A Microcomputer System manual is actually supplied in
two
publications: this MCEM-8080 Operating Manual, and the Intel 8080
Microcomputer Systems User1s Manual. Specific operating instructions
and specifications pertaining to the HAL Communications Corp. MCEM-8080
system are discussed in the MCEM-8080 Operating Manual. General information
relating to the 8080A and associated integrated circuits is discussed in
detail in the Intel 8080 Microcomputer Systems User's Manual (© Intel
Corporation). When pertinent, references are made in the operating manual
to the detailed discussions in the Intel manual. These referen~es are given
in the form: "Intel; pp A-xx to A-yy". In addition, a copy of the
Intel 8080 Assembly Language Reference Card (© Intel Corporation) is
furnished with the MCEM-8080 Microcomputer System to aid in program develop-
ment.
Figure 1. I MCEM-8080 Microcomputer System
iv

I. SYSTEM COMPONENTS
The HAL MCEM-8080 Microcomputer System contains the following basic
and optional components:
1.1 8080A Microprocessor
The 8080A is an eight bit microprocessor integrated circuit with
an instruction repertoire of 73 instructions. The execution time of
these instructions varies from 2.0 ~sec. to 9.0 ~sec. The 8080A integrated
circuit itself contains all of the circuitry required to address the memory,
address Input / Output (I/O) devices, and manipulate data. A more detailed
discussion of the 8080A will be found in pages 2-1 to 2-20 of the Intel
manual (Intel~. pp 2-1 to 2-20).
1.2 Processor Control Circuitry
Two additional integrated circuits are used in conjunction with the
808oA to provide all of the timing and control signals for the micro-'
processor system. These are the 8228 Bus Controller IC and the 8224 Clock
Generator IC.
1.2.1 8228 Bus Controller (Intel; pp 5-7 to 5-12)
A type 8228 integrated circuit is used to decode signals from the
8080A and generate the required bus control signals. This device also
buffers the 8080A data bus signals and will support a single vector
interrupt (RST 7).
1.2.2 8224 Clock Generator (Intel; pp 5-1 to 5-6)
A type 8224 integrated circuit generates all system timing signals.
An 18 MHz crystal is used with the device to generate the 2.0 MHz processor
timing signals, power-on reset signal and ready line synchronization pulses.
J.3 Random Access Memory
The standard MCEM circuit board is provided with 1024 bytes of Random
Access Memory (RAM). This memory can be used by the user's programs, but
the lower 64 bytes are required for the software monitor program. Additional
circuit board space is provided so that an additional 1024 bytes ("lK") of
RAM can be installed on the MCEM board (factory installation is recommended).
All
RAM integrated circuits should be type 8102A-4, a device featuring an
access time of 450 nsec. or less. Slower RAM devices should NOT be used as
they may cause improper operation of the system. Further information on the
8102A-4 is found on pages 5-79 through 5-82 of the Intel manual (Intel;
pp 5-79 to 5-82).
Within the processor memory space, the standard "IK" bytes of RAM
occupy locations between 0 and 1023 (0 - 3FF -Hex). The second (optional)
"IK" bytes of RAM occupy locations between 1024 and 2047 (400 H - 7FF H).
The software monitor uses RAM locations between 0 and 63 (0 - 3F H).
1-1

1.4 Read Only Memory
The MCEM system is provided with sufficient circuit board space for
4096 bytes of EPROM (Erasable Programmable Read Only Memory) or 2048 bytes
of bi-polar PROM (Programmable Read Only Memory - NOT erasable). The
device selection is made by selection of the proper circuit board jumpers.
Four socket locations are provided for the ROM - all four must be of the
same type (EPROM or PROM). The ROM occupies consecutive memory locations,
starting at 32,768 (8000 H).
1.4. I EPROM
Either a type 8708 or 8704 EPROM integrated circuit (Intel; pp 5-45 to
5-50) can be used on the MCEM board. The 8708 is a 1024 x 8 device and
the 8704 is a 512 x 8 device. Refer to Appendix A for proper jumper place-
ment.
1. 4.2 PROM
Type 3624 PROM integrated circuits can be used on the MCEM. This IC
is the standard device furnished with the MCEM. The 3624 is a bi-polar
PROM with a 512 x 8 organization. ' Up to four 3624 1s can be used on the
MCEM-8080 circuit board. NOTE: Production MCEM-8080 circuit boards are
jumpered for use of this device on the circuit board. If it is desired
to use other devices, refer to Appendix A for details.
1.4.3 ROM
A type 8308 ROM integrated circuit (Inte~; pp 5-59 & 5-60) can also be
used in
the HAL MCEM-8080. This is a mask-programmed version of the 8708.
Refer to Appendix A for jumper details.
1.4.4 Monitor Software ROM
The HAL software monitor can be resident in either 2-3624, 1-8708, or
l-83Q8 ROM integrated circuits. Either 2-3624 or 1-8308 ROM is standard
with the MCEM. The monitor software is 1024 bytes in length and begins at
location 32,768 (8000 H).
1.5 Serial Input / Output (I/O)
The standard MCEM-8080 provides for either synchronous or asynchronous
serial data interface. The software monitor supports asynchronous serial
I/O in either Baudot (5-unit) or ASCII (8-unit) codes.
1.5.1 8251 USART
A type 8251 integrated circuit (Intel; pp 5-135 to 5-146) Universal
Synchronous/Asynchronous Receiver/Transmitter (USART) is used to input and
output serial data. This device is fully programmable and is controlled by
the processor. Parallel-to-serial and serial-to-parallel conversions as
well as word length selection and parity are controlled by the 8251.
1-2

1.5.2 Serial Timing Oscillator
A type 555 integrated circuit timer is used to generate the serial
data baud rate. The data rate is screw-driver adjustable on the circuit
board. The actual 555 clock frequency is 4 times the baud rate in ASCI I
mode and 16 times the baud rate in Baudot mode.
1.5.3 EIA -RS-232C Data Interface
Two operational ampl ifiers (both halves of a type 145B Ie) are used
as RS-232 drivers and receivers. The serial output of the B251 USART is
directly converted to a ± 5 volt signal, with -5 volts representing the
"mark" signal condition and +5 volts as "space". The output impedance
of the circuit is approximately 400 ohms. For input data, an operational
amplifier is used as a sense ampl ifier and level converter. Input voltages
greater than +1.0 volts are interpreted to be in the "space
ll
condition and
those less than +1.0 volts as "mark". The input impedance is approximately
2700 ohms. This input will property sense TTL-level signals, as well as
EIA -RS-232C signals.
1.5.4 Current Loop Interface
Current loop signals with either 20 or 60 ma mark currents can also
be connected to the MCEM-BoBO. Two optical isolator integrated circuits
are ~sed to convert between the floating cur~ent loop circuit and the
RS-232 levels. These sensors are separated so that one can be used for
data input and the other for output (separate current loops - "full-
duplex" operation). The two circuits can also be series connected to
provide both data input and output on a single current loop circuit
("half-duplex" operation).
1.6 Parallel Data Input / Output
A type 8255 integrated circuit (Intel; pp 5-113 to 5-133) is provided
to allow parallel data interfacing. This device, called the "Programmable
Peripheral Interface
ll
, consists of three buffered B-bit parallel data ports.
The software monitor util izes the 8255 for parallel I/O operations.
1.7 Bus Indicators and Control
A number of indicators (small LEOs - Light Emitting Diodes) and switches
are installed along the front edge of the MCEM-BoBo circuit board to permit
evaluation and control of the processor operation.
1.7.1 Address Indicators
The entire 16 bits of the BOBo address bus are displayed on 16 LEDs.
The lamps are grouped in four-lamp clusters, four clusters total. Each
group
of four lamps represents a single hexadecimal (HEX) character, 0 through
F. An illuminated lamp indicates a logic "I" condition. Within a four-lamp
cluster, the least significant bit (LSB) is represented by the right-hand
lamp. Similarly, the right-hand cluster of four lamps represents the least
significant hexidecimal character.
1-3

1.7.2 Data Indication
Eight lamps (in two four-lamp clusters) are used to indicate the
state of the processor data bus. These lamps are immediately to the left
of the address lamps. As before, the right-hand lamp represents the LSB
and an illuminated lamp represents a logical 11111 for that bit.
1.7.3 Bus Control Indication
The four lamps on the extreme left end of the circuit board indicate
the state of the I/O Read, I/O Write, Memory Read, and Memory Write (left-
to-right order) signals from the processor. An illuminated lamp indicates
which of these operations is active. A complete description of the function
of these signals is found in the Intel manual (Intel; pp 5-7 to 5-12).
1.7.4 Manual Data Switches
Immediately in front of the eight data lamps are located two, four-
sectio~ miniature switches. The switches provide manual control of the
contents of the data bus. These switches can be used to enter data only
when the Data Bus Override (DBa) switch (to the right of the data switches)
is in the ON position. The data switch settings at any other time does
not affect the processor. The switches are arranged in the same manner as
the lamps, LSB to the right.
1.7.5 Run / Stop Switch
A miniature toggle switch on the right-hand section of the board
(labeled RUN - STOP) allows manual control of the 8080A Ready line. When
this switch is set to the RUN position, the processor will continue to
operate (unless halted by the program or some other control). When in the
STOP position, the processor is halted and only the manual STEP and RESET
switches will cause processor activity.
1.7.6 Reset Switch
The far right-hand push-button switch (labeled RESET) is a momentary
contact type that can be used to manually reset the 808oA. A reset operation
causes the program counter to set to zero and the interrupt flip-flop to be
cleared. Processor execution commences at location 0000 when the reset switch
is released. Appl ication of DC power supplies automatically issues a reset
function.
1.7.7 Single Step Switch
The STEP switch (located between the RUN - STOP and RESET switches)
allows manual stepping of the computer, one MEMORY cycle at a time. This
switch only functions when the processor has been halted by either the
RUN - STOP switch or the break point register. It is important to remember
that some instructions require more than one memory cycle and therefore more
than one operation of step switch to complete.
1-4

1.7.8 Break Point Register Switches
In the middle of the control area of the circuit board are located
four, four-section miniature switches. These 16 switches form a. "break
point register
l
•. Circuitry is provided to compare the value of this switch
register with the address bus and cause the 8080A to stop operation if the
two are equal. This function is similar to a programmable stop. Once the
808oA is halted due to a break point Ilmatch
ll
, it can only be caused to
continue running by either manual stepping with the STEP switch or by re-
setting the break point switches to a new value.
1.7.9 Memory Write and Output Write Switches
Two momentary switches are located on the far left-hand side of the
circuit board. These switches allow manual operation of memory or output
functions. The MEMORY WRITE switch will cause a manual memory write function
when depressed, overriding the normal bus control from the 8228 integrated
circuit. Similarly, depression of the OUTPUT WRITE switch will cause an
output write function, again overriding the normal control from the 8228.
1.8 Connectors used on the MCEM-8080
There are three connectors used on the basic MCEM-8080 circuit board.
These connectors are used for I/O Interface, Power Input, and connection
to the Universal Processor Bus. Mating connectors for each are furnished
wi th the MCEM.
1.8.1 I/O Interface Connector
Input / Output (I/O) connections to the MCEM are made through a 36 pin
circuit board edge connector (0.156
11
finger spacing, 18 pin double readout)
located on the left edge of the board. All three parallel I/O ports of the
8255 are available on this connector as well as connections for serial data.
The form of serial data to be used is selected with circuit board jumpers.
1.8.2 Power Connector
Power connections to the MCEM are made through the 12 pin edge
connector (0.156
11
finger spacing 6 pin double readout) located in the
upper right-hand corner of the circuit board. The MCEM requires ± 12 volt
and +5 volt power supplies.
1.8.3 Universal ~rocessor Bus Connector
Direct connection to the computer address, data, and control 1 ines
can be made through the 40 pin Universal Processor Bus (UPB) connector
located in the lower right-hand corner of the board. A mating connector
and attached ribbon cable are supplied for use of this feature. Connection
of options such as additional memory and the Keyboard/Video Display unit
is made through the UPB connector.
1-5

2. INSTALLATION OF THE MCEM-8080
2.1 Initial Inspection
Upon receipt of the MCEM-BoBO, unpack the circuit board and accessories
and inspect them for evidence of shipping damage. If evidence of shipping
damage is found, contact the carrier 'immediately. Before discarding the
packing material, check that all parts and accessories are accounted for.
If any are missing, please notify the factory or distributor in writing.
The following parts and accessories are furnished with the MCEM-BoBo:
Accessories and Parts:
40 pin Universal Processor Bus (UPB) connector with 2 ft.
of ribbon cable attached.
36 pin edge connector
12 pin edge connector
MCEM Operating Manual
Intel BoBo Microcomputer System User's Manual
Intel B080 Assembly Language Reference Card
2.2 Connection of Serial Input / Output Devices,
The MCEM-BoBo standard circuitry and software will support serial I/O
(Input/Output) operations in either the 7-unit ASCI I code OR the 5-unit
Baudot code at a variety of baud rates. The code to be used is selected
with circuit board jumpers. The MCEM-BoBo is usually factory connected
for the ASCI I code.
2.2.1 ASCII Serial I/O Operation
The ASCI I mode is selected by strapping pin 22 (DSR) of the B251
(circuit number 15, left edge of board) to ground (see Appendix B). In
ASCI I mode. all serial communications is performed with a 7-bit ASCII
format. This format is:
I s
tar.t bit (space)
7
data bits
I
parity bit
(set to
space)
2
stoE bits
(mark)
II bits per
character
The serial baud rate timing is screw driver adjustable from 100 to
600 baud. The unit is factory adjusted for 300 baud (30 characters per
second). As noted in section 1.5.2, the 555 timer is set to 16 ti.mes the
output baud rate (ego. 16 x 300 = 4Boo Hz for 300 baud). Table 2.1 contains
a list of the ASCI I character set used and their corresponding hexadecimal
values. Common ASCII baud rates and the corresponding oscillator frequencies
and periods are listed in Table 2.3. .
2-1

Table 2. I ASC II
Character Code
3 Most
Significant
Bits
0 2 3 4 5 6 7
0
NUL DLE
SPACE
0 @ P P
SOH
DCI
A Q a q
2 STX
DC2
II
2 B R b r
3
ETX
DC3
# 3 C S c s
4
EOT Dc4
$ 4 D T d t
III
.....
5
ENQ NAK
% 5 E U e u
co
.....
6
ACK
SYN
& 6 F V f v
C
III
7
BEL
ETB
7 G W g w
U
4-
8
BS CAN
( 8 H X h x
c
CJ)
9
HT EM
) 9 Y y
V> A
LF
SUB
it\. J Z j z
.....
III
III B
VT
ESC
+ K k {
C1l
-.oJ
C
FF
FS
< L \
-'T
D
CR
GS
M m }
E
SO RS
> N A n 'V
F SI
US
/ ? 0
RUB
a
OUT
ACK acknowledge FS
file separator
BEL bell
GS
group separator
BS
backspace
HT
horizontal
tabulation
CAN
cancel LF
line feed
CR carriage return
NAK
negative acknowledge
DCI device control 1
NUL
nu 11
DC2
=
device control 2
RS =
record separator
DC3
device
control
3
RUB
delete
(= DEL)
DC4 device control 4
OUT
DLE
data 1 ink escape
SI
shift in
EM
end of medium
SO
= shift
out
ENQ WRU = enquiry
SOH =
start
of heading
EOT
end of transmission
STX
start of text
ESC =
escape
SUB
substitute
ETB
end of transmiss ion block
SYN
synchronous idle
ETX end of text
US unit separator
FF
= form feed
VT
vertical tabu1 at ion
Mark =
logical
1
Data j s
transmitted
LSB first.
2-2

Table 2.2
Baudot Character Code
Most Significant
Bit (1)
Letters
Figures
0 0
0
BLANK T
BLANK
5
E Z 3 +
2
LF
L
LF
)
3 A W 2
III 4
SPACE
H
SPACE
#
~
co
5 S Y 6
~
6 P 8 0
e
ttl
U 7 u Q 7
<l-
e 8
CR
OJ 0
CR
9
In
9 D B $ 7
.j...I A R G 4 &
III
ttl
CIl
B J
FIG
BEL
FIG
...J
~
C N M
D F X /
E C V =
F K LTR
LTR
BEL
=
be 11
(or "')
BLANK
=
blank (non print or
space)
CR
= carriage return
FIG
figures case
LTR letters case
LF
= line feed
Mark = logical I
Data is transmitted. LSB first.
2-3

circuit board. THE MCEM-8080 CAN BE DAMAGED IF THE I/O CONNECTOR IS
REVERSED (particularly if connected to high-voltage current loop circuits).
2.6 Universal Processor Bus Connector
The processor bus of the 8080A can be extended with a 40 conductor
ribbon cable attached to the Universal Processor Bus (UPB) connector.
The total length of this cable should not exceed 24 inches. The total
external loads should not exceed three standard TTL loads on the address
and control 1 ines and 5, LOW CURRENT, bus receiver loads on the data lines.
The connections to the UPB connector are shown in Table 2.6.
Table 2.6
Universal Processor Bus
Connections
Pin
Function Pin
Function
Pin
Function
Al2
15
Al
29
AI4
2 +12
16 MEMR
30
(NC)
3
A10
17 A3
31
A15
4
+5
18
I/O R
32
Locating
5
A8
19 A5
33
DB0
6 Ground 20 I/O W
34
DB4
7
A6 21
A7
35
DBI
8 Ground 2Z
RESET
36
DB5
9
A0 23
A9
37
DB2
10
02
(TTL)
24
RDY
38
DB6
II
A2
25
A II
39
DB3
J2 (NC)
26 (NC) 40 DB7
13
A4
27 A13
14
MEMW 28 (NC)
Note: Connections with the (NC) designator may have a function assigned
but not connected on the factory standard units.
2-12
Key

3. OPERATION OF THE MCEM-8080
3.1 Software Monitor
The software monitor supplied with the MCEM-8080 properly interfaces
the serial I/O port, the parallel I/O ports, the keyboard display option,
or other user-defined I/O devices. The monitor allows the user to perform
the following operations. These commands are entered from the console.
3.1.1 Load hex (hexidecimal) files.
Large files can be loaded into the MCEM-8080 RAM from the reader device
by using the following format:
I~ ~~3~ r3[57. ·rl-_· ._._23 __ T __ :~~:H;~:LD
RECORD TYPE
L------------LOAD ADDRESS
L..- _____________ RECORD LENGTH
L---------------COLON
COLON:
All records must start with a COLON character. Any
characters preceding the COLON are ignored.
RECORD LENGTH: The number of load bytes in the data field is
specified as a number between 00 and FF (0 to 255).
This is a hexadecimal number and is either two characters
long or a single character followed by a comma
(i.e., 07 = 7,). If a zero length record is entered,
the load is terminated and control is restored to the
mon i tor.
LOAD ADDRESS: The memory location. into which the first byte of
the data field will be written is specified here.
Successive bytes in the data field will be written into
successively higher memory locations. This number is
either four characters long or less if terminated with
a comma (i.e., 032E = 32E,).
RECORD TYPE: The record type is specified here. With the present
version of the monitor (Version 1.1), all records are
of type zero (enter 00).
DATA FIELD: The actual data to be written into memory is specified
here. These are two character hex bytes and each pair of
characters is converted to eight bits to be loaded into
memory.
3-1

SUMCHECK: This hex byte represents the negative sum of all bytes
(the load address is two bytes) in the record. The
SUMCHECK value is such that, when modulo 256 is added to
all of the other bytes of the record, the total will equal
zero. This is a validity check on the record. If the
SUMCHECK fails, an ··X" will be printed on the serial
output device. However, the data will still be loaded
if the SUMCHECK fails.
The format used to specify a load file is:
L 0 t
p<-------carr i age Return (CR)
~-------Load offset (added to the load address
portion of the hex records to load memory
other than that specified, up to four
hex characters, 0000 - FFFF)
L----------L indicates load
L-----------------Prompting peri9d issued by the monitor
After receIvIng this command, the monitor will begin searching for
the first colon.
3.1.2 Dump or Display
The contents of memory can be dumped (or displayed) by specifying the
range to be dumped. The output generated is compatible with the load
command so that memory areas can first be dumped and then loaded. The
format of the Idump is in a number of hex records (of maximum length =
10 H) until the entire range is depleted. For clarity, spaces are
inserted between the various bytes but the monitor ignores spaces on
input so th~t the dumped file is compatible with the load file routine.
The dumped file is sent to the punch device. The command format is:
. D 300 , 400 ~
T .. T... TL-----Carriage Return (CR)
I L--~--------First undumped byte
L-------------------Comma separator
~---------------------First dumped byte
<------------------------0 (Dump) command
~--------------------------Monitor prompting period
This example command will cause display of all memory contents
between locations 300 H to 400 H - 1 as 16, 16 byte records. A zero
length record is always added at the end.
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3.1.3 Insert Memory Data
Individual locations in memory can be modified by using this command.
The
command format is:
82E t
T TL----Carriage Return (CR)
Starting memory address
'--------------1 (Insert) command
~---------------Monitor prompting period
The output generated is of the following format:
82E = 27
~pcesent memocy contents
Equals sign
'-------------Space character
~--------------Address
After this has been output, a comma is typed followed by a new byte
and when done, written into memory. If it is desired to leave the memory
location unchanged, any non-comma charqcter can be typed. After the new
data has been entered, the address is incremented and displayed again.
For example, consider:
. I 82E
(Insert memory command, generated by user)
82E
= 27 , 2E
----~--~Il['-----New data (entered by user)
L _______ Comma (entered by user)
'----------------Response by computer
82F
87
(Computer response indicating contents of
next location)
If any character between "G" and IIZII is typed instead of a hex
character, control returns to the monitor.
3.1.4 JUMP Command
Program control can be transferred to a specific location through the
JUMP command. This command can be used to "jump" to a user program or
subroutine. The format for this command:
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· J 23 }.
T T~------carr iage Return (CR)
Destination address
~-----------------JUMP command
L--------------------Prompting period issued by monitor
3.1.5 RETURN command
Program control can be transferred to a specific location and the
CPU registers restored to a predetermined value by executing a RETURN
command. The format of this command is:
R 283 t
T
TL----' -
------ Carriage Return (CR)
Destination address
L---------------RETURN command
L-------------------Prompting period issued by monitor
Twelve register values are restored by this command including:
Register
B
C
D
E
A (Accumulator)
PSW (Processor Status Word)
H
l
PC (PCH (high order program counter)
PCl (low order program counter)
SP (SPH (high order stack pointer)
SPl (low order stack pointer)
Stored at
Memory location
37
36
35
34
33
32
31
30
2F
2E
2D
2C
The initial. value (to be restored) of these registers can be set by
using an I (Insert) command to the memory location used for storage.
These locations are shown in the above list. Note that, during the
process of restoring the registers, the stack area indicated by SP
(SPH & SPl) is used as temporary storage and therefore SP should contain
a val id RAM address. If the destination address specified in the command
is zero, the destination is taken from the storage area.
3.1.6 STOP command
A STOP command can be initiated at any time at which the monitor is
expecting a control character by typing an IISII (or any other letter between
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"G" and "Z"). As explained in section 3.1.4, this will cause the command
to be aborted and control is returned to the mon i tor. The mon i tor wi 11
then issue a new prompting period.
3.1.7 EXIT command
An exit from a program to the monitor can be executed by entering
a RST 7 instruction or a CALL 38 H. The monitor, upon turn-on, establishes
an entry at 38 H from which it saves ALL CPU registers and status. This
command is intended to permit the examination of all CPU registers and
status while in the process of executing a program. The RST 7 instruction
saves the PC (Program Counter) on the stack and jumps to location 38 H.
From here, it jumps to a routine within the monitor which copies all
registers into a special RAM area. When finished, the address of the
initial RST 7 instruction is typed out as:
EXIT 232E (hexadecimal)
A prompting period is then issued by the monitor. At this point, the
I (Insert) command can be used to examine and/or change individual registers.
The memory location used to store the register values is listed under the
RETURN command.
The most
valuable use of the exii command is accomplished by inserting
a RST 7 (0FF H) instruction in the program sequence being de-bugged and an
automatic exit will be executed. The RETURN command can be used to return
to the program sequence. An interrupt will also cause the exit command to
be executed since a RST 7 is used as the interrupt vector.
3.2 Monitor Subroutines
Sever~1 general purpose subroutines are included in the software
monitor. Some of these subroutines are:
3.2.1 BEGIN (address 8000 H)
Th is subrout i ne allows genera I entrance to the mon i tor mode. It
initial izes all parameters and the USART.
3.2.2 CI (Console Input - address 8003 H)
CI is a conso)e input routine that will return an ASCI I character
(standard serial I/O) from the console control device and place the
ASCI I code in the A register. The contents of the A and PSW registers
are modified. Three levels of the stack are used by this operation.
3.2.3 RI (address 8006 H)
This routine is the same as the CI routine except that the character
is originated by the reader input device instead of by the console.
Serial ASCII I/O is standard.
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3.2.4 co (address 8009 H)
This subroutine causes an ASCI I character in the C register to be
output to the console device (serial I/O is standard). The contents of
the A and PSWregisters are modified and three stack levels are used
by this operation.
3.2.5 PO (address 800C H)
This routine is the same as the CO subroutine except that the ASCI I
character is output to the punch device (serial ASCII I/O is standard).
3.2.6 LO (address 800F H)
This routine is also similar to the CO routine with the exception
that the data is output to the list output device. As before, serial
ASCI I I/O is the standard code format.
3.2.7 . CSTS (address 8012 H)
This is a console status request subroutine which evaluates the
status of the console input device and returns A = 0 (zero value in the
A register) or A = 0FF H if an input character is waiting. Since the CI
subroutine will only return if a character is input, a call to CSTS can
be used
to determine if a call to CI is successful (will result in a
character being input and returned).
3.2.8 10CHK (address 8015 H)
10SET (address 8018 H)
A single memory location in RAM is used to define the four input /
output (I/O) devices. The logical devices available are:
CONSOLE:
READER:
PUNCH:
LI ST:
Referenced by CI, CO, CSTS
Referenced by RI
Referenced by PO
Referenced by LO
These logical devices can be "assigned" to anyone of the following
physical devices:
Serial I/O:
Keyboard / Display:
Parallel I/O:
User Defined I/O:
Uses the 8251 USART
Optional MCEM-KB/VDU Keyboard/Video Display Unit
Uses the 8255 Programmable Peripheral Interface IC
USRIN (address 40 H): A user input subroutine which will
return an ASCII character in the A register, similar in
operation to the CI subroutine.
USROT (address 43 H): A user subroutine, similar in function
to the CO subroutine, which will allow output to the user I/O
.
of an ASCII character in the C register.
3-6