hyperstone E1-16XS User manual

hyper stone E1-32XS / E1-16XS
32-Bit-RISC/DSP Microprocessor
User's Manual

Specifications and information in this document are subject to change
without notice and do not represent a commitment on the part of
Hyperstone AG. Hyperstone AG reserves the right to make changes to
improve functioning. Although the information in this document has been
carefully reviewed, Hyperstone AG does not assume any liability arising
out of the use of the product or circuit described herein.
Hyperstone AG does not authorize the use of the Hyperstone
microprocessor in life support applications wherein a failure or
malfunction of the microprocessor may directly threaten life or cause
injury. The user of the Hyperstone microprocessor in life support
applications assumes all risks of such use and indemnifies Hyperstone
AG against all damages.
No part of this manual may be reproduced or transmitted in any form or
by any means, electronic or mechanical, including photo-copying and
recording, for any purpose without the permission of Hyperstone AG.
Hyperstone is a registered trademark of Hyperstone AG
For further information please contact:
Hyperstone AG
Line-Eid-Strasse 3
D-78467 Konstanz
Germany
Phone (+49) 7531 / 9803-0
Fax (+49) 7531 / 51725
E-Mail [email protected]
www.hyperstone.com
Copyright 1990..2004 Hyperstone AG
Revision 02/2004

Table of Contents
Table of Contents
1. ARCHITECTURE...................................................................................................... 1-1
1.1. INTRODUCTION ....................................................................................................... 1-1
1.1.1. Compatibility:................................................................................................. 1-2
1.1.2. Phased Locked Loop: ..................................................................................... 1-2
1.1.3. Registers: ........................................................................................................ 1-2
1.1.4. Flags:.............................................................................................................. 1-2
1.1.5. Register Data Types: ...................................................................................... 1-3
1.1.6. External Memory:........................................................................................... 1-3
1.1.7. On-Chip Memory (IRAM): ............................................................................. 1-3
1.1.8. Memory Data Types: ...................................................................................... 1-3
1.1.9. Runtime Stack:................................................................................................ 1-3
1.1.10. Instruction Cache: ........................................................................................ 1-3
1.1.11. Instructions General:.................................................................................... 1-3
1.1.12. Instruction Summary: ................................................................................... 1-4
1.1.13. Exceptions: ................................................................................................... 1-5
1.1.14. Timer: ........................................................................................................... 1-6
1.1.15. Bus Interface: ............................................................................................... 1-6
1.1.16. Power Management: .................................................................................... 1-6
1.2. BLOCK DIAGRAM ................................................................................................... 1-7
1.3. GLOBAL REGISTER SET .......................................................................................... 1-8
1.3.1. Program Counter PC ..................................................................................... 1-9
1.3.2. Status Register SR......................................................................................... 1-10
1.3.3. Floating-Point Exception Register FER....................................................... 1-13
1.3.4. Stack Pointer SP ........................................................................................... 1-13
1.3.5. Upper Stack Bound UB ................................................................................ 1-13
1.3.6. Bus Control Register BCR............................................................................ 1-13
1.3.7. Timer Prescaler Register TPR...................................................................... 1-14
1.3.8. Timer Compare Register TCR ...................................................................... 1-14
1.3.9. Timer Register TR......................................................................................... 1-14
1.3.10. Watchdog Compare Register WCR ............................................................ 1-14
1.3.11. Input Status Register ISR............................................................................ 1-14
1.3.12. Function Control Register FCR ................................................................. 1-14
1.3.13. Memory Control Register MCR.................................................................. 1-14
1.4. LOCAL REGISTER SET........................................................................................... 1-15
1.5. PRIVILEGE STATES ............................................................................................... 1-16
1.6. REGISTER DATA TYPES ........................................................................................ 1-17
1.7. MEMORY ORGANIZATION..................................................................................... 1-18
1.8. STACK .................................................................................................................. 1-20
1.9. INSTRUCTION CACHE............................................................................................ 1-25
1.10. ON-CHIP MEMORY (IRAM) ............................................................................... 1-27
2. INSTRUCTIONS GENERAL ................................................................................... 2-1
2.1. INSTRUCTION NOTATION ........................................................................................ 2-1
2.2. INSTRUCTION EXECUTION ...................................................................................... 2-2
2.3. INSTRUCTION FORMATS.......................................................................................... 2-3
2.3.1. Table of Immediate Values ............................................................................. 2-5
2.3.2. Table of Instruction Codes ............................................................................. 2-6
2.3.3. Table of Extended DSP Instruction Codes ..................................................... 2-7

Table of Contents
2.4. ENTRY TABLES....................................................................................................... 2-8
2.5. INSTRUCTION TIMING........................................................................................... 2-12
3. INSTRUCTION SET ................................................................................................. 3-1
3.1. MEMORY INSTRUCTIONS ........................................................................................ 3-1
3.1.1. Address Modes ............................................................................................... 3-2
3.1.1.1. Register Address Mode:.......................................................................... 3-2
3.1.1.2. Postincrement Address Mode: ................................................................ 3-2
3.1.1.3. Displacement Address Mode: ................................................................. 3-2
3.1.1.4. Absolute Address Mode:......................................................................... 3-2
3.1.1.5. I/O Displacement Address Mode:........................................................... 3-3
3.1.1.6. I/O Absolute Address Mode: .................................................................. 3-3
3.1.1.7. Next Address Mode:................................................................................ 3-4
3.1.1.8. Stack Address Mode: .............................................................................. 3-4
3.1.1.9. Address Mode Encoding:........................................................................ 3-5
3.1.2. Load Instructions ........................................................................................... 3-6
3.1.3. Store Instructions ........................................................................................... 3-8
3.2. MOVE WORD INSTRUCTIONS................................................................................ 3-10
3.3. MOVE DOUBLE-WORD INSTRUCTION................................................................... 3-10
3.4. LOGICAL INSTRUCTIONS....................................................................................... 3-11
3.5. INVERT INSTRUCTION........................................................................................... 3-12
3.6. MASK INSTRUCTION............................................................................................. 3-12
3.7. ADD INSTRUCTIONS.............................................................................................. 3-13
3.8. SUM INSTRUCTIONS.............................................................................................. 3-15
3.9. SUBTRACT INSTRUCTIONS .................................................................................... 3-16
3.10. NEGATE INSTRUCTIONS...................................................................................... 3-17
3.11. MULTIPLY WORD INSTRUCTION......................................................................... 3-18
3.12. MULTIPLY DOUBLE-WORD INSTRUCTIONS ........................................................ 3-18
3.13. DIVIDE INSTRUCTIONS ....................................................................................... 3-19
3.14. SHIFT LEFT INSTRUCTIONS................................................................................. 3-20
3.15. SHIFT RIGHT INSTRUCTIONS............................................................................... 3-21
3.16. ROTATE LEFT INSTRUCTION............................................................................... 3-22
3.17. INDEX MOVE INSTRUCTIONS .............................................................................. 3-23
3.18. CHECK INSTRUCTIONS........................................................................................ 3-24
3.19. NO OPERATION INSTRUCTION ............................................................................ 3-24
3.20. COMPARE INSTRUCTIONS ................................................................................... 3-25
3.21. COMPARE BIT INSTRUCTIONS............................................................................. 3-26
3.22. TEST LEADING ZEROS INSTRUCTION .................................................................. 3-26
3.23. SET STACK ADDRESS INSTRUCTION ................................................................... 3-27
3.24. SET CONDITIONAL INSTRUCTIONS...................................................................... 3-27
3.25. BRANCH INSTRUCTIONS ..................................................................................... 3-29
3.26. DELAYED BRANCH INSTRUCTIONS ..................................................................... 3-30
3.27. CALL INSTRUCTION ............................................................................................ 3-32
3.28. TRAP INSTRUCTIONS .......................................................................................... 3-33
3.29. FRAME INSTRUCTION ......................................................................................... 3-35
3.30. RETURN INSTRUCTION........................................................................................ 3-37
3.31. FETCH INSTRUCTION .......................................................................................... 3-39
3.32. EXTENDED DSP INSTRUCTIONS ......................................................................... 3-40
3.33. SOFTWARE INSTRUCTIONS ................................................................................. 3-42
3.33.1. Do Instruction ............................................................................................ 3-43
3.33.2. Floating-Point Instructions........................................................................ 3-44

Table of Contents
4. EXCEPTIONS ............................................................................................................ 4-1
4.1. EXCEPTION PROCESSING ........................................................................................ 4-1
4.2. EXCEPTION TYPES .................................................................................................. 4-2
4.2.1. Reset ............................................................................................................... 4-2
4.2.2. Range, Pointer, Frame and Privilege Error .................................................. 4-2
4.2.3. Extended Overflow ......................................................................................... 4-3
4.2.4. Parity Error .................................................................................................... 4-3
4.2.5. Interrupt.......................................................................................................... 4-3
4.2.6. Trace Exception.............................................................................................. 4-4
4.3. EXCEPTION BACKTRACKING................................................................................... 4-4
5. TIMER AND CPU CLOCK MODES ...................................................................... 5-1
5.1. OVERVIEW.............................................................................................................. 5-1
5.1.1. Timer Prescaler Register TPR........................................................................ 5-1
5.1.2. Timer Register TR........................................................................................... 5-2
5.1.3. Timer Compare Register TCR ........................................................................ 5-3
5.1.4. Power-Down Mode......................................................................................... 5-3
5.1.5. Additional Power Saving................................................................................ 5-4
5.1.6. Sleep Mode ..................................................................................................... 5-5
6. BUS INTERFACE...................................................................................................... 6-1
6.1. BUS CONTROL GENERAL ........................................................................................ 6-1
6.1.1. Boot Width Selection ...................................................................................... 6-2
6.1.2. SRAM and ROM Bus Access .......................................................................... 6-2
6.1.3. DRAM Bus Access, Fast Page Mode or EDO DRAM.................................... 6-2
6.1.3.1. DRAM Row Address Bits Multiplexing ................................................. 6-3
6.1.4. SDRAM Bus Access ........................................................................................ 6-4
6.1.4.1. SDRAM Row Address Bits Multiplexing............................................... 6-4
6.1.4.2. SDRAM Mode Register Setting.............................................................. 6-5
6.1.4.3. SDRAM Connection ............................................................................... 6-5
6.2. I/O BUS ACCESS..................................................................................................... 6-6
6.3. BUS CONTROL REGISTER BCR............................................................................... 6-8
6.4. MEMORY CONTROL REGISTER MCR.................................................................... 6-12
6.4.1. MEMx Parity Disable................................................................................... 6-14
6.4.2. MEM2 Wait Disable ..................................................................................... 6-14
6.4.3. DRAMType and DRAMType2 ...................................................................... 6-15
6.4.4. Entry Table Map........................................................................................... 6-15
6.4.5. MEMx Bus Hold Break................................................................................. 6-15
6.4.6. MEMx Bus Size............................................................................................. 6-15
6.5. SDRAM CONTROL REGISTER SDCR................................................................... 6-16
6.5.1. BankAddrEnable........................................................................................... 6-16
6.5.2. CS1Enable .................................................................................................... 6-16
6.5.3. CS1Select ...................................................................................................... 6-17
6.5.4. CASLatency .................................................................................................. 6-17
6.5.5. SDCLKSelect ................................................................................................ 6-17
6.5.6. SDRAM Connection Example....................................................................... 6-17
6.6. INPUT STATUS REGISTER ISR............................................................................... 6-18
6.7. FUNCTION CONTROL REGISTER FCR.................................................................... 6-19
6.7.1. CLKOUTControl and CLKOUTControl2 .................................................... 6-21
6.8. WATCHDOG COMPARE REGISTER WCR ............................................................... 6-21
6.9. IO3 CONTROL MODES.......................................................................................... 6-21

Table of Contents
6.9.1. IO3Standard Mode....................................................................................... 6-21
6.9.2. Watchdog Mode............................................................................................ 6-21
6.9.3. IO3Timing Mode .......................................................................................... 6-21
6.9.3.1. On IO3Direction = Input:...................................................................... 6-22
6.9.3.2. IO3Direction = Output: ......................................................................... 6-22
6.9.4. IO3TimerInterrupt Mode ............................................................................. 6-22
6.10. BUS SIGNALS...................................................................................................... 6-23
6.10.1. Bus Signals for the E1-32XS Processor ..................................................... 6-23
6.10.2. Bus Signals for the E1-16XS Processor ..................................................... 6-24
6.10.3. Bus Signal Description............................................................................... 6-25
6.11. BUS CYCLES....................................................................................................... 6-30
6.11.1. SRAM and ROM Accesses.......................................................................... 6-30
6.11.1.1. SRAM and ROM Single-Cycle Read Access ..................................... 6-30
6.11.1.2. SRAM Single-Cycle Write Access ..................................................... 6-30
6.11.1.3. SRAM and ROM Multi-Cycle Read Access....................................... 6-31
6.11.1.4. SRAM Multi-Cycle Write Access....................................................... 6-31
6.11.2. MEM2 Read Access with WAIT Pin........................................................... 6-32
6.11.3. I/O Read Access ......................................................................................... 6-33
6.11.4. I/O Read Access with WAIT Pin................................................................. 6-34
6.11.5. I/O Write Access......................................................................................... 6-35
6.11.6. DRAM......................................................................................................... 6-36
6.11.6.1. Fast Page Mode DRAM Access.......................................................... 6-36
6.11.6.2. EDO DRAM Single-Cycle Access ..................................................... 6-37
6.11.6.3. EDO DRAM Multi-Cycle Access....................................................... 6-38
6.11.6.4. Fast Page Mode or EDO DRAM Refresh ........................................... 6-39
6.11.6.5. SDRAM Access .................................................................................. 6-40
6.12. DC CHARACTERISTICS ....................................................................................... 6-41
6.12.1. Absolute Maximum Ratings........................................................................ 6-41
6.12.2. D.C. Parameters......................................................................................... 6-41
6.13. AC CHARACTERISTICS ....................................................................................... 6-42
6.13.1. Processor Clock and CLKIN...................................................................... 6-42
6.13.2. GRANT# response time .............................................................................. 6-42
7. MECHANICAL DATA ............................................................................................. 7-1
7.1. HYPERSTONE E1-32XS, 144-PIN LQFP PACKAGE.................................................. 7-1
7.1.1. Pin Configuration - View from Top Side........................................................ 7-1
7.1.2. Pin Cross Reference by Pin Name ................................................................. 7-2
7.1.3. Pin Cross Reference by Location................................................................... 7-3
7.2. HYPERSTONE E1-16XS, 100-PIN LQFP PACKAGE.................................................. 7-4
7.2.1. Pin Configuration - View from Top Side........................................................ 7-4
7.2.2. Pin Cross Reference by Pin Name ................................................................. 7-5
7.2.3. Pin Cross Reference by Location................................................................... 7-6
7.3. HYPERSTONE E1-32XSB, 144-PIN TFBGA PACKAGE............................................ 7-7
7.3.1. Pin Configuration – View from Top Side....................................................... 7-7
7.3.2. Pin Cross Reference by Pin Name ................................................................. 7-8
7.3.3. Pin Cross Rreference by Location ................................................................. 7-9
7.4. HYPERSTONE E1-16XSB, 100-PIN TFBGA PACKAGE.......................................... 7-10
7.4.1. Pin Configuration – View from Top Side..................................................... 7-10
7.4.2. Pin Cross Reference by Pin Name ............................................................... 7-11
7.4.3. Pin Cross Rreference by Location ............................................................... 7-12
7.5. PACKAGE DIMENSIONS......................................................................................... 7-13

Table of Contents
7.5.1. Package Dimensions LQFP ......................................................................... 7-13
7.5.2. Package Dimensions TFBGA ....................................................................... 7-15

E1-32XS User’s Manual Page 1-1
1. Architecture
1.1. Introduction
The hyperstone E1-32XS and hyperstone E1-16XS microprocessors represent a further
development of the hyperstone E1-32X and hyperstone E1-16X processors. Using a
sophisticated 0.25 µm CMOS process, the maximum clock rate of the processor could be
further improved. Being pin-compatible to their predecessors these new processors can be
used as a direct replacement in existing designs, given that the changed voltage supply
requirements are considered.
This combination of a high-performance RISC microprocessor with an additional powerful
DSP instruction set and on-chip microcontroller functions offers a high throughput. The
speed is obtained by an optimized combination of the following features:
❒The most recent stack frames are kept in a register stack, thereby reducing data memory
accesses to a minimum by keeping almost all local data in registers.
❒Pipelined memory access allows overlapping of memory accesses with execution.
❒16 KByte fully static On-Chip Memory (IRAM).
❒On-chip Instruction Cache omits instruction fetch in inner loops and provides prefetch.
❒Variable-length instructions of 16, 32 or 48 bits provide a large, powerful instruction
set, thereby reducing the number of instructions to be executed.
❒Primarily used 16-bit instructions halve the memory bandwidth required for instruction
fetch in comparison to conventional RISC architectures with fixed-length 32-bit
instructions, yielding also even better code economy than conventional CISC
architectures.
❒Orthogonal instruction set.
❒Most instructions execute in one cycle.
❒Pipelined DSP instructions.
❒Parallel execution of ALU, DSP, and load/store instructions.
❒Single-cycle half-word multiply-accumulate operation.
❒Fast Call and Return by parameter passing via registers.
❒An instruction pipeline depth of just two stages — decode/execute — provides
branching without insertion of wait cycles in combination with Delayed Branch
instructions.
❒Range and pointer checks are performed without speed penalty, thus, these checks need
no longer be turned off, thereby providing higher runtime reliability.
❒Separate address and data buses provide a throughput of one 32-bit word each cycle.
The features noted above contribute to reduce the number of idle wait cycles to a bare
minimum. The processor is designed to sustain its execution rate with a standard SDRAM
memory.
The low power consumption is of advantage for mobile (portable) applications or in
temperature-sensitive environments.

Page 1-2 Architecture
Most of the transistors are used for the on-chip memory, the instruction cache, the register
stack and the multiplier, whereas only a small number is required for the control logic.
Due to their low manufacturing costs, the hyperstone E1-32XS and E1-16XS
microprocessors are very well suited for embedded systems applications requiring high
performance and lowest cost. To simplify board design as well as to reduce system costs,
the hyperstone E1-32XS and E1-16XS already come with integrated peripherals, such as a
timer and memory and bus control logic. Therefore, complete systems using hyperstone
microprocessors can be designed with a minimum of external components. To connect any
kind of memory or I/O, no glue logic is necessary. It is even suitable for systems where up
to now microprocessors with 16-bit architecture have been used for cost reasons. Its
improved performance compared to conventional microcontrollers can be used to
software-substitute many external peripherals like graphics controllers or DSPs. Using the
hyperstone E1-32XS as a core for ASICs or ASSPs is particularly advantageous because the
total gate count of the entire logic is just about 35k gates without the on-chip memory.
The software development tools include an optimizing C compiler, assembler, source-level
debugger with profiler as well as a runtime kernel and a sophisticated DSP library. Using
the runtime kernel, up to 31 tasks, each with its own virtual timer, can be developed
independently of each other. The synchronization of these tasks is effected almost
automatically by the runtime kernel. For the system designer, it seems as if he has up to 31
hyperstone microprocessors to which he can allocate his programs accordingly. Real-time
debugging of multiple tasks is assisted in an optimized way. The DSP library provides a
powerful set of DSP related functions and is taking care of all parallelism between ALU,
DSP, and Load/Store unit.
The following description gives a brief architectural overview:
1.1.1. Compatibility:
❒Pin compatible to hyperstone E1-32X and hyperstone E1-16X.
1.1.2. Phased Locked Loop:
❒An internal phased locked loop circuit (PLL) provides clock rate multiplication by a
factor ½, 1, 2, 4, or 8. For example, only an external crystal of 12 MHz is required to
achieve an internal clock rate of 96 MHz.
1.1.3. Registers:
❒32 global and 64 local registers of 32 bits each
❒16 global and up to 16 local registers are addressable directly
1.1.4. Flags:
❒Zero(Z), negative(N), carry(C) and overflow(V) flag
❒Interrupt-mode, interrupt-lock, trace-mode, trace-pending, supervisor state, cache-mode
and high global flag

E1-32XS User’s Manual Page 1-3
1.1.5. Register Data Types:
❒Unsigned integer, signed integer, single or double signed short, signed complex short,
single or double 16-bit fixed-point, bit string, IEEE-754 floating-point, each either 32 or
64 bits
1.1.6. External Memory:
❒Address space of 4 Gbytes, divided into five areas
❒Separate I/O address space
❒Load/Store architecture
❒Pipelined memory and I/O accesses
❒High-order data located and addressed at lower address (big endian)
❒Instructions and double-word data may cross DRAM page boundaries
1.1.7. On-Chip Memory (IRAM):
❒16 KByte fully static internal memory, 32 bit wide, single cycle access
1.1.8. Memory Data Types:
❒Unsigned and signed byte (8 bit)
❒Unsigned and signed half-word (16 bit), located on half-word boundary
❒Undedicated word (32 bit), located on word boundary
❒Undedicated double-word (64 bit), located on word boundary
1.1.9. Runtime Stack:
❒Runtime Stack is divided into memory part and register part
❒Register part is implemented by the 64 local registers holding the most recent stack
frame(s)
❒Current stack frame (maximum 16 registers) is always kept in register part of the stack
❒Data transfer between memory and register part of the stack is automatic
❒Upper stack bound is guarded
1.1.10. Instruction Cache:
❒An on-chip Instruction Cache reduces instruction memory access substantially
1.1.11. Instructions General:
❒Variable-length instructions of one, two or three half-words halve required memory
bandwidth
❒Pipeline depth of only two stages, assures immediate refill after branches
❒Register instructions of type "source operator destination ⇒destination" or

Page 1-4 Architecture
"source operator immediate ⇒destination"
❒All register bits participate in an operation
❒Immediate operands of 5, 16 and 32 bits, zero- or sign-expanded
❒Large address displacement of up to 28 bits
❒Two sets of signed arithmetical instructions: instructions set or clear either only the
overflow flag or trap additionally to a Range Error routine on overflow
❒DSP instructions operate on 16-bit integer, real and complex fixed-point data and 32-bit
integer data into 32-bit and 64-bit hardware accumulators
1.1.12. Instruction Summary:
❒Memory instructions pipelined to a depth of two stages, trap on address register equal to
zero (check for invalid pointers)
❒Memory address modes: register address, register post-increment, register + dis-
placement (including PC relative), register post-increment by displacement (next
address), absolute, stack address, I/O absolute and I/O displacement
❒Load, all data types, bytes and half-words right adjusted and zero- or sign-expanded,
execution proceeds after Load until data is needed
❒Store, all data types, trap when range of signed byte or half-word is exceeded
❒Move, Move immediate, Move double-word
❒Logical instructions AND, AND not, OR, XOR, NOT, AND not immediate, OR
immediate, XOR immediate
❒Mask source and immediate ⇒destination
❒Add unsigned/signed, Add signed with trap on overflow, Add with carry
❒Add unsigned/signed immediate, Add signed immediate with trap on overflow
❒Sum source + immediate ⇒destination, unsigned/signed and signed with trap on
overflow
❒Subtract unsigned/signed, Subtract signed with trap on overflow, Subtract with carry
❒Negate unsigned/signed, Negate signed with trap on overflow
❒Multiply word ∗word ⇒low-order word unsigned or signed, Multiply word ∗word ⇒
double-word unsigned and signed
❒Divide double-word by word ⇒quotient and remainder, unsigned and signed
❒Shift left unsigned/signed, single and double-word, by constant and by content of
register
❒Shift right unsigned and signed, single and double-word, by constant and by content of
register
❒Rotate left single word by content of register
❒Index Move, move an index value scaled by 1, 2, 4 or 8, optionally with bounds check
❒Check a value for an upper bound specified in a register or check for zero
❒Compare unsigned/signed, Compare unsigned/signed immediate

E1-32XS User’s Manual Page 1-5
❒Compare bits, Compare bits immediate, Compare any byte zero
❒Test number of leading zeros
❒Set Conditional, save conditions in a register
❒Branch unconditional and conditional (12 conditions)
❒Delayed Branch unconditional and conditional (12 conditions)
❒Call subprogram, unconditional and on overflow
❒Trap to supervisor subprogram, unconditional and conditional (11 conditions)
❒Frame, structure a new stack frame, include parameters in frame addressing, set frame
length, restore reserve frame length and check for upper stack bound
❒Return from subprogram, restore program counter, status register and return-frame
❒Software instructions, call an associated subprogram and pass a source operand and the
address of a destination operand to it
❒DSP Multiply instructions:
signed and/or unsigned multiplication ⇒single and double word product
❒DSP Multiply-Accumulate instructions:
signed multiply-add and multiply-subtract ⇒single and double word product sum and
difference
❒DSP Half-word Multiply-Accumulate instructions:
signed multiply-add operating on four half-word operands ⇒single and double word
product sum
❒DSP Complex Half-word Multiply instruction:
signed complex half-word multiplication ⇒real and imaginary single word product
❒DSP Complex Half-word Multiply-Accumulate instruction:
signed complex half-word multiply-add ⇒real and imaginary single word product sum
❒DSP Add and Subtract instructions:
signed half-word add and subtract with and without fixed-point adjustment ⇒single
word sum and difference
❒Floating-point instructions are architecturally fully integrated, they are executed as
Software instructions by the present version. Floating-point Add, Subtract, Multiply,
Divide, Compare and Compare unordered for single and double-precision, and Convert
single ⇔double are provided.
1.1.13. Exceptions:
❒Pointer, Privilege, Frame and Range Error, Extended Overflow, Parity Error, Interrupt
and Trace mode exception
❒Watchdog function
❒Error-causing instructions can be identified by backtracking, thus allowing a very
detailed error analysis

Page 1-6 Architecture
1.1.14. Timer:
❒Two multi-functional timers
1.1.15. Bus Interface:
❒Separate address bus of 26 (E1-32XS) or 22 (E1-16XS) bits and data bus of up to 32 (E1-
32XS) or 16 bits (E1-16XS) provide a throughput of up to four or two bytes at each clock
cycle, respectively.
❒Data bus width of 32, 16 or 8 bits, individually selectable for each external memory
area.
❒8-bit, 16-bit, and 32-bit boot width selectable via two external pins.
❒Configurable I/O pins
❒Internal generation of all memory and I/O control signals
❒Wait pin function for I/O accesses to peripheral devices.
❒Wait pin function for memory accesses to address space MEM2.
❒On-chip DRAM controller supporting Fast-Page-Mode DRAMs, EDO DRAMs, and
synchronous DRAMs (SDRAM).
❒Up to seven vectored interrupts.
❒Control function for CLKOUT pin.
1.1.16. Power Management:
❒Lower power supply current in power-down mode.
❒Clock-Off function to further reduce power dissipation (Sleep Mode).
❒PLL settings controllable by software, providing a “gear-up” or “gear-down” within one
clock cycle.

E1-32XS User’s Manual Page 1-7
1.2. Block Diagram
Internal
Timer
I/O and
Interrupt
Control
Store Data
Pipeline
Watchdog
PLL
Power
Reset
Control
16 KByte
SRAM
Data Bus Parity
Address
Bus
Control
Bus
Bus Interface
Control
Bus Pipeline
Control
Instruction
Prefetch Control
Instruction
Decode
X Decode
Y Decode
Instruction
Cache
Control
Load
Decode
7
26
(22)
14
32
4
(2)
32
(16)
Register Set
64 Local
26 Global
X Y PC
Instruction
Cache
Memory Address
Pipeline
X Y
DSP
Execution
Unit
ALU
Barrel Shifter
Z W A
X Y I Instruction
Execution
Control
Figure 1.1: Block Diagram

Page 1-8 Architecture
1.3. Global Register Set
The architecture provides 32 global registers of 32 bits each. These are:
G0 Program Counter PC
G1 Status Register SR
G2 Floating-Point Exception Register FER
G3..G15 General purpose registers
G16..G17 Reserved
G18 Stack Pointer SP
G19 Upper Stack Bound UB
G20 Bus Control Register BCR (see section 6. Bus Interface)
G21 Timer Prescaler Register TPR (see section 5. Timer)
G22 Timer Compare Register TCR (see section 5. Timer and CPU Clock
Modes)
G23 Timer Register TR (see section 5. Timer and CPU Clock Modes)
G24 Watchdog Compare Register WCR (see section 6. Bus Interface)
G25 Input Status Register ISR (see section 6. Bus Interface)
G26 Function Control Register FCR (see section 6. Bus Interface)
G27 Memory Control Register MCR (see section 6. Bus Interface)
G28..G31 Reserved
Registers G0..G15 can be addressed directly by the register code (0..15) of an instruction.
Registers G18..G27 can be addressed only by a MOV or MOVI instruction with the high
global flag H set to 1.

E1-32XS User’s Manual Page 1-9
G0
031
0
G1
G2
G3
G15
G16
G17
G18
G19
G20
G21
G22
G23
G24
G25
G26
G27
Program Counter PC
Status Register SR
Floating-Point Exception Register FER
Reserved
Reserved
General Purpose Registers G3..G15
Stack Pointer SP
Upper Stack Bound UB
Bus Control Register BCR
Timer Prescaler Register TPR
Timer Compare Register TCR
Timer Register TR
Watchdog Compare Register WCR
Input Status Register ISR
Function Control Register FCR
Memory Control Register MCR
G28..G31 Reserved
0
00
0
G28
G31
Figure 1.2: Global Register Set
1.3.1. Program Counter PC
G0 is the program counter PC. It is updated to the address of the next instruction through
instruction execution. Besides this implicit updating, the PC can also be addressed like a
regular source or destination register. When the PC is referenced as an operand, the value
supplied is the address of the first byte after the instruction which references it, except
when referenced by a delay instruction with a preceding delayed branch taken (see section
3.26. Delayed Branch Instructions).
Placing a result in the PC has the effect of a branch taken. Bit zero of the PC is always
zero, regardless of any value placed in the PC.

Page 1-10 Architecture
1.3.2. Status Register SR
G1 is the status register SR. Its content is updated by instruction execution. Besides this
implicit updating, the SR can also be addressed like a regular register. When addressed as
source or destination operand, all 32 bits are used as an operand. However, only bits 15..0
of a result can be placed in bits 15..0 of the SR, bits 31..16 of the result are discarded and
bits 31..16 of the SR remain unchanged. The full content of the SR is replaced only by the
Return Instruction. A result placed in the SR overrules any setting or clearing of the
condition flags as a result of an instruction.
Frame Pointer Frame Length
2829
FL S PT
Trace-Mode Flag
Trace Pending Flag
Supervisor State Flag
Instruction-Length Code
31 30 27 26 25 24 23 22 21 20 19 18 17 16
ILC
FP
Figure 1.3: Status Register SR (bits 31..16)
Floating-Point Rounding Mode
Floating-Point Trap Enable
Interrupt-Mode Flag
High Global Flag
Cache-Mode Flag
1213
FTE V N ZC
Carry Flag
Zero Flag
Negative Flag
Overflow Flag
1514 11109876543210
MH
FRM
L I
Reserved
Interrupt-Lock Flag
Figure 1.4: Status Register SR (bits 15..0)

E1-32XS User’s Manual Page 1-11
The status register SR contains the following status information:
CBit zero is the carry condition flag C. In general, when set it indicates that the
unsigned integer range has been exceeded. At add operations, it indicates a
carry out of bit 31 of the result. At subtract operations, it indicates a borrow
(inverse carry) into bit 31 of the result.
ZBit one is the zero condition flag Z. When set, it indicates that all 32 or 64
result bits are equal to zero regardless of any carry, borrow or overflow.
NBit two is the negative condition flag N. On compare instructions, it indicates
the arithmetic correct (true) sign of the result regardless of an overflow. On all
other instructions, it is derived from result bit 31, which is the true sign bit
when no overflow occurs. In the case of overflow, result bit 31 and N reflect
the inversion of the true sign.
VBit three is the overflow condition flag V. In general, when set it indicates a
signed overflow.
MBit four is the cache-mode flag M. Besides being set or cleared under program
control, it is also automatically cleared by a Frame instruction and by any
branch taken except a delayed branch. See section 1.9. Instruction Cache for
details.
HBit five is the high global flag H. When H is set, denotation of G0..G15 addres-
ses G16..G31 instead. Thus, the registers G18..G27 may be addressed by deno-
ting G2..G11 respectively.
The H flag is effective only in the first cycle of the next instruction after it was
set; then it is cleared automatically.
Only the MOV or MOVI instruction issued as the next instructions can be used
to copy the content of a local register or an immediate value to one of the high
global registers. The MOV instruction can also be used to copy the content of a
high global register (except the BCR, TPR, FCR and MCR register, which are
write-only) to a local register. With all other instructions, the result may be
invalid.
If one of the high global registers is addressed as the destination register in user
state (S = 0), the condition flags are undefined, the destination register remains
unchanged and a trap to Privilege Error occurs.
Reserved Bit six is reserved for future use. It must always be zero.
IBit seven is the interrupt-mode flag I. It is set automatically on interrupt entry
and reset to its old value by a Return instruction. The I flag is used by the
operating system; it must be never changed by any user program, regardless of
user or supervisor state.
FTE Bits 12..8 are the floating-point trap enable flags (see section 3.33.2. Floating-
Point Instructions).
FRM Bits 14..13 are the floating-point rounding modes (see section 3.33.2. Floating-
Point Instructions).

Page 1-12 Architecture
LBit 15 is the interrupt-lock flag L. When the L flag is one, all Interrupt, Parity
Error and Extended Overflow exceptions regardless of individual mode bits are
inhibited. The state of the L flag is effective immediately after any instruction
which changed it. The L flag is set to one by any exception.
The L flag can be cleared or kept set in any or on return to any privilege state
(user or supervisor). Changing the L flag from zero to one is privileged to
supervisor or return from supervisor to supervisor state. A trap to Privilege
Error occurs if the L flag is set under program control from zero to one in user
or on return to user state.
The following status information cannot be changed by addressing the SR:
TBit 16 is the trace-mode flag T. When both the T flag and the trace pending
flag P are one, a trace exception occurs after every instruction except after a
Delayed Branch instruction. The T flag is cleared by any exception.
Note: The T flag can only be changed in the saved return SR and is then
effective after execution of a Return instruction.
PBit 17 is the trace pending flag P. It is automatically set to one by all in-
structions except by the Return instruction, which restores the P flag from bit
17 of the saved return SR.
Since for a Trace exception both the P and the T flag must be one, the P flag
determines whether a trace exception occurs (P = 1) or does not occur (P = 0)
immediately after a Return instruction which restored the T flag to one.
Note: The P flag can only be changed in the saved SR. No program except the
trace exception handler should affect the saved P flag. The trace exception
handler must clear the saved P flag to prevent a trace exception on return, in
order to avoid tracing the same instruction in an endless loop.
SBit 18 is the supervisor state flag S (see section 1.5. Privilege States). It is set
to one by any exception.
ILC Bits 20 and 19 represent the instruction-length code ILC. It is updated by
instruction execution. The ILC holds (in general) the length of the last in-
struction: ILC values of one, two or three represent an instruction length of
one, two or three half-words respectively. After a branch taken, the ILC is
invalid. The Return instruction clears the ILC.
Note: Since a Return instruction following an exception clears the ILC, a
program must not rely on the current value of the ILC.
FL Bits 24..21 represent the frame length FL. The FL holds the number of usable
local registers (maximum 16) assigned to the current stack frame.
FL = 0 is always interpreted as FL = 16.
FP Bits 31..25 represent the frame pointer FP. The least significant six bits of the
FP point to the beginning of the current stack frame in the local register set,
that is, they point to L0.
The FP contains bit 8..2 of the address at which the content of L0 would be
stored if pushed onto the memory part of the stack.