ICL 22 User manual
ICL
System
Ten
Model
22
Processor
Reference
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Technical Publication
7529
© International
Computers
limited
1977
First Edition
June
1977
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Preface
This publication describes the hardware and method
of
operation
of
the System Ten Model 22
processor.
Chapter I describes the components
of
the machine, and Chapter 2 describes the way that core
store
is
organised and used. The machine instructions are detailed in Chapter 3 and the
Input/Output controllers
are
described in Chapter 4. Appendix I provides a convenient reference
to the System Ten character set.
7529/0
iii
Contents
The
text
of
this publication is divided
into
chapters in
the
normal way, and each
chapter
is
subdivided
into
sections. A section's level
in
the hierarchy is indicated by its number. Therefore,
within Chapter n, first level section headings are numbered
n.l,
n.2
and
so
on;
second level
headings are
numbered
n.l.l,
n.l.2
...
n.2.l
and so
on;
third
level headings are
numbered
n.
1.1.1, n.1.1.2
...
n.l.2.1
and so on.
The
contents
list and index, and cross-references in
the
text,
all refer
to
section numbers.
Pages are numbered within chapters, in
the
form c-p, where c is
the
chapter
number
and
p·the
page
number
within
that
chapter. Figures and tables, where they appear, are also
numbered
within chapters, so
that
Figure n.2 is the second figure in Chapter
n,
and
Table n.2
is
the
second
table
in
that
chapter.
Section numbers, page numbers
and
figure and table numbers in appendices are preceded by
the
letter
A.
Preface
Architecture
of
the
Model
22 processor
Introduction
Components
Memory
description
Definitions
Memory
The
Arithmetic
and
Control
Unit
(ACU)
The File Access Channel (FAC)
The
Input/Output
Controllers
(IOCs)
How
the
ACU operates
The
Base
Adder
Service Request
Interrupt
Power failure
Program check
Address check
Load Request
Store organisation and
use
Common
Partition
memory
Memory
addressing
Indexing
Manipulating indexes
Indirect
addressing
Extended indexing
I
nformation
storage
Character set
Collating sequence
Alternative
characters in the set
Representation
of
negative numbers
7529/0
iii
Chapter 1
Chapter
1.1
1.2
1.2.1
1.2.1.1
1.2.1.2
1.2.2
1.2.3
1.2.4
1.3.1
1.3.2
1.3.3
1.3.4
1.3.5
1.3.6
1.3.7
2
2.1
2.2
2.3
2.3.1
2.3.1.1
2.3.2
2.3.3
2.4
2.4.1
2.4.2
2.4.3
2.4.4
v
Instructions
Format
of
the
instruction
Operation code field
Address mode
Indexing field
Indirect
addressing
indicator
Page
indicator
Address length specifier
The Address field
I
nstruction
descriptions
Add
Add
Address
Branch
Compare
Divide
Edit
Exchange
Form
Numeric
Move Address
Move Character
Move
Numeric
Multiply
Read
Write
The
Input/Output
Controllers
The
Multiterminal
Input/Output
Channel II
(MTIOC
II)
Polling
Service Request
Load Request
I
nputlOutput
The
Digital
Clock
The Multi-Device IOC II
Branch-on-service-request
Read
Write
Write
Control
The Synchronous Communications
Adaptor
Introduction
vi
Control
characters
OLE pairs
Terminator
control
characters
SCA I
nputlOutput
instructions
Write
Read
Write
Control
Read
Control
Programming conventions
Leading
SYNs
Chapter 3
3.1
3.1.1
3.1.2
3.1.3
3.1.4
3.1.5
3.1.6
3.1.7
3.2
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
3.2.6
3.2.7
3.2.8
3.2.9
3.2.10
3.2.11
3.2.12
3.2.13
3.2.15
Chapter 4
4.1
4.1.1
4.1.1.1
4.1.1.2
4.1.2
4.2
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.4
4.4.1
4.4.2
4.4.2.1
4.4.2.2
4.4.3
4.4.3.1
4.4.3.2
4.4.3.3
4.4.3.4
4.4.4
4.4.4.1
7529/0
Transmitting
messages
Responses
to
polling
and selecting
Answering calls
in
dial line configurations
Condition
codes
after
SCA operations
Condition
code 1
Condition
code 2
Condition
code 4
The Asynchronous
Communications
Adaptor
Physical description
Operational characteristics
Dial operations
Manual dialling
Automatic
dialling
Automatic
dial
options
Operations
in
ISF mode
Introduction
Timeout
periods
Manual dialling in ISF mode
Automatic
dialling in ISF mode
Transmission status character
Reverse (Back) channel
communication
Receiving data
from
ISF
Automatic
error
correction
Communicating
with
the
ACA
Initial
isation
ACA
instructions
The Asynchronous Terminal
Adaptor
General description
Physical description
Functional
description
Selection switches
Control
character
input
Operation
Break
Service Request
Load Request
Repeat
function
Programming
information
Introduction
Status indications
Communication
format
Read
Write
ATA
application design considerations
Load
Timeout
On-Iine/local
Write
delay
timer
Device start/stop codes
7529/0
4.4.4.2
4.4.4.3
4.4.4.4
4.4.5
4.4.5.1
4.4.5.2
4.4.5.3
4.5
4.5.1
4.5.1.1
4.5.2
4.5.2.1
4.5.2.2
4.5.2.3
4.5.3
4.5.3.1
4.5.3.2
4.5.3.3
4.5.3.4
4.5.3.5
4.5.3.6
4.5.3.7
4.5.3.8
4.5.3.9
4.5.3.10
4.5.3.11
4.6
4.6.1
4.6.2
4.6.3
4.6.3.1
4.6.3.2
4.6.4
4.6.4.1
4.6.4.2
4.6.4.3
4.6.4.4
4.6.5
4.6.5.1
4.6.5.2
4.6.5.3
4.6.5.4
4.6.5.5
4.6.6
4.6.6.1
4.6.6.2
4.6.6.3
4.6.6.4
4.6.6.5
vii
Special programming considerations Chapter 5
The System Ten character set Appendix1
Index
viii 7529/0
Architecture
of
the Model
22
processor
Chapter
1
1.1
Introduction
1.2
1.2.1
1.2.1.1
The System Ten
computer
is a multi-programming system capable
of
executing
up
to
20
independent
programs concurrently. This is achieved
without
the overhead
of
an executive
program: core store is divided
into
a shareable area
of
store called
Common
and
up
to
20
user
partitions. A hardware switching system allocates processing time
to
each
partition
in turn.
COMMON FAC
PARTlTlONO
PARTITION 1
PARTITION 2
To
s-iphofall
PARTITION 3
PARTITION
19
Figure 1.1 The main components
of
a System Ten computerand
how
they are
logically connected
The execution
of
instructions
and
all transfers
to
and
from core store are
performed
by
the
Arithmetic and Control
Unit
(ACU). Additional large volume storage
is
provided
by
magnetic
tape
and
disc units
through
the File Access Channel
(F
AC). Communication
between
the
ACU
and
other
peripheral devices is
by
means
of
Input/Output
Controllers
(laCs)
of
several types,
each
of
which is linked
to
a partition. A System
Ten
computer
therefore has one F
AC
and
one
to
20
laCs.
The
components
of
the
System Ten
computer
are described in the sections
that
follow, and
how
they are logically
connected
is
shown in Figure 1.1.
Components
Memory description
Definitions
Throughout
this publication, terms have
the
following definitions:
Term Definition
Bit One
of
the
two digits 0
or
I held
by
one element
of
core storage
7529/0
1-1
1.2.1.2
Architecture
of
the
Model
22
processor
Term
Location
Definition
The smallest addressable unit of core store consisting
of
six
bits and
holding one character
Character One symbol from the System Ten set (see Figure 2.2) represented by a
unique code
of
six bits
Field
K
Memory
One or more contiguous characters which together hold an item of
information
1000 locations
System Ten memory provides random access core storage for from 20K to 160K locations in
modules
of
20K. Each location
is
addressable and contains one six bit character. The highest
address that can be handled, and therefore the maximum size
of
Common or any partition, is 80K.
It
is
a convention that the address
of
a location in Common will be specified by
five
digits followed
by the letter
C;
for example 29480C.
At installation, the available memory is divided between Common memory and the desired number
of
partitions. Common can
be
allocated from
lK
to
80Klocations in modules
of
lK. Because
of
system requirements the minimum allocated
is
usually 10K.
A partition can be allocated from
lK
to
10K in modules
of
lK,
or from 10K
to
the maximum
of
80K in modules
of
10K.
The system
of
memory allocation
is
very flexible and a user must select the number
of
partitions
and how memory
is
divided between them and Common
that
will provide the most satisfactory
performance for his application. An example configuration might be a 60K machine with memory
divided into 19K Common, a
lK
partition with a digital clock and four application partitions
of
10K each.
1-2
30000
20000
19000
PARTITION
2 (SIZE
10K)
PARTITION
1 (SIZE
10K)
11
21
31
41
PARTITION
0 (SIZE 1
K)
INDEX
REGISTERS ERROR
INFORMATION
COMMON
AREA
(SIZE
19K)
PROTECTED
AREA
ASSOCIATED
WITH
PARTITION
NUMBER
~~~~~~~~~
..............
~~
............
Figure 1.2 Example allocation
of
memory
A ADDRESSES
BADDRESSES
PADDRESSES
7529/0
Architecture
of
the
Model
22
processor
1.2.2 The Arithmetic and Control
Unit
(ACU)
The Arithmetic and Control Unit (ACU) carries
out
three important functions
that
are fundamental
to the running
of
the machine:
To allocate processing time to each
IOC
and its associated partition in turn. Each IOC in
turn
is
selected'by the ACU and monopolises the unit for (nominally)
40
milliseconds. See
the Branch instruction, section 3.2.3
2 To
extract
each instruction and its associated data from core store; operate on
the
data and
store the results
3 To transfer data character by character between core store and the FAC or one
of
the IOCs
1.2.3 The File
Access
Channel (FAC)
The File Access Channel (FAC) provides an interface between the ACU and magnetic tape and
disc storage. Depending on the high-speed devices provided in the system, the F
AC
includes a
Magnetic Tape Controller (handling up
to
four tape drives) and/or a Disc Controller (handling up
to
16
logical disc devices). Unlike the IOCs, the F
AC
is
shared. The devices attached
to
the F
AC
are directly accessible
to
all partitions. Thus, several programs may share the same disc
or
magnetic tape files.
Data
is
transferred between core store and disc units in groups
of
100 characters, and between
core store and magnetic tape in groups
of
up
to
10,000 characters.
Note
that
(unlike the IOCs) the FAC retains control
of
the processor until a data transfer
is
complete. It
is
therefore possible for a lengthy tape transfer (for example reconstituting a disc
from a tape security copy)
to
occupy the processor for a considerable time.
1.2.4 The I
nput/Output
Controllers (I
DCs)
The
Input/Output
Controllers (IOCs) provide communication between the
ACU
and
the
various
peripheral devices.
It
is
the IOCs
that
perform the conversion between the ASCII seven-bit
character
pattern
and the System Ten internal six-bit pattern (see section 2.4.1). Each IOC can
address any location in its own partition or above 299 Common.
The following IOCs are available:
IOC
type
Multi-terminal
laC
(MTIOC II)
Multi Device
laC
(MDIOC II)
Synchronous Communications
Adaptor
(SeA)
Asynchronous Communications
Adaptor (ACA)
Asynchronous Terminal
Adaptor (ATA)
Digital clock
1.3
How
the
ACU
operates
User device
Workstation(typebar or Visual Display Unit (VDU), Line
Printer
Point
of
sale
(PaS)
terminal, Job Information terminal, Data
Collection terminal
Remote computer, visual display unit (VDU) or
other
synchronous device
Remote asynchronous devices including computers
Devices from Other Equipment Manufacturers (OEM) using
asynchronous communications methods
Provides time
of
day information for user
The
ACU
performs all major functions by means
of
hardware logic controlled
by
hardware
function codes which are similar
to,
but
at a lower level than, instruction function codes. These
hardware codes control the manipulation
of
information and its transfer between components
of
the processor and
to
and from peripherals.
Even though the general course
of
action
of
the ACU
is
set by the instruction function code, the
ACU must step through and branch between hardware functions many times to perform the
various checks and actions necessary
to
complete one instruction. The sequence
of
steps and
functions
is
different for each instruction, and during execution the sequence
is
constantly being
modified depending on certain conditions encountered, for example a data error or a busy or
inactive peripheral.
7529/0
1-3
Architecture
of
the
Model
22
processor
Because
of
the very high speed
at
which the
ACU
operates compared with
an
10C, or with
peripherals, which
are
even slower, the
ACU
is
able
to
initiate some action in an 10C or peripheral
and then perhaps carry out a number
of
other functions while waiting for the first to be
completed.
In
this way, the ACU
is
able
to
direct and monitor activities
in
many parts
of
the
machine, and take the necessary action in order
to
achieve the required result with the greatest
efficiency.
Some
of
the activities to which the
ACU
reacts are:
The power supply to the machine
is
constantly monitored so
that
no information
is
lost in
the event
of
a power failure.
See
section
l.3.4
2 Data
is
transferred character by character between core store and the
ACU,
and between the
FAC
and 10Cs and the ACU, whenever the necessity
is
indicated by an Interrupt.
See
section
1.3.3
3 Although it
is
usually the
ACU
that
initiates a data exchange with
an
10C or a peripheral,
some peripherals can attract the attention
of
the
ACU
by a Service Request,
see
section
1.3.2
4 The validity
of
each instruction is checked before and during execution and any fault causes
a Program Check (see section 1.3.5) or an Address Check (see section 1.3.6)
1.3.1
The
Base
Adder
The
Base
Adder
is
a part
of
the
ACU
that
derives the actual address in core store, or absolute
address, from the address specified in an instruction.
Each location in a partition
is
addressed by the partition user relative
to
the beginning
of
that
partition.
In
order for the
ACU
to
arrive
at
the absolute address, the store allocated to Common
and
to
all
the partitions numbered lower than that partition must be added to the instruction
address. Addresses in Common do not use the
Base
Adder.
1.3.2 Service
Request
Service Request
is
a hardware function that allows a program
to
recognise when a peripheral such
as
a terminal has information to pass.
The program will contain a Branch on Service Request instruction which can transfer control to a
Read instruction.
A message
is
typed into and held by the terminal and when the Enter key
is
pressed, Service
Request
is
indicated to the 10C and thus
to
the
ACU.
When
the ACU next encounters the Branch
on Service Request instruction in the program, the Service Request
is
recognised, the
ACU
passes
control to the Read instruction and the transfer
is
handled by Interrupt.
1.3.3 Interru
pt
Interrupt
is
a hardware function that enables characters
to
be
transferred between the
ACU
and
the F
AC
and the
IOCs.
When
a Read or Write instruction
is
executed and therefore a character transfer
is
required, the
10C and the
ACU
first establish the housekeeping
of
the transfer (such
as
how many characters
are
to
be
transferred, from where and
to
where) and then the transfer
is
effected character by
character by the
ACU
during slack periods
of
its internal activity.
The partition requesting the transfer
is
not allocated processing time again until
all
the required
characters have been transferred. Having initiated the transfer
of
one character for an 10C
requesting such service, the
ACU
then initiates the transfer
of
one character for every other 10C
requesting interrupt transfer before continuing with processing.
Because character transfers to or
"from
disc or magnetic tape are faster than with other peripherals,
the
ACU
is
able to
give
more priority
to
such transfers. The interrupt function therefore takes
place at one
of
three levels depending on the peripheral concerned.
1
DISC
The
ACU
is
dedicated to the
disc
until the transfer
is
complete
2 MAGNETIC TAPE During one interrupt cycle, interrupt after interrupt
is
generated until
the transfer
is
complete
3 OTHER During one interrupt cycle, one interrupt
is
satisfied and one character transferred
for each requesting 10C
1-4
7529/0
Architecture of
the
Model
22
processor
1.3.4 Power failure
The line voltage
of
the ACU is constantly monitored. When a power failure
is
sensed, execution
of
the current program
is
suspended and status information
is
saved. When the power returns to
normal, processing continues with the same partition, without operator intervention. The contents
of
core store remain unaltered
by
a power failure.
1.3.5
Program check
Certain serious errors during the execution
of
a program can be detected
if
they occur, and will
cause aprogram check. That is, execution
of
the program in that partition ceases, the user
is
informed
by,
for example, the LOAD and LOCAL lights being illuminated on his VDU, and
useful information about the program check
is
stored
to
assist in later determining the cause.
Processing continues with the next partition.
When a program check occurs, the system stores in the error register (locations
41
to
44)
of
the
relevant partition either the address plus ten
of
the instruction that caused the error, or, in the
case
of
an I/O instruction, the address plus one
of
the instruction.
The errors which will cause a program check are:
An
attempt
being made
to
address a location outside the limit
of
Common or the partition
2 An
attempt
being made to write
to
the protected area
of
Common (the
A,
Band
P registers)
3 Bit 5
of
the fifth character fetched
as
part
of
an instruction
is
zero
4 The Binary-Coded Decimal value
of
the address bits
of
a character fetched
as
part .of
an
instruction, an index register, or a disc address exceeds nine .
1.3.6. Address check
An
Address check occurs because the address specified in an instruction lies outside the allotted
partition or Common size.
As
well
as
occurring at the initial specification
of
the instruction, an
address check can occur
as
the instruction
is
executed. For example,
if
the instruction is required
to
access a number
of
consecutive characters, although the address
of
the first may be in range,
as
the instruction steps through, the address generated to access a later character may be
out
of
range.
The instruction specifies
to
the ACU how many characters are to be accessed, and
if
for any
reason too few can be accessed, an address check will occur.
1.3.7 Load Request
Load Request
is
the procedure
that
the ACU follows in order
to
begin processing in a partition
either initially or after a program failure.
When a Load Request
is
encountered, a hardware Read Control instruction accepts ten characters
from device zero, and executes the instruction they form. Typically, this instruction would be
ten zeros which causes a Read (op code
0000)
of
sector zero from disc drive zero into location
zero partition. Execution then continues with the
next
instruction
(at
location ten) which now
contains some software instruction, and processing begins.
The same effect would be achieved
if
no instruction were entered:
if
less than ten characters are
entered on device zero, remaining characters are zero-filled.
A Load Request occurs
if
the ACU encounters a Program Check or Address Check,
or
if
a program
failure
is
forced by, for example, the Load and Local keys at a terminal being pressed.
7529/0
1-5
Store organisation and use Chapter 2
System Ten core store provides direct access storage for a maximum
of
160,000
(I60K)
locations.
Store size can be installed in modules
of
20K from the minimum
of
20K. Each location
is
addressable and contains one six-bit character.
When the machine
is
installed,
the
available store
is
divided among Common and the desired
number
of
partitions.
2.1 Common
Common may be a maximum
of
80K locations in size and may be incremented in steps
of
1K
from the minimum
of
lK.
Memory,
both
Common and partition,
is
further subdivided
into
pages
of
10K each.
If
the allocated memory
is
not
a whole number
of
pages, the
part
page must have the
highest page number. Locations in Common are addressed from 0000. Locations in Common may
be used by any partition, except locations 0
to
299 which can be read only.
Locations 0
to
299 are divided
into
three areas used
to
store system information when partition
switching occurs. Core storage is permanent, and
it
is
this feature and
the
storage
of
this system
information that, after a power failure allows processing
to
continue
without
further interruption.
The three areas are designated the P, B and A registers, and each
is
further subdivided
to
hold the
information for each partition. The registers are allocated
as
follows:
Name
P register
B register
A register
'"'I '1 Partition memory
Location
000
to
099
100
to
199
200
to
299
Use
To store the
next
program address
to
be accessed
when the partition
is
next
serviced
To store the
count
of
characters still
to
be
transferred during
interrupts
To store information
about
the F
AC
peripherals
available
to
the partition, and
the
data being used
by the
current
instruction
Partition memory may be a maximum
of
80K
locations in size and may be incremented in steps
of
lK
from the minimum
of
zero,
to
10K and then in steps
of
10K
to
80K. Memory,
both
Common and partition
is
further subdivided logically
into
pages
of
10K each.
If
the allocated
memory
is
not
a whole number
of
pages, the part page must have the highest page number.
Locations in a partition are addressed from 0000 (see section 1.3.1), and may only be accessed
by
a program in
that
partition, or
by
a program residing in Common but activated by a program in
the currently executing partition.
Certain locations near the beginning
of
each partition have special uses, and are allocated
as
follows:
Locations
0011 -
0014
0021 -
0024
0031 -
0034
0041 -
0044
Use
Index register one
Index register
two
Index register three
Error register
Each index register
is
numbered respectively by the tens digit
of
its address and can be used by the
program for indexing, see section 2.3.1. The error register
is
used by
the
system
to
store the value
of
the P register
if
an error occurs. Location
40
holds a character
that
represents the size
of
the
partition, and therefore does
not
change. The registers are
not
protected in any way, and can be
used in the same way
as
any
other
partition locations.
7529/0
2-1
Store organisation and use
2.3 Store
addressing
There
is
no difference between characters stored
as
data or instructions except in the way in which
each
is
interpreted. A data character
is
meaningful to the user and
an
instruction character
is
part
of
a ten-character instruction that
is
meaningful to the
ACU.
However, an instruction can be moved
or overwritten in exactly the same way
as
data and
it
is this feature that allows a program to
modify itself.
A
address
I0
\1
12
1314151617
181911~
11
1;2113\14115116117118119,1
~~
7 ,
Baddress
Paddress
FAC
protection
character
A5
A4
AO
00255
00257
00259
00256
00258
Figure 2.1 How systems information for partition 11
is
held
in
the
A,
Band
P
registers
in
Common
Before the
ACU
can execute an instruction or operate on data, the address
in
store
of
the
instruction and/or
of
the data must be specified.
All
store addressing
is
by character position, the
six bits
of
the character being addressed simultaneously and being considered
as
one store location.
A data field or an instruction
is
addressed by the position
of
its leftmost character and can
be
located anywhere
in
the store available to a partition user, that is, in partition or Common.
An
instruction (simply a ten-character field) must be located at
an
address divisible-by-ten.
Although at its lowest level the hardware can address the
fulll60K
store available to the Model
22 processor, there
is
no need for a partition user
to
be able to address any location in store,
merely any location within the store available
to
him: 80K Common and 80K partition at the
most. Common and each partition
is
further logically subdivided into pages
of
10K. Addresses
in
Common and each partition begin at 00000. It
is
convention that the address
of
a location in
Common will be specified by
five
digits followed by the letter
C;
for example 29480C.
Thus any address available to a partition user (from 00000 to 79999 in Common or partition) can
be
indicated by:
One bit which specifies that the address
is
in
Common or partition
2 Three page identification bits specify the relevant page (0
to
7)
3 The four numeric characters
of
the address specify the location (0000 to 9999, see below)
An
address may be further modified (so long
as
it still
falls
within the store available to a partition
user) by adding to the address the contents
of
another location in store. This
is
called indexing
and
is
discussed fully in section 2.3.1.
2-2
7529/0
Store organisation and
use
In an instruction, an address is held in the four numeric bits
of
four characters.
If
these bits were
interpreted in the usual (binary) way, this bit arrangement could only hold an address
up
to
60
(four numeric characters each holding up
to
the value 15). However, the address
is
held
as
four
binary-coded decimal (BCD) digits, each capable
of
holding the digits 0
to
9,
enabling addresses
up to 10,000 (0
to
9999)
to
be accessed.
2.3.1
Indexing
2.3.1.1
Indexing
is
a convenient programming aid
by
which an address on which an instruction operates
can be modified
at
execution time. A typical application for indexing
is
table access.
When the ACU finds
that
indexinghas been specified for an address, the contents
of
the relevant
index register added to the address specified by the instruction to form and effective address. The
effective address
is
then
used in the operation.
Each partition has three four-character registers (fields) held in locations
11
to
14,
21
to
24 and
31
to
34
named respectively Index Register one, two and three.
Indexing
is
specified in an instruction (see section 3.1)
by
the Indexing specifier (see section 3.1.3)
for the A and/or B address being non-zero.
If
indexing has been specified, the numeric bits
(interpreted
as
Binary-Coded Decimal (BCD))
of
the relevant index register are added
to
the
address held in the instruction to form the effective address.
An
example
of
the use
of
indexing
is
as
follows: the A address in an instruction contains the
address 2000 and
is
indexed
by
index register two, which contains 0050. When the instruction
is
executed, the effective address
of
the A operand
is
2050.
Manipulating indexes
The index registers are located in partition memory and their contents are therefore the
responsibility
of
the user. The index registers may be used in two ways and
it
is
important to
differentiate between them:
1 The index may modify the address
of
a field
to
be operated on
2 The index may be the operand in any instruction (except Branch) and may therefore be
operated on itself. It
is
in
this way
that
its contents may be changed
2.3.2
Indirect
addressing
Indirect addressing
is
a facility by which the address in
an
instruction does
not
point directly
to
the field
to
be operated on,
but
points
to
a field to be used
as
the address
of
the field
to
be
operated on.
Indirect addressing
may
be specified for the A address and/or the B address
of
an instruction.
An
indirect address may refer
to
a location in partition or Common. That location
is
considered
to
be the first
of
a four-character address which may also refer
to
a location in partition
or
Common.
For the purposes
of
indirect indexing, only some bits
of
the four characters are significant: the
numeric bits
(1
to
4)
and the page bits (bit 5)
of
the first three characters, and the numeric bits
and the address mode
bit
(bit 7)
of
the fourth character.
If
both
indexing and indirect addressing are specified for an address, the indirect address
is
calculated first and
then
the contents
of
the index register are added.
2.3.3
Extended
indexing
Extended indexing
is
a facility
that
permits, with indexing, an effective address greater than the
page specified by the instruction address. That is, the page bits
of
the instruction and the index
register are included in the calculation
of
the effective address.
Extended indexing
is
specified by
bit
5
of
the
tenth
character
of
an instruction being set
to
O.
2.4 Information storage
The smallest addressable unit
of
information in the System Ten computer
is
the character, and
each character
is
represented
by
a pattern
of
six bits. Information
is
therefore stored and
manipulated character
by
character. A number
of
contiguous characters
is
called a field and is
addressed by the address
of
its leftmost character. Thus, a three-character field occupying
locations 0641, 0642 and 0643 is addressed
by
0641. Information in a field may be interpreted
as
data or an instruction
7529/0
2-3
Store
organisation
and
use
An instruction consists
of
a field
of
ten
characters,
but,
an
important
distinction, it
is
interpreted
bit
by
bit
without
regard
to
character. Each instruction
must
begin at an address divisible
by
ten.
Instructions are described in Chapter 3.
A data field
may
be from 1
to
100 characters and may
contain
one
of
three types
of
data:
1 Numeric: any
of
the numbers 0
to
9
2 Alphabetic: any
of
the letters A
to
Z
3 Alphanumeric: any
of
the characters from the System
Ten
set
2.4.1 Character set
The bit patterns which represent the characters conform
to
the
requirements
of
the American
National Standards Institute (ANSI) and
the
System
Ten
computer
character set
is
therefore a
subset
of
the American Standard Code for Information Interchange (ASCII).
Column o 2 3 4 5 6 7
~
NUMERIC\
0 0 0 0 1 1 1 1 b7
BITS 0 0 1 1 0 0 1 1 b6
ZONE
0 1 0 1 0 BITS
Row b4 b3
b2
b1
1 0 1 b5
0 0 0 0 0
NUL
DLE
space
0
Ii
p • P
1 0 0 0 I
SOH
DCI
I 1 A Q a q
0 0 1 0
STX
DC2 " 2 B R b r
2
3 0 0 1 1
ETX
DC3
• 3 C S C 5
4 0
l'
0 0
EOT
DC4 $ 4 D T d t
5 0 1 0 1
ENQ
NAK
% 5 E U e u
6 0 1 1 0
ACK
SYN
" 6 F V f y
7 0 1 1 I
BEL
ETB
, 7 G W g w
8 I 0 0 0
8S
CAN
( 8 H X h x
9 1 0 0 1
HT
EM
) 9 I Y i Y
10
1 0 1 0 LF SUB • : J Z j Z
11
1 0 1 1
VT
ESC
+ ; K [ k {
12
1 1 0 0
FF
FS
< L \ . 1 I
• I
13 1 1 0 1
CR
OS -= M ) m }
14
1 1 1 0
SO
RS · > N " n -
15 1 1 1 1
81
US I ? 0 0
DEL
Figure
2.2
The
ASCII
character set with the System
Ten
character set outlined boldly
By
convention the seven bits
of
an ASCII character are numbered from the right from
bl
to
b7.
Figure 2.2 shows the ASCII character set and bit patterns,
with
the System Ten character set
outlined boldly.
The full ASCII character set requires seven bits to represent all 128 characters. The System Ten
set has only
64
characters which
is
represented by six bits. The four least significant bits are called
the numeric bits and the two most significant bits are called
the
zone bits. The System
Ten
bit
pattern for a character may therefore be derived
by
omitting
bit
6 from the ASCII bit
pattern
for
the character. For example:
Character
D
2-4
ASCII
7654321
0101100
1000100
System
Ten
754321
001100
100100
bit
number
7529/0
Store
organisation
and
use
It is a convention
that
the bits
of
a System Ten character are numbered 1, 2, 3, 4, 5 and 7.
It
is
often required
to
convert a System Ten character back
to
its ASCII representation; during
output, for example. This can be achieved by inserting a bit 6 into the System Ten bit pattern
that
is
the inverse
of
bit 7. For example:
Character
System
Ten
ASCII
754321 7654321 bit number
C~1100
0101100
D
C~0100
1000100
A different conversion may take place when the special instruction Write Control
is
executed, or
during FAC I/O operations. Write control mode
is
described in section 3.2.15.2, and the control
characters are described
in
section 4.1.2.
2.4.2 Collating sequence
The collating sequence
of
the System Ten character set determines the relative values
of
the
characters for the purposes
of
making comparisons and sorting.
In
the System Ten character set,
the space character
I:::.
has the lowest value and the underline character _ has the highest value.
Thus, the digits are lower than the letters, the letter B has a greater value than the letter A and ?
has a greater value than /.
The collating sequence
is
as
follows:
Lowest Highest
I:::.!"#$%&'O*+,-./ 0 to
9:;<=>
.?@A
to
Z[\]
,,_
2.4.3 Alternative characters in the set
The following alternatives
to
the standard characters are permitted
to
allow for national
variations:
Standard
#
@
Alternative
£
± or 0
Aor
A or
AE
AorU
Oar
%0
2.4.4 Representation
of
negative numbers
If
a numeric field has a sign, the sign
is
stored in bit 7
of
the rightmost (least significant) digit.
If
bit 7
is
one, the field
is
negative;
if
bit 7
is
zero, the field
is
positive. Notice that, from Figure 2.2,
this causes a negative digit
to
have a bit configuration identical to an alphabetic character in the
range
Pta
Y.
The System Ten instruction set recognises the value
of
numbers
that
follow this
convention and operates algebraically on signed numeric data. Thus, adding a minus orte to
an
eight yields a result
of
seven.
7529/0
2-5
Instructions Chapter 3
3.1
Format
of
the instruction
Each System Ten instruction
is
ten characters in length and must begin so
that
its leftmost
character
is
situated in a location whose address is evenly divisible
by
ten.
The first few characters
of
an instruction as they appear in memory have the following format:
Character
Bit
use
Bit
o
F3 IDA LA LA LA LA
7 5 4 3 2
2
F2
PAl
A A A A
Fl
PA2 A A A A
7 5 4 3 2 1 7 5 4 3 2 1
but since the ten characters
of
an instruction are interpreted bit by bit without regard
to
character, a more useful representation
is
achieved by giving a vertical orientation
to
the six bits
of
each character:
r-
Zone
bits
4
3
Numeric bits
2
0
F2
PAl
2
F1
I
: PA2
I
I
I
I I
3
FO
PA4
I I I
Characters
Io
4 5
_____
L
_____
~
____
~
_____
"
I I I
I I
I I
I I
I I I
-
LA-
-----~----
~
----1-----
--LB"
I I I
I I
I I
I I I
-----~----~-----~-----
I I I
I I I
I
I
I
6 7
I
I
I
8
I I I
9
[;]
[J
----~-----~-----~-----
.
I I
I
I
I I
I I
----~-----B·----+-----
I I I
I I I
I I I
I I I
I I I
----,-----'-----T----- "
I I I
I I
I I
I
Each
of
the bit fields shown in the above illustration
is
used
by
the
ACU
in interpreting and
executing instructions.
Field Size
in
Interpretation and use
bits
F 4 Operation code of the instruction
AC
A address common/partition indicator
IA
2 A address indexing field
IB
2 B address indexing field
BC
B address common/partition indicator
IDA
Indirect addressing indicator for A address
PA
3
Page
indicator for A address
Reserved, must be set
to
1
IDB
Indirect addressing indicator for B address
PB
3
Page
indicator for B address
E Extended indexing bit
LA
4 Length specifier for A address
A
16
A address within page
LB
4 Length specifier for B address
B
16
B address within page
The above fields are explained in the sections
that
follow.
7529/0
3-1
Instructions
3.1.1 Operation
code
field
3.1.2
The operation code
is
stored in bit 7
of
the first four characters
of
the instruction. The code
is
interpreted in biriary fonn and indicates which
of
the 16 (0
to
15) available instructions the
ACU
is
to
execute.
The instructions and their binary representations are
as
follows:
Binary code Instruction
0000 Read
0001 Write
0010 Add Address
0011
Move
Address
0100 Add
0101 Divide
0110 Multiply
0111 Subtract
1000
Move
Character
1001
Move
Numeric
1010 Reserved
1011 Branch
1100 Edit
1101 Form Numeric
1110 Compare
1111 Exchange
Address
mode
The address mode bits (one each for the A address and the B address) specify,
if
set to 1, that the
appropriate address
is
in Common or,
if
set to 0, that it
is
in partition memory.
3.1.3 I
ndexing
field
Indexing
is
explained
in
section 2.3.1 and 2.3.3.
The indexing field
is
interpreted
as
follows:
Bit
content
00
01
10
11
Meaning
No
indexing
Indexing using index register one
Indexing using index register two
Indexing using index register three
3.l.4
Indirect
addressing
indicator
Indirect addressing
is
explained in section 2.3.1.1.
If
the indirect addressing indicator bit
is
set to
one, the
ACU
accesses four characters from store starting at the relevant address specified in the
instruction and uses those characters to form the effective address.
3.l.5
Page
indicator
The three page indicator bits
of
an address extend the addressable memory by specifying in which
of
the eight (0 to 7) pages the address
is
located. A page contains 10K characters and
is
therefore
written as the most significant characters
of
a store location. For example, location 5048 in
page
2
of
Common
is
usually written 25048C.
3-2
7529/0
I
nstruct
ions
The page indicator bits
of
an address are
not
held in
the
conventional binary form, in
that
they
are written from left
to
right (least significant
to
the
left)
and
then complemented.
For
example,
to
decode a page number held as
001
:
Complement (invert) its binary representation, giving
110
2 Decode the complement from left
to
right:
Decimal
bit
value 1 2 4
Complement 1 1 0
giving 1 plus 2 plus 0 equals 3
So the page number specified
is
3.
3.1.6 Address length specifier
The
lengths
of
the operands
on
which an instruction will act are held in
the
instruction, one for
the
A address, one for
the
B address. However, certain instructions use
the
length specifiers
differently since the instructions
may
have one
of
two
formats:
the
one-length format
or
the
two-length format.
In
both
formats
the
length specifiers hold the operand length in the same way; it
is
in
the
way
the
instruction interprets this value
that
they
differ.
The length specifier holds
the
number
of
characters
to
be operated
upon
by
the instruction
as
a
binary coded decimal (BCD) value,
that
is, a value from 0
to
9 (where 0 represents
ten)
held in
binary. The four bits available can,
of
course, hold
up
to
the
value 16
(0
to
15)
but
values over 9
are illegal.
It
is
therefore
not
possible
to
specify a length
of
o.
The two-length format
is
typical
of
arithmetic instructions, and each address length specifier gives
the
number
of
characters addressed. For example, a three-digit operand A is
to
be added
to
a
four-digit operand
B.
The A length specifier will hold 3 and the B iellgln speciiier will
hold
4.
Notice
that
an operand
of
ten characters
is
the longest
that
can be specified in a two-length
format
instruction.
The one-length format
is
typical
of
instructions used
to
manipulate alphanumeric data, and
can
specify fields longer
than
ten
characters.
In
a one-length format instruction,
the
address length
specifiers are copsidered
as
a two-digit value. Thus
if
the
A length contains 5 and
the
B length
contains 6, the instruction manipulates
56
characters
of
data.
If
both
length specifiers are zero,
the instruction manipulates 100 characters
of
data.
Certain instructions use
the
length specifiers for
other
purposes. See the relevant instruction for
further details.
3.1.7
The
address field
Each instruction contains two address fields, A and
B.
In
most
instructions
they
are used
to
specify
the
location
of
the leftmost character
of
the
operands
to
be
used
by
the
instruction. Each address
is a four-digit binary coded decimal number from 0000
to
9999.
If
the
numeric bits
of
any
character in the address indicate decimal numbers greater
than
9,
the
ACU will cause Program
Check.
The address fields may
be
modified
by
other
fields in
the
instruction
to
indicate whether an
address
is
in Common or partition, in which page it lies,
and
whether
or
not
indexing is
to
be
applied.
Note
that
it
is
possible
to
specify
an
A address and a B address
that
point
to
the same field,
or
to
fields which overlap.
3.2 Instruction descriptions
This section describes
the
ACU instructions, in alphabetical order
by
instruction name.
The interpretation and naming
of
the
bit
fields
of
an instruction is given
in
section 3.1
and
these
descriptions should be read
in
conjunction with
that
section.
3.2.1
Add
The Add instruction adds the numeric bits
of
the field indicated
by
the
A address
to
the
numeric
bits
of
the field indicated
by
the
B address, according
to
the
rules
of
algebra. The result overwrites
the
contents
of
the B field. The A field remains unchanged so long as
the
fields
do
not
overlap.
7529/0
3-3
Table of contents
