Icom ID-1 User manual

SERVICE
MANUAL
DIGITAL TRANSCEIVER
S-14120IZ-C1
May. 2005

INTRODUCTION
REPAIR NOTES
This service manual describes the latest service information
for the ID-1 DIGITAL TRANSCEIVER at the time of
publication.
DANGER
NEVER connect the transceiver to an AC outlet or to a DC
power supply that uses more than 16 V. Such a connection
could cause a fire or electric hazard.
DO NOT expose the transceiver to rain, snow or any liquids.
DO NOT reverse the polarities of the power supply when
connecting the transceiver.
DO NOT apply an RF signal of more than 20 dBm (100 mW)
to the antenna connector. This could damage the trans-
ceiver's front end.
ORDERING PARTS
Be sure to include the following four points when ordering
replacement parts:
1. 10-digit order numbers
2. Component part number and name
3. Equipment model name and unit name
4. Quantity required
<SAMPLE ORDER>
2710000590 Fan MF40D-12H-001 ID-1 Chassis 2 pieces
8900010940 Cable OPC-1119 RC-24 Chassis 3 pieces
Addresses are provided on the inside back cover for your
convenience.
1. Make sure a problem is internal before disassembling
the transceiver.
2. DO NOT open the transceiver until the transceiver is
disconnected from its power source.
3. DO NOT force any of the variable components. Turn
them slowly and smoothly.
4. DO NOT short any circuits or electronic parts. An
insulated turning tool MUST be used for all adjustments.
5. DO NOT keep power ON for a long time when the
transceiver is defective.
6. DO NOT transmit power into a signal generator or a
sweep generator.
7. ALWAYS connect a 30 dB to 40 dB attenuator between
the transceiver and a deviation meter or spectrum
analyzer when using such test equipment.
8. READ the instructions of test equipment thoroughly
before connecting equipment to the transceiver.
To upgrade quality, all electrical or mechanical parts and
internal circuits are subject to change without notice or
obligation.
MODEL VERSION SYMBOL RC-24
ID-1
U.S.A. USA-2 Optional
USA-3 Supplied
Europe EUR-2 Optional
EUR-3 Supplied
General GEN-2 Optional
GEN-3 Supplied
Icom, Icom Inc. and logo are registered trademarks of Icom Incorporated (Japan) in the United States, the United
Kingdom, Germany, France, Spain, Russia and/or other countries.

TABLE OF CONTENTS
SECTION 1 SPECIFICATIONS
SECTION 2 INSIDE VIEWS
2-1 ID-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
SECTION 3 DISASSEMBLY INSTRUCTIONS
3-1 ID-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3-2 RC-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
SECTION 4 CIRCUIT DESCRIPITON
4-1 RECEIVER CIRCUITS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4-2 TRNSMITTER CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
4-3 PLL CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
4-4 POWER SUPPLY CIRCUITS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
4-5 PORT ALLOCATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
SECTION 5 ADJUSTMENT PROCEDURES
5-1 PREPARATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5-2 PLL AND CODEC ADJUSTMENT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
5-3 TRANSMITTER ADJUSTMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
5-4 RECEIVER ADJUSTMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
SECTION 6 PARTS LIST
SECTION 7 SEMI-CONDUCTOR INFORMATION
SECTION 8 MECHANICAL PARTS AND DISASSEMBLY
8-1 ID-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
8-2 RC-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
SECTION 9 BOARD LAYOUTS
9-1 MAIN UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
9-2 LOGIC-1 UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
9-3 RC-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5
SECTION 10 BLOCK DIAGRAM
10-1 MAIN UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
10-2 LOGIC-1 UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
10-3 RC-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
SECTION 11 VOLTAGE DIAGRAM
11-1 MAIN UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
11-2 LOGIC-1 UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4
11-3 RC-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6

■GENERAL
• Frequency coverage : 1240.000–1300.000 MHz
• Type of emission : FM, GMSK (Digital)
• Transmission speed (theoretical value) : Data 128 kbps
Digital voice 4.8 kbps
• Codec : AMBE (2.4 kbps)
• Number of memory channel : 105 (incl. 2 scan edges and 3 calls)
• Tuning steps : 5, 6.25, 10, 12.5, 20, 25, 50, 100 kHz
• Frequency stability : ±2.5 ppm (–10˚C to +60˚C)
• Operating temperature range : –10˚C to +60˚C (–22˚F to +140˚F)
• Antenna connector : Type-N (50 Ω)
• Power supply requirement : 13.8 V DC ±15% (Negative ground)
• Current drain (at 13.8 V DC) : Transmit Less than 7 A (at 10 W)
Receive Less than 1.5 A (AF max.)
• Dimensions (projections not included) :
Main unit 141(W)×40(H)×165.8(D) mm; 59⁄16(W)×19⁄16(H)×617⁄32(D) in
Remote controller (RC-24) 150(W)×50(H)×49.5(D) mm; 529⁄32(W)×131⁄32(H)×615⁄16(D) in
• Weight (Approx.) :
Main unit 1.2 kg; 2 lb 10 oz
Remote controller (RC-24) 220 g; 7.7 oz
■TRANSMITTER
• Output power (at 13.8 V DC) : 10/1 W
• Modulation : Variable reactance frequency modulation (FM)
Quadrature modulation (Digital)
• Maximum frequency deviation (FM) : ±5.0 kHz
• Spurious emissions : Less than –50 dB
• Microphone connector : 8-pin modular jack (600 Ω)
■RECEIVER
• Receive system : Triple conversion superheterodyne system (FM, DV)
Double conversion superheterodyne (DD)
• Intermediate frequencies : 1st IF: 243.95 MHz, 2nd IF: 31.05 kHz, 3rd IF: 450 kHz (FM, DV)
1st IF: 243.95 MHz, 2nd IF: 10.7 MHz (DD)
• Sensitivity : Less than 0.18 µV (–122 dBm) at 12 dB SINAD (FM)
Less than 0.35 µV (–116 dBm) at BER 1×10–2 (DV)
Less than 1.58 µV (–103 dBm) at BER 1×10–2 (DD)
• Selectivity (typical) : More than 12 kHz/6dB, Less than 30 kHz/60 dB (FM)
More than 6 kHz/6dB, Less than 18 kHz/50 dB (DV)
More than 140 kHz/6dB, Less than 520 kHz/40 dB (DD)
• Spurious and image rejection : More than 50 dB
• Audio output power (at 13.8 V DC) : 2.0 W at 10% distortion with an 8 Ωload
• Squelch sensitivity (at threshold) : Less than 0.18 µV (–122 dBm) (FM only)
• Ext. speaker connector : 2-conductor 3.5 (d) mm/(1⁄8")/8 Ω
All stated specifications are subject to change without notice or obligation.
S SECTION 1 SPECIFICATIONS
1 - 1

SECTION 2 INSIDE VIEWS
2 - 1
(IC271: MC3356)
(IC1160: RA18H1213G1)
(IC1250: TA75501F)
MSK receiver IC
[DD mode]
Power amplifier*
APC amplifier*
*: Located under side of this point
(FI193: CFWLA450KHFA)
3rd IF filter [DV mode]
(X400: CR662)
(IC1551: LA4425)
PLL reference
oscillator
(FI192: CFWLB450KEIY)
3rd IF filter
[FM mode]
AF power amplifier
1st VCO circuit
2nd VCO circuit
(Q1: NE34018)
RF amplifier
(IC191: TA33136)
Demodulator IC
[DV mode], [FM mode]
•MAIN UNIT
Top view
•LOGIC-1 UNIT
Top view
CPU
(IC50: µPD70F3102A)
+5V regulator
(IC500: TA7805)
AMBE CODEC IC
(IC2: AMBE2020)
Ethernet controller
(IC104: RTL8019)
Liner CODEC IC
(IC1: µPD9930)

SECTION 3 DISASSEMBLY INSTRUCTIONS
3 - 1
*
)
)
)
*
+
,
LOGIC-1 unit
+
/.
.
-
,
•REMOVING THE MAIN UNIT
1 Unsolder 5 points A, and remove the ANT plate B.
3-1 ID-1
•REMOVING THE LOGIC-1 UNIT
1 Unscrew 1 screw A, and remove the cover B.
2 Remove 2 main shield plates C.
3 Disconnect 2 cables D, and unsolder 1 point E.
4 Unscrew 4 screws F, and remove the earth spring G.
5 Take off the LOGIC-1 unit.
2 Unsolder 11 points C.
3 Unscrew 2 screws D, and remove the ANT connector E.
4 Take off the cable Ffrom the chassis.
5 Disconnect the cable G, and remove the TR-A clip H.
6 Unscrew 7 screws I, and take off the MAIN unit.
MAIN unit
1
+
.
-
/
0
1
,1
3-2 RC-24
•REMOVING THE FRONT UNIT
1 Unscrew 4 screws A, and remove the rear plate B.
2Unscrew 3 screws C, and remove the front panel D.
3 Disconnect the cable E, and remove the knob F.
4 Unscrew 5 screws G, and take off the FRONT unit.
D
E
G
C
F
C
FRONT unit
G
B
A
A
Continue to right above.

4 - 1
SECTION 4 CIRCUIT DESCRIPTION
4-1 RECEIVER CIRCUITS
4-1-1 ANTENNA SWITCHING CIRCUIT (MAIN UNIT)
The antenna switching circuit functions as a low-pass filter
while receiving and a resonator circuit while transmitting.
This circuit does not allow transmit signals to enter the
receiver circuits.
Received signals from the antenna connector (CHASSIS;
J1) are passed through the low-pass filter which contains
strip-line and C1198, and are then applied to the λ⁄4type
antenna switching circuit (D1160–D1162, L1162).
While receiving, no voltage is applied to D1160–D1162.
Thus, the receive line and ground are disconnected and
received signals are applied to the RF circuit.
4-1-2 RF CIRCUIT (MAIN UNIT)
The RF circuit amplifies signals within the range of frequen-
cy coverage and filters out-of-band signals.
The signals from the antenna switching circuit pass through
the high-pass filter (L1–L4, C2–C5) and then applied to the
RF amplifier (Q1). The amplified signals are passed through
the bandpass filter (FI1) and then applied to the another RF
amplifier (Q2). The amplified signals are passed through the
another bandpass filter (FI2) to suppress unwanted signals.
The filtered signal is applied to the 1st mixer circuit.
4-1-3 1ST MIXER AND 1ST IF CIRCUITS (MAIN UNIT)
The 1st mixer circuit converts the received signals into
fixed frequency of the 1st IF signal with the 1st LO signal.
By changing the 1st LO signal, only the desired frequency
passes through the bandpass filter at the next stage of the
1st mixer circuit.
The RF signals from the bandpass filter (FI2) are mixed
with the 1st LO signal, where come from the 1st VCO cir-
cuit, at the 1st mixer circuit (IC71) to produce a 243.95
MHz 1st IF signal. The 1st IF signal is passed through the
bandpass filter (FI71) to suppress unwanted signals and
pass only the desired signals.
The filtered signal is applied to the 2nd IF circuit.
4-1-4 2ND MIXER AND 2ND IF CIRCUITS
(MAIN UNIT)
The 2nd mixer circuit converts the 1st IF signal into the 2nd
IF signal with the 2nd LO signal.
• DV/FM MODE
The filtered 1st IF signal from the bandpass filter (FI71) is
mixed with the 2nd LO signal (275.00 MHz), where come
from 2nd VCO circuit, at the 2nd mixer circuit (Q131) to
produce the 2nd IF signal (31.05 MHz). The 2nd IF signal
is passed through the MCF (FI191) via the DV/FM switch
(D131). The filtered signal is applied to the IF amplifier
(Q191) and then applied to the 3rd mixer circuit in the
demodulator IC (IC191).
• DD MODE
The filtered 1st IF signal from the bandpass filter (FI71) is
mixed with the 2nd LO signal (233.25 MHz), where come
from the 2nd VCO circuit, at the 2nd mixer circuit (Q131)
to produce the 2nd IF signal (10.7 MHz). The 2nd IF signal
is passed through the bandpass filter (FI272) to remove
unwanted heterodyned frequencies via the DD switch
(D273). The filtered signal is amplified at the IF amplifier
(Q270) and then passed through the another bandpass
filter (FI273). The filtered signal is applied to the another IF
amplifier (Q271) and then applied to the MSK receiver IC
(IC271).
FI2
FI1
Q1 Q2
1240–1300 MHz
1st mixer
IC71
1st LO:
3rd LO: 30.6 MHz
AF amplifier
circuit
LOGIC-1 unit
1056.05–1016.05 MHz
2nd IF: 31.05 MHz
2nd IF: 10.7 MHz
Fl71
BPFAMP
AMP
1st IF:
243.95 MHz
2nd mixer
Q131
2nd LO:
DV, FM: 275.00 MHz
DD: 233.25 MHz
HPF BPF
BPF
FI272
FI273
Q271 Q270
AMP
AMP BPF
BPF
FI191
D131
D273 DD mode
DV, FM mode
IC191
IC271
Q191
AMP BPF
Demodulator
IC
MSK
receiver
• RF AND IF CIRCUITS

4 - 2
4-1-5 DEMODULATOR CIRCUITS (MAIN UNIT)
• DV MODE
The demodulator IC (IC191) contains the 3rd mixer, limiter
amplifier, quadrature detector, active filter and noise ampli-
fier, etc.
The amplified signal from the IF amplifier (Q191) is applied
to the 3rd mixer section of the demodulator IC (IC191, pin
16) and is then mixed with the 3rd LO signal to be converted
into the 450 kHz 3rd IF signal. The 3rd IF signal from the
3rd mixer section (IC191, pin 3) passes through the ceramic
filter (FI193) via the mode switches (D192, D193) to remove
unwanted heterodyned frequencies. The filtered signal is
amplified at the limiter amplifier section (IC191, pin 5) and
then applied to the quadrature detector section (IC191, pins
10, 11) to demodulate the digital audio signals.
The 3rd LO signal (30.6 MHz) is produced at the 1st PLL
circuit by doubling it’s reference frequency (X400: 15.3 MHz)
at the doubler (Q550).
The digital audio signals from the demodulator IC (IC191, pin
9) are amplified at IC343 (pins 6, 7) and then applied to the
mode switch (IC342, pins 1, 7).
The switched signals from the mode switch (IC342, pin 1)
are applied to the LOGIC-1 unit via J1801 (pin 20).
• DD MODE
The MSK receiver IC (IC271) contains the limiter amplifier,
quadrature detector, etc.
The amplified signal from the IF amplifier (Q271) is applied
to the limiter amplifier section of the MSK receiver IC (IC271,
pin 7) and then applied to the quadrature detector section
(IC271, pin 11) to demodulate to the data signals.
The demodulated data signals from the MSK receiver IC
(IC271, pin 13) are amplified at IC343 (pins 1, 2) and then
applied to the mode switch (IC342, pins 1, 6).
The switched signals from the mode switch (IC342, pin 1)
are applied to the LOGIC-1 unit via J1801 (pin 20).
• FM MODE
The same demodulator IC that is used for DV mode opera-
tion is used for FM demodulation.
The amplified signal from the IF amplifier (Q191) is applied
to the 3rd mixer section of the demodulator IC (IC191, pin
16) and is then mixed with the 3rd LO signal to be converted
into the 450 kHz 3rd IF signal. The 3rd IF signal from the
3rd mixer section (IC191, pin 3) passes through the ceramic
filter (FI192) via the mode switches (D192, D193) to remove
unwanted heterodyned frequencies. The filtered signal is
amplified at the limiter amplifier section (IC191, pin 5) and
then applied to the quadrature detector section (IC191, pins
10, 11) to demodulate the AF signals.
The AF signals are output from the demodulator IC (IC191,
pin 9) and are then applied to the AF amplifier circuit.
4-1-6 DIGITAL CIRCUITS (LOGIC-1 UNIT)
The digital circuits convert the demodulated digital audio
signals into the analog audio signals and convert the
demodulated data signals format for PC communication via
the USB controller (for DV mode: low speed data operation)
or Ethernet controller (for DD mode).
The demodulated digital audio or data signals from the
mode switch (MAIN unit: IC342, pin 1) are applied to the
GMSK MODEM IC (IC150, pin 11). The applied signals are
synchronized with the clock signal, then the synchronized
FI192 (FM mode)
FI193 (DV mode)
3rd IF filters
450 kHz
Noise
detector
Q550
Quadrature
detector
Active
filter
Noise
amp.
Limiter
amp.
AF signals
5V
X191 Discriminator
Mixer
X400
15.3 MHz
30.6 MHz
2nd IF from the IF amplifier (Q191)
“NOIS” signal to the CPU (LOGIC-1 unit; IC50)
“A_RS” signal to the CPU (LOGIC-1 unit; IC50)
875
BPF
32
2
161411109
IC191
TA31136FN
RSSI
12
• 3RD IF AND DEMODULATOR CIRCUIT (DV/FM MODE)
From
demodulator
circuit (IC342)
To AF amplifier circuit
(MAIN unit; IC1411)
From
MIC amplifier circut
(MAIN unit; IC1671)
To modulator
circuit (IC831)
RECEIVED SIGNAL
IC1IC2
IC50
IC200
IC150
LINER
CODEC
AMBE
CODEC
CPU
GMSK
MODEM
BASEBAND
FILTER
FPGA
TRANSMIT SIGNAL
• DIGITAL CIRCUITS (LOGIC-1 UNIT)

4 - 3
signals are applied to the CPU (IC50) via the FPGA IC
(IC200).
• DV MODE (VOICE OPERATION)
The digital audio signals from the CPU (IC50) are applied
to the AMBE CODEC IC (IC2) for code expansion, and are
then applied to the linear CODEC IC (IC1). The digital audio
signals are converted into analog audio signals at the D/A
converter section and then output from pin 34 (IC1)
The analog audio signals are applied to the mode switch
(MAIN unit; IC1411, pins 1, 7) via the J101 (pin 30) as “DAF”
signal.
• DD MODE/DV MODE (LOW SPEED DATA OPERATION)
While operating in DD mode, the output signals from
the CPU (IC50) are applied to the connected PC via the
Ethernet controller (IC104).
While operating in DV mode (low speed data operation), the
output signals from the CPU (IC50) are applied to the con-
nected PC via the USB controller (IC550).
4-1-7 AF AMPLIFIER CIRCUIT (MAIN UNIT)
The AF amplifier circuit amplifies the demodulated AF sig-
nals to a level needed to drive a speaker.
• DV MODE
The AF signals from the LOGIC-1 unit are applied to the
mode switch (IC1411, pins 1, 7) and then amplified at the
buffer amplifier (IC1460, pins 1, 3). The buffer amplified
signals are applied to the filter switch (IC1462, pins 1, 6)
to select the appropriate AF filters for DV mode and then
passed through the low-pass (IC1461, pins 8, 10) and high-
pass (IC1461, pins 12, 14) filters. The filtered signals are
passed through the filter switch (IC1463, pins 1, 6) and are
then applied to the volume controller (IC1550, pins 2, 9).
• FM MODE
The AF signals from the demodulator IC (IC191, pin 9) are
applied to the mode switch (IC1411, pins 1, 6) and then
applied to the buffer amplifier (IC1460, pins, 1, 3). The buf-
fer amplified signals are applied to the filter switch (IC1462,
pins, 1, 7) to select the appropriate AF filters for FM mode
and then passed through the low-pass (IC1460, pins 6, 7,
8, 9) and high-pass (IC1460, pins 13, 14) filters. The filtered
signals are passed through the filter switch (IC1463, pins 1, 7)
and are then applied to the volume controller (IC1550, pins 2,
9).
The switched AF signals from the filter switch (IC1463, pin
1) are applied to the volume controller (IC1550, pins 2, 9).
The level adjusted AF signals (IC1550, pin 9) are applied to
the AF power amplifier (IC1551, pins 1, 4) via the AF mute
switch (Q1550).
The AF mute switch is mute the AF signals while digital
squelch, call sign squelch, noise squelch, tone squelch are
closed, the audio level is set to minimum position or trans-
mitting.
The power amplified AF signals from the AF power amplifier
(IC1551, pin 4) are applied to the speaker that is connected
to [SP] jack (J1550).
4-1-8 SQUELCH CIRCUITS (MAIN UNIT)
• DIGITAL CODE/CALL SIGN SQUELCH (DV MODE ONLY)
The digital code/call sign squelch circuit detects matched
digital code/call sign and opens the squelch only when
receiving a signal containing a matching digital code/call
sign. When digital code/call sign squelch is in use, and a sig-
nal with a unmatched digital code/call sign is received, the
digital code/call sign squelch circuit mutes the AF signals.
The detected digital audio signals from IC191 (pin 9) are
applied to the CPU (LOGIC-1 unit; IC50) via the mode
switch (IC342, pins 1, 7), GMSK MODEM IC (LOGIC-1 unit;
IC150) and FPGA IC (LOGIC-1 unit; IC200). Then the CPU
analyzes the digital code/call sign and output the AF mute
signal as “RMUT” from the pin 102 to the filter switch (IC1463,
pin 2) via the mute switch (LOGIC-1 unit; Q155).
• NOISE SQUELCH (FM MODE ONLY)
The noise squelch circuit cuts out AF signals when no RF
signals are received. By detecting noise components in
the AF signals, the squelch circuit switches the filter switch
(IC1463).
Portion of the AF signals from the demodulator IC (IC191,
pin 9) are applied to the active filter section in the demodu-
lator IC (IC191, pin 8). The active filter section filters and
amplifies noise components only. The amplified noise signals
are converted into the pulse-type signals at the noise detec-
tor section. The detected signals output from pin 14 (IC191).
The detected signals from the demodulator IC (IC191,
pin 14) are amplified at the noise amplifiers (Q192, Q193)
and then applied to the noise detector (D195). The detected
signals are applied to the CPU (LOGIC-1 unit; IC50, pin 32)
as "NOIS" signals. Then the CPU analyzes the noise condi-
tion and outputs the AF mute signal as “RMUT” from the pin
102 to the filter switch (IC1463, pin 2) via the mute switch
(LOGIC-1 unit; Q155).
• TONE SQUELCH (FM MODE ONLY)
The tone squelch circuit detects tone signals and opens the
squelch only when receiving a signal containing a matching
subaudible tone (CTCSS). When tone squelch is in use, and
a signal with a unmatched or no subaudible tone is received,
the tone squelch circuit mutes the AF signals even when
noise squelch is open.
A portion of “DEAF” signals from the buffer amplifier (IC1460,
pin 1) are applied to the low-pass filters (IC1461, pins 1, 2,
5, 7) to remove AF (voice) signals. The filtered signals are
applied to the CTCSS decoder in the CPU (LOGIC-1 unit,
IC50, pin 33) as “TONI” signals. Then the CPU analyzes
the decoded tone signals and output the AF mute signal as
“RMUT” from the pin 102 to the filter switch (IC1463, pin 2)
via the mute switch (LOGIC-1 unit; Q155).
4-1-9 S-METER CIRCUITS (MAIN UNIT)
Some of the amplified IF signal is applied to the S-meter
detector section in the demodulator IC (IC191) to be con-
verted into DC voltage. The output signal from the demodu-
lator IC (IC191, pin 12) is applied to the mode switch (IC341,
pins 10, 11) and then applied to the CPU (LOGIC-1 unit;
IC50). The CPU then outputs S-meter control signal to the
RC-24 or connected PC via the USB controller (LOGIC-1
unit; IC550).

4-2 TRANSMITTER CIRCUITS
4-2-1 MICROPHONE AMPLIFIER CIRCUIT (MAIN UNIT)
The microphone amplifier circuit amplifies audio signals
from the microphone to a level needed for the modulation
circuit.
While connecting the microphone to ID-1, the AF signals
from the microphone (J1600, pin 6) are applied to the micro-
phone amplifier (Q1673) via the microphone mute switch
(Q1670). The amplified AF signals are applied to the mode
switch (IC1670, pins 1, 6, 7).
While connecting the microphone to RC-24, the AF signals
from the microphone (RC24; J1) are applied to the MAIN
unit (J1600, pin 6) via the buffer amplifier (RC-24; Q13).
• DV MODE
The amplified AF signals from microphone amplifier (Q1673)
are amplified at the ALC amplifier (IC1672, pins 3, 5) via
the mode switch (IC1670, pins 1, 7). The amplified signals
are applied to the IDC amplifier (IC1671, pins 6, 7) and then
passed through the splatter filter (IC1671, pins 1, 3).
The filtered signals are applied to the LOGIC-1 unit via the
J1801 (pin 10).
• FM MODE
The amplified AF signals from microphone amplifier (Q1673)
are passed through the mode switch (IC1670, pins 1, 6)
and then applied to the IDC amplifier (IC1671, pins 6, 7).
The amplified signals are passed through the splatter filter
(IC1671, pins 1, 3) and mode switch (IC1673, pins 1, 6).
The CTCSS signals (CTCS) from the CPU (LOGIC-1 unit;
IC50) via (LOGIC-1 unit; IC57, pin 1) are mixed with the AF
signals from the IDC amplifier (IC1671, pin 7). The mixed
signals are passed through the splatter filter (IC1671, pins 1,
3) and mode switch (IC1673, pins 1, 6).
The switched AF signals (IC1673, pin 6) are applied to the
modulation circuit.
4-2-2 DIGITAL CIRCUITS (LOGIC-1 UNIT)
• DV MODE (VOICE OPERATION)
The AF signals from the splatter filter (MAIN unit; IC1671,
pin 1) are applied to the liner CODEC IC (IC1, pin 24) to
convert into digital voice data at the A/D converter section
as the "DAMOD" signal. The converted digital audio signals
are applied to the AMBE CODEC IC (IC2) for code com-
pression and are then applied to the CPU (IC50).
The digital audio signals are processed at the CPU (IC50)
and then applied to the FPGA IC (IC200).
• DD MODE/DV MODE (LOW SPEED DATA OPERATION)
While operating in DD mode the data signal from connected
PC are applied to the Ethernet controller (IC104) and then
applied to the CPU (IC50)
While operating in DV mode (low speed data operation) the
data signal from connected PC are applied to the USB con-
troller (IC550) and then applied to the CPU (IC50)
The applied data signals to the CPU (IC50) are processed
and then applied to the FPGA IC (IC200).
The output signals from the CPU (IC50) are applied to the
FPGA IC (IC200) to convert to the I/Q baseband signals and
then output from pins 75–80, 82–87, 92–99 (IC200). The I/Q
baseband signals are mixed at the resisters (R250–R293)
and then pass through the baseband filters (IC300, IC301,
IC302).
The filtered signals (I/Q baseband signals) are applied to the
MAIN unit via J400 (pins 1, 3).
4-2-3 MODULATION CIRCUIT (MAIN UNIT)
• DV/DD MODE
The modulation circuit modulates the 2nd LO signal at the
quadrature modulation circuit (IC890) using the I/Q base-
band signals from the LOGIC-1 unit.
The I/Q baseband signals from the LOGIC-1 unit are ampli-
fied at the I/Q baseband amplifiers (IC832, pins 1, 2, 6,
7) and then applied to amplifier section (pins 4, 7) of the
quadrature modulator IC (IC890, pins 4, 7, 14). The 2nd LO
signal is applied to the quadrature modulator IC (IC890, pin 8)
4 - 4
• MODULATION AND TRANSMIT CIRCUITS
FI1020
FI9611st mixer
FI880
Q1020
I/Q baseband
signals
“DAMOD” signal to liner CODEC IC
(LOGIC-1 unit; IC1, pin 24)
“MODI” signal to D631
Q1673
Q1670
IC1672
IC890
Q1080 Q1081 IC1160
AMP
AMP
AMP
AMP
ALC
AMP AMP
HPF
Mute
SW
IDC
AMP
BPF
LPF
LPF BPF
LOGIC-1 unit
Quadrature
modulator
AMP
2nd PLL
LPF ANT
SW
IC1671
IC1671
Q890
LPF
DV mode
DV mode
FM mode
FM mode
IC1673
IC1670
IC831
Microphone

The power amplified signal from the power amplifier (IC1160,
pin 4) is passed through the antenna switch (D1160),
SWR detector circuit (D1166, D1170), low-pass filter which
contains strip-line and C1198, and then applied to the
antenna connector (CHASSIS unit: J1).
4-2-6 APC CIRCUIT (MAIN UNIT)
The APC circuit protects the driver and power amplifiers
from a mismatched output load and stabilizes the output
power.
The SWR detector circuit (D1166, D1170) detects the for-
ward signals and reflection signals, and converts it into DC
voltage. The output voltage is at a minimum level when the
antenna impedance is matched with 50 Ωand is increased
when it is mismatched.
The detected voltage is applied to the APC amplifier (IC1250,
pins 3, 4) and is compared with the reference voltage which
is supplied from the CPU (LOGIC-1 unit: IC50, pin 38) as
"PCON" signal.
When antenna impedance is mismatched, the detected volt-
age exceeds the power setting voltage. The output voltage
of the APC amplifiers (IC1250, IC1251) controls the bias
voltage of the drive (Q1080) and power (IC1160) amplifiers
to reduce the output power.
4-3 PLL CIRCUITS
4-3-1 PLL CIRCUITS (MAIN UNIT)
The PLL circuit provides stable oscillation of the 1st LO fre-
quencies and 2nd LO frequency. The PLL output compares
the phase of the divided VCO frequency to the reference
frequency. The PLL output frequency is controlled by the
divided ratio (N-data) of a programmable divider.
4-3-2 1ST PLL CIRCUIT (MAIN UNIT)
The 1st PLL circuit oscillates the 1st LO frequencies, and
signals are applied to the 1st mixer circuit. The oscillated
4 - 5
and then mixed with the amplified I/Q baseband signals. The
modulated signal is output from pin 14.
The modulated signal (IC890, pin 14) is passed through the
bandpass (FI880) and low-pass (L892, L893, C904–C908)
filters and then applied to the 1st mixer circuit.
• FM MODE
The modulation circuit modulates the 2nd LO signal using
the microphone audio signals.
The switched AF signals from the mode switch (IC1673, pin
6) change the reactance of varactor diode (D631) to modu-
late the 2nd LO signal at the 2nd VCO circuit (Q631, D630).
The modulated signal from the 2nd VCO circuit is amplified
at the buffer amplifiers (Q632, Q771) and is then applied to
the T/R switch (D770). The switched signal is applied to the
2nd LO amplifier (Q890) and then passed through the low-
pass filter (L891, C896–C898), quadrature modulator IC
(IC890), bandpass filter (FI880) and low-pass filter (L892,
L893, C904–C908).
The filtered signal is applied to the 1st mixer circuit.
4-2-4 1ST MIXER CIRCUITS (MAIN UNIT)
The filtered signal from the low-pass filter (L892, L893, C904
–C908) is mixed with the 1st LO signal, generated at the
1st VCO circuit (Q471, Q472, D472) via the buffer amplifier
(Q710), at the 1st mixer circuit (IC960, pin 1, 6) to convert
into the RF signal. The RF signal from the 1st mixer circuit
(IC960, pin 6) is passed through the bandpass filter (FI961)
and then amplified at the RF amplifier (IC1021). The ampli-
fied signal is passed through the bandpass filter (FI1020) to
suppress spurious components.
4-2-5 DRIVE/POWER AMPLIFIER CIRCUITS
(MAIN UNIT)
The filtered RF signal from the bandpass filter (FI1020) is
amplified at the drive (Q1080, Q1081) and power (IC1160)
amplifiers to obtain a stable 10 W of output power.
Loop
filter
Loop
filter
X400
15.3 MHz
Q631, D630
2nd VCO
Buffer
Buffer
Buffer
Q771
Q632
IC551
Q633
IC550
Q400
to 2nd LO amplifier
to 2nd mixer circuit
D771
D770
Analog
switch
LPF
PLL IC
Loop
filter
Q471, Q472,
D472
1st VCO
Buffer
Buffer
Buffer
Buffer
Q710
Q473
Q474
IC400
to 1st mixer circuit
to 1st mixer circuit
D711
D710
1ST PLL CIRCUIT
2ND PLL CIRCUIT
LPF
PLL IC
• PLL CIRCUITS

4 - 6
4-4-2 MAIN UNIT VOLTAGE LINE
Line Description
HV The voltage from a DC power supply.
VCC
The same voltage as the HV line which
is controlled by the power switching cir-
cuit (Q23, Q24). When the power switch is
pushed, the CPU outputs the "PWR" control
signal to the power switching circuit to turn
the circuit ON.
+9
Common 9 V converted from the HV line at
the +9 CTRL circuit (IC1330). The output
voltage is applied to the volume controller
(IC1550), etc.
+5
Common 5 V converted from the +9V line at
the 5 V regulator circuit (IC1331). The out-
put voltage is applied to the mode switches
(IC1462, IC1463), etc.
DM+5
Common 5 V converted from the +9V line at
the 5 V regulator circuit (IC830). The output
voltage is applied to the modulation ampli-
fiers (IC831, IC832), etc.
T+9
Transmit 9 V controlled by the T+9 regula-
tor circuit (Q1333, Q1334, D1331) using the
"TXS" signal from the CPU (LOGIC-1 unit;
IC50, pin 94). The output voltage is applied
to the APC amplifier (IC1250), etc.
T+5
Transmit 5 V controlled by the T+5 regula-
tor circuit (Q1336, D1332, D1333) using the
"TXS" signal from the CPU (LOGIC-1 unit;
IC50, pin 94). The output voltage is applied
to the RF amplifier (IC1021), etc.
R+5
Receive 5 V controlled by the R+5 regulator
circuit (Q1337) using the "RXS" signal from
the CPU (LOGIC-1 unit; IC50, pin 95). The
output voltage is applied to the RF amplifier
(Q2) and 1st mixer (IC71), etc.
T+3
Transmit 3 V controlled by the T+3 regulator
circuit (Q1342) using the "TXS" signal from
the CPU (LOGIC-1 unit; IC50, pin 94). The
output voltage is applied to the 1st mixer
(IC960), etc.
R+3
Receive 3 V controlled by the R+3 regulator
circuit (Q1343) using the "RXS" signal from
the CPU (LOGIC-1 unit; IC50, pin 95). The
output voltage is applied to the RF amplifier
(Q1), etc.
4-4 POWER SUPPLY CIRCUITS
4-4-1 LOGIC-1 UNIT VOLTAGE LINE
Line Description
5V
Common 5 V controlled by the +5 V regula-
tor circuit (Q50 and Q51) using the “PWRS”
signal from the CPU (IC50, pins 101).
3.3V Common 3.3 V converted from the 5V line
by the 3.3V regulator circuit (IC502).
3.2V Common 3.2 V converted from the 5 V line
by the 3.2V regulator circuit (IC4).
signal from the 1st VCO (Q471, Q472, D471) is applied to
the buffer amplifiers (Q473, Q474) and is then applied to the
PLL IC (IC400, pin 6).
The PLL IC contains a prescaler, programmable counter,
programmable divider and phase detector, etc.
The applied signal is divided at the prescaler and program-
mable counter section by the N-data ratio from the CPU
(LOGIC-1 unit; IC50). The divided signal is detected on
phase at the phase detector using the reference frequency
and output from pin 4. The output signal is passed through
the loop filter and is then applied to the 1st VCO circuit.
The oscillated signal at the 1st VCO is buffer amplified at
Q473 and then passed through the low-pass (L474, L475,
C488–C492) and high-pass (L47–L477, C493–C497) filters.
The filtered signal is applied to the buffer amplifier (Q710)
and then applied to the T/R switch (D710, D711).
The receive 1st LO signal from the T/R switch (D711) is
applied to the 1st mixer circuit (IC71).
The transmit signal from the T/R switch (D710) is applied to
the 1st mixer circuit (IC960).
A portion of the signal from the buffer amplifier (Q473) is
fed back to the PLL IC (IC400, pin 6) via the buffer amplifier
(Q474) as the comparison signal.
4-3-3 2ND PLL CIRCUIT (MAIN UNIT)
The 2nd PLL circuit oscillates the 2nd LO frequency, and the
signal is applied to the 2nd mixer circuits.
The signal oscillated at the 2nd VCO circuit (Q631, D630) is
amplified at the buffer amplifiers (Q632, Q633), then applied
to the PLL IC (IC550, pins 2, 19). The applied signal is
divided at the prescaler and programmable counter section
by the N-data ratio from the CPU (LOGIC-1 unit; IC50). The
divided signal is detected on phase at the phase detector
using the reference frequency and output from pins 8, 13
(IC550).
While operating in DV/DD mode, the detected signal from
pin 13 (IC550) is passed through the loop filter (R555–R557,
C564, C567) and then applied to the 2nd VCO circuit via the
mode switch (IC551, pins 1, 7).
While operating in FM mode, the detected signal from pin 8
(IC550) is passed through the loop filter (R559–R561, C571,
C574) and then applied to the 2nd VCO circuit via the mode
switch (IC551, pins 1, 6).
The oscillated signal at the 2nd VCO is amplified at the buf-
fer amplifiers (Q632 Q771), and is then applied to the T/R
switch (D770, D771).
The receive 2nd LO signal from the T/R switch (D771) is
applied to the 2nd mixer circuit (Q131).
The transmit signal from the T/R switch (D770) is applied to
the 2nd LO amplifier (Q890).
A portion of the signal from the buffer amplifier (Q632) is fed
back to the PLL IC (IC550, pins 2, 19) via the buffer ampli-
fier (Q633) and low-pass filter (L631, C653, C654) as the
comparison signal.

4 - 7
4-5 PORT ALLOCATIONS
4-5-1 CPU (LOGIC-1 UNIT; IC50)
Pin
number
Port
name Description
29 MU/D Input port for up/down signal from the
connected microphone.
32 NOIS Input port for the noise signal from the
noise detector (MAIN unit; D195).
31 RSSI
Input port for the S-meter signal from
the demodulator IC (MAIN unit; IC191,
pin 12).
33 TONI
Input port for CTCSS signal from the
low-pass filter (MAIN unit, IC1461, pin
1).
42 TXD1 Output data signals to the USB con-
troller (IC550, pin 24).
43 RXD1
Input port for data signals from the
USB controller (IC550, pin 25) via the
(IC553).
53 SDA I/O port for data signals from/to the
EEPROM (IC54, pin 5).
54 SCL Outputs clock signal to the EEPROM
(IC54, pin 6).
61 BEEP Outputs beep audio signals.
71 RESET Input port for reset signal form the re-
set IC (IC52, pin 1).
72 P2RSC
Outputs control signal to the mode
switch (MAIN unit; IC551, pin 5) via
the level converter (IC55).
73 P2STC
Outputs strobe signal to the 2nd PLL
IC (MAIN unit; IC550, pin 3) via the
level converter (IC55).
74 PDATC
Outputs the data signal to the 1st and
2nd PLL ICs (MAIN unit; IC400, pin 15,
IC550, pin 5) via the level converter
(IC55).
75 PSCKC
Outputs clock signal to the 1st and 2nd
PLL ICs (MAIN unit; IC400, pin 14,
IC550, pin 4) via the level converter
(IC55).
76 P1STC
Outputs strobe signal to the 1st PLL
IC (MAIN unit; IC400, pin 16) via the
level converter (IC55).
77 +5AC
Outputs control signal to the 5A
(Q1345) and D+5 (Q1347) regulators
via the level converter (IC55).
Low: While the +5 and D+5 regu-
lators are activated.
78 W/NSC
Outputs control signal to the DV/FM
filter switches (MAIN unit; D192,
D193) via the level converter (IC55).
High: While DV mode is selected.
79 ADSWC
Outputs control signal to the mode
switches (MAIN unit; IC1411, IC1670,
IC1673) via the level converter (IC55).
Low: While DV mode is selected.
80 TXLED Outputs TX LED control signal.
High: During transmit.
82 RXLED
Outputs RX LED control signal.
High: While receiving or squelch is
opened.
Pin
number
Port
name Description
85 PCON Outputs control signal to the TX power
controller (MAIN unit; Q1250).
86 ULCK Input port for the PLL unlock signal.
High: The PLL circuit is unlocked.
87 MMUT
Outputs the microphone mute sig-
nal to the mute switch (MAIN unit;
Q1670).
Low: While microphone audio is
muted.
93 SCAN
Outputs scan control signal to the
scan switch (Q400).
High: While scanning.
94 TXS
Outputs the T+5, T+3 regulator
circuits (MAIN unit; Q1336, Q1342)
control signal.
High: During transmit.
95 RXS
Outputs the R+5, R+3 regulator
circuits (MAIN unit; Q1337, Q1343)
control signal.
High: During receive.
96 AMUT
Outputs the AF mute signal to the AF
mute switch (MAIN unit; Q1550).
Low: While digital code/call
sign/noise/tone squelch are
closed, the audio level is
set to minimum position or
transmitting.
102 RMUT
Outputs the SQL mute signal to the
AF switch (MAIN unit; IC1463, pin 2).
High: While noise or tone squelch
is closed.
103 AFCSW Outputs AFC switch (IC352, pin 5)
control signal.
105 DACK2 Outputs clock signal to the D/A con-
verter (IC57, pin 7).
106 DADAT2 Outputs the data signal to the D/A
converter (IC57, pin 6).
107 DACK1 Outputs clock signal to the D/A con-
verter (IC56, pin 7).
108 DADAT1 Outputs the data signal to the D/A
converter (IC56, pin 6).
128 FSTB Outputs strobe signal to the FPGA IC
(IC200).
129 MSTRC
Outputs strobe signal to the liner
CODEC IC (IC1) and FPGA IC
(IC200).
130 MDATC
Outputs the data signal to the liner
CODEC IC (IC1) and FPGA IC
(IC200).
131 MCLKC
Outputs clock signal to the liner
CODEC IC (IC1) and FPGA IC
(IC200).
132 MRESC
Outputs reset signal to the liner
CODEC IC (IC1) and FPGA IC
(IC200).

5 - 1
SECTION 5 ADJUSMENT PROCEDURESE
5-1 PREPARATION
When adjusting ID-1, ADJUSTMENT SOFTWARE, JIG CABLE (see illustration on page 5-2) and OPC-1127 USB CABLE are re-
quired.
▄ REQUIRED TEST EQUIPMENT
EQUIPMENT GRADE AND RANGE EQUIPMENT GRADE AND RANGE
DC power supply Output voltage
Current capacity
: 13.8 V DC
: 10 A or more Audio generator Frequency range
Measuring range
: 300–3000 Hz
: 1–500 mV
Modulation analyzer Frequency range
Measuring range
: DC–1500 MHz
: 0 to ±10 kHz Attenuator Power attenuation
Capacity
: 50 or 60 dB
: 20 W
Frequency counter
Frequency range
Frequency accuracy
Sensitivity
: 0.1–1500 MHz
: ±1 ppm or better
: 100 mV or better
Standard signal
generator (SSG)
Frequency range
Output level
: 0.1–1500 MHz
: 0.1 µV to 32 mV
(–127 to –17 dBm)
Digital multimeter Input impedance : 10 MΩ/V DC or more AC millivoltmeter Measuring range : 10 mV to 10 V
RF power meter
Measuring range
Frequency range
Impedance
SWR
: 1–20 W
: 1000–1500 MHz
: 50 Ω
: Better than 1.2 : 1
Oscilloscope Frequency rang
Measuring range
: DC–20 MHz
: 0.01–20 V
External speaker Input impedance
Capacity
: 8 Ω
: 10 W or more
Spectrum analyzer Frequency range
Spectrum bandwidth
: At least 1500 MHz
: 100 kHz or more DC Ammeter Measuring capacity : 3 A
MSYSTEM REQUIREMENTS
• Microsoft®Windows®98/98SE/Me/2000/XP
• USB port
MADJUSTMENT SOFTWARE INSTALLATION
qQuit all applications when Windows is running.
wInsert the CD into the appropriate CD drive.
eDouble-click the “Setup.exe” contained in the adjustment
software folder in the CD drive.
rThe “Welcome to the InstallShield Wizard for adjustment
software screen will appears.
Click [Next>].
tThe “Choose Destination Location” will appears.
Click [Next>] to install the software into the specified fold-
er.
y
After the installation is completed, the “InstallShield Wiz-
ard Complete” will appears.
Click [Finish].
uEject the CD.
iThe adjustment software icon appears on the desktop
screen.
M
STARTING SOFTWARE ADJUSTMENT
qConnect the transceiver and PC with the OPC-1127.
wTurn the transceiver power ON.
eBoot up Windows, and double click the adjustment soft-
ware icon on the desktop screen.
Then the control panel screen will appears.
rClick [Adjustment (A)] in the menu bar and then click [Ad-
justment panel (F9)] in the pull down menu.
Then the adjustment screen will appears.
tSet or modify adjustment data as desired.
MOPERATING ON THE ADJUSTMENT MODE
(CONNECTED COMPUTER KEYBOARD)
• Adjustment item selection* : [↑]/[↓]
• Specified value adjustment : [←]/[→]
• Mode selection : [M]
• PTT control : [T]
• RF power selection : [P]
• AF level control [UP] : [Q]
• AF level control [DOWN] : [W]
• Squelch level control [UP] : [A]
• Squelch level control [DOWN] : [S]
• Read the transceiver's data : [F5]
• All Default setting : [CTRL]+[D]
*When select the adjustment item, the adjustment frequency
and operating mode are selected automatically.

5 - 2
pin 6 (MIC)
pin 4 (PTT)
pin 7 (GND)
[PTT]
pin 5 (MICE)
to the antenna connector
Standard signal generator
0.1–1500 MHz
–127 to –17 dBm (0.1 µV to 32 mV)
RF power meter
50 Ω, 20 W
Modulation
analyzer
Attenuator
50 dB or 60 dB
DC power supply
13.8 V, 10 A or more
JIG CABLE INFORMATION
to the microphone connector
Audio generator
300 Hz to 3 kHz
AC millivoltmeter
Coution
DO NOT transmit
while an SSG is
connected to the
antenna connec-
tor.
PC
to USB
port
• CONNECTION

5 - 3
5-2 PLL AND CODEC ADJUSTMENT
ADJUSTMENT ADJUSTMENT CONDITION MEASUREMENT VALUE ADJUSTMENT
UNIT LOCATION UNIT ADJUST
FPGA
FREQUENCY
[Set FPGA
frequency]
1 • Operating freq. : 1240.00 MHz
• Mode : DD mode
• Receiving
LOGIC-1
unit
Connect a frequency
counter to the check
point "CP200".
16.3840 MHz LOGIC-1
unit
C202
2 • Operating freq. : 1240.00 MHz
• Mode : DV mode
• Receiving
9.8304 MHz LOGIC-1
unit
C215
PLL LOCK
VOLTAGE
1 • Operating freq. : 1240.00 MHz
• Mode : DV mode
• Connect an RF power meter or
50 Ωdummy load to the antenna
connector.
• Receiving
MAIN
unit
Connect a digital
multimeter or an oscillo-
scope to the check point
"LV1".
More than
0.9 V
Verify
2 • Operating freq. : 1300.00 MHz
• Receiving
Less than
4.4 V
3 • Mode : FM mode
• Receiving
MAIN
unit
Connect a digital
multimeter or an oscillo-
scope to the check point
"LV2".
3.1–4.0 V
4 • Mode : DD mode
• Receiving
2.6–3.3 V
5 • Mode : FM mode
• Transmitting
3.3–4.0 V
I/Q
BALANCE
[FPGA D.C.
voltage ad-
justment
/DV I]
1•Preset "IQ Direct-current output"
ON.
• Operating freq. : 1270.00 MHz
• Mode : DV mode
• Connect an RF power meter or
50 Ωdummy load to the antenna
connector.
• Transmitting
MAIN
unit
Connect a digital
multimeter or an oscillo-
scope to the check point
"CP.I".
The same
voltage of the
check point
"CP.IR".
PC
screen
[FPGA
D.C.
voltage
adjust-
ment
/DV I]
[FPGA D.C.
voltage ad-
justment
/DV Q]
2 • Transmitting MAIN
unit
Connect a digital
multimeter or an oscillo-
scope to the check point
"CP.Q".
The same
voltage of the
check point
"CP.QR".
PC
screen
[FPGA
D.C.
voltage
adjust-
ment
/DV Q]
[FPGA D.C.
voltage ad-
justment
/DV I]
3 • Transmitting Rear
panel
Connect a spectrum
analyzer to the antenna
connector through an
attenuator.
Minimum out-
put level
PC
screen
[FPGA
D.C.
voltage
adjust-
ment
/DV I],
[FPGA
D.C.
voltage
adjust-
ment
/DV Q]
[FPGA D.C.
voltage ad-
justment
/DV Q]
4
•
Repeat step 3 and step 4 several times.

CP.IR
CP.I
I/Q balance check point
LV2
LV1
CP.Q
CP.QR
LV1
PLL lock voltage
check point
LV2
PLL lock voltage
check point
CP200
FPGA frequency
check point
C202
C215
FPGA frequency
adjustment
5 - 4
• MAIN AND LOGIC-1 UNITS

5 - 5
5-3 TRANSMITTER ADJUSTMENT
ADJUSTMENT ADJUSTMENT CONDITION MEASUREMENT VALUE ADJUSTMENT
UNIT LOCATION UNIT ADJUST
YGR
CURRENT
[FPGA D.C.
voltage ad-
justment
/DV I ]
1•Preset R1086 and R1087 maxi-
mum counterclockwise.
• Preset "IQ Direct-current output"
ON.
• Operating freq. : 1300.00 MHz
• Mode : DV mode
• Connect an RF power meter or
50 Ωdummy load to the antenna
connector.
• Transmitting
Rear
panel
Connect an ammeter
between the DC power
supply and ID-1.
100 mA higher
from the pre-
set position.
MAIN
unit
R1087
2100 mA higher
from step 1.
MAIN
unit
R1086
REFERENCE
FREQUENCY
[REF Crystal
adjustment]
1 • Operating freq. : 1300.00 MHz
• Mode : FM mode
• Connect an RF power meter or
50 Ωdummy load to the antenna
connector.
• Transmitting
Rear
panel
Loosely couple a fre-
quency counter to the
antenna connector.
1300.0000 MHz PC
screen
[REF
Crystal
adjust-
ment]
FM
CARRIER
[FPGA D.C.
voltage ad-
justment
/FM I]
1 • Operating freq. : 1300.00 MHz
• Mode : FM mode
• Connect an RF power meter or
50 Ωdummy load to the antenna
connector.
• Transmitting
MAIN
unit
Connect a digital
multimeter or an oscillo-
scope to the check point
"CP30".
The same
voltage that
during in DV
mode (TX)
at the check
point "CP30".
PC
screen
[FPGA
D.C.
voltage
adjust-
ment
/FM I]
[FPGA D.C.
voltage ad-
justment
/FM Q]
2 • Transmitting The same
adjustment as
step 1, if need.
PC
screen
[FPGA
D.C.
voltage
adjust-
ment
/FM Q]
OUTPUT
POWER
[TX output
adjustment]
1 • Operating freq. : 1300.00 MHz
• Mode : FM mode
• TX power : High
• Transmitting
Rear
panel
Connect an RF power
meter to the antenna
connector.
11 W MAIN
unit
R1251
FM
DEVIATION
[FM
modulation
adjustment]
1 • Operating freq. : 1270.00 MHz
• Mode : FM mode
• Connect an audio generator to
the [MIC] connector and set as
:
1.0 kHz/20 mVrms
• Set a Modulation analyzer as:
HPF : OFF
LPF : 20 kHz
De-emphasis : OFF
Detector : (P–P)/2
• Transmitting
Rear
panel
Connect a modulation
analyzer to the antenna
connector through an
attenuator.
±4.35 kHz MAIN
unit
R1704
DSP INPUT
LEVEL
[DSP input
level adjust-
ment]
1 • Operating freq. : 1270.00 MHz
• Connect an audio generator to
the [MIC] connector and set as
:
1.0 kHz/20 mVrms
• Connect an RF power meter or
50 Ωdummy load to the antenna
connector.
• Transmitting
LOGIC-1
unit
Connect an oscillo-
scope to the check point
"CP207".
750 mVp-p MAIN
unit
R1707

5 - 6
LV2
CP207
LV1
R1251
TX power adjustment
CP207
DSP input level
check point
R1707
DSP input level
adjustment
R1087
YGR current adjustment
R1704
FM deviation adjustment
CP30
FM carrier check point
R1086
YGR carrent
adjustmentent
• MAIN AND LOGIC-1 UNITS

5 - 7
5-4 RECEIVER ADJUSTMENT
ADJUSTMENT ITEM ADJUSTMENT CONDITION OPERATION
SQUELCH
LEVEL
[SQL adjustment
/FM thresh]
1• Operating freq. : 1270.00 MHz
• Mode : FM mode
• Connect an SSG to the antenna connector and
set as:
Level : 0.11 µV* (–126 dBm)
Modulation : 1 kHz
Deviation : 3.5 kHz
• Receiving
• Push [ENTER] on the connected computer key-
board to set to "SQL adjustment/FM thresh" level.
[SQL adjustment
/FM tight]
2• Set an SSG as:
Level : 0.18 µV* (–122 dBm)
• Receiving
• Push [ENTER] on the connected computer key-
board to set to "SQL adjustment/FM tight" level.
AFC CENTER
[AFC center
voltage adjust-
ment/FM]
1• Operating freq. : 1270.00 MHz
• Mode : FM mode
• Connect an SSG to the antenna connector and
set as:
Level : 1 mV* (–47 dBm)
Modulation : OFF
• Receiving
• Push [ENTER] on the connected computer's key-
board to set to "AFC center voltage adjustment/
FM" level.
[AFC center
voltage adjust-
ment /DV]
2• Mode : DV mode
• Receiving
• Push [ENTER] on the connected computer key-
board to set to "AFC center voltage/DV" level.
S-METER (FM)
[S-meter
adjustment
/FM min]
1• Operating freq. : 1270.00 MHz
• Mode : FM mode
• Connect an SSG to the antenna connector and
set as:
Level : 0.18 µV* (–122 dBm)
Modulation : OFF
• Receiving
• Push [ENTER] on the connected computer key-
board to set to "S-meter adjustment/FM min" level.
[S-meter
adjustment
/FM full]
2• Set an SSG as:
Level : 5.6 µV* (–92 dBm)
• Receiving
• Push [ENTER] on the connected computer key-
board to set to "S-meter adjustment/FM full" level.
S-METER (DV)
[S-meter
adjustment
/DV min]
1• Operating freq. : 1270.00 MHz
• Mode : DV mode
• Set an SSG as:
Level : 0.18 µV* (–122 dBm)
Modulation : OFF
• Receiving
• Push [ENTER] on the connected computer key-
board to set to "S-meter adjustment/DV min" level.
[S-meter
adjustment
/DV full]
2• Set an SSG as:
Level : 5.6 µV* (–92 dBm)
• Receiving
• Push [ENTER] on the connected computer key-
board to set to "S-meter adjustment/DV full" level.
S-METER (DD)
[S-meter
adjustment
/DD min]
1• Operating freq. : 1270.00 MHz
• Mode : DD mode
• Set an SSG as:
Level : 1.6 µV* (–103 dBm)
Modulation : OFF
• Receiving
• Push [ENTER] on the connected computer key-
board to set to "S-meter adjustment/DD min" level.
[S-meter
adjustment
/DD full]
2• Set an SSG as:
Level : 5.6 µV* (–92 dBm)
• Receiving
• Push [ENTER] on the connected computer key-
board to set to "S-meter adjustment/DD full" level.
*The output level of the standard signal generator (SSG) is indicated as the SSG's open circuit.