ICP DAS USA PIO-DA4 User manual

PIO-DA4/DA8/DA16
PIO-DA4U/DA8U/DA16U
PISO-DA4U/DA8U/DA16U
User Manual Version 2.9
Feb. 2011
Warranty
All products manufactured by ICP DAS are warranted against defective
materials for a period of one year from the date of delivery to the original
purchaser.
Warning
ICP DAS assumes no liability for damages consequent to the use of this product.
ICP DAS reserves the right to change this manual at any time without notice.
The information furnished by ICP DAS is believed to be accurate and reliable.
However, no responsibility is assumed by ICP DAS for its use, nor for any
infringements of patents or other rights of third parties resulting from its use.
Copyright
Copyright © 2010 by ICP DAS. All rights are reserved.
Trademark
Names are used for identification only and may be registered trademarks of their
respective companies.
PIO-DA/PISO-DA Series User Manual (Ver.2.9, Feb. 2011, PMH-009-29 ) 1

Tables of Contents
1. INTRODUCTION .............................................................................................................................3
1.1 FEATURES ...................................................................................................................................4
1.2 SPECIFICATIONS ..........................................................................................................................5
1.3 ORDER INFORMATION .................................................................................................................6
1.4 PRODUCT CHECKLIST..................................................................................................................6
2. HARDWARE CONFIGURATION .................................................................................................7
2.1 BOARD LAYOUT..........................................................................................................................7
2.2 COUNTER ARCHITECTURE...........................................................................................................9
2.3 INTERRUPT OPERATION.............................................................................................................10
2.4 D/I/O BLOCK DIAGRAM............................................................................................................17
2.5 D/A ARCHITECTURE .................................................................................................................20
2.6 D/A CONVERSION OPERATIONS ................................................................................................21
2.7 PIN ASSIGNMENTS.....................................................................................................................31
2.8 DAUGHTER BOARDS..................................................................................................................34
3. I/O CONTROL REGISTER...........................................................................................................39
3.1 HOW TO FIND THE I/O ADDRESS ...............................................................................................39
3.2 THE ASSIGNMENT OF THE I/O ADDRESSES................................................................................45
3.3 THE I/O ADDRESS MAP.............................................................................................................47
4. SOTFWARE INSTALLATION.....................................................................................................55
4.1 SOFTWARE INSTALLING PROCEDURE ........................................................................................55
4.2 PNPDRIVER INSTALLATION......................................................................................................56
4.3 CONFIRM THE SUCCESSFUL INSTALLATION...............................................................................57
5. DEMO PROGRAMS.......................................................................................................................58
5.1 DEMO PROGRAMS FOR WINDOWS.............................................................................................58
5.2 DEMO PROGRAMS FOR DOS......................................................................................................59
5.3 PIO_PISO.EXE FOR WINDOWS................................................................................................61
5.4 DEMO1....................................................................................................................................62
5.5 DEMO2....................................................................................................................................63
5.6 DEMO3....................................................................................................................................64
5.7 DEMO5....................................................................................................................................66
5.8 DEMO8....................................................................................................................................68
5.9 DEMO9....................................................................................................................................69
PIO-DA/PISO-DA Series User Manual (Ver.2.9, Feb. 2011, PMH-009-29 ) 2

1. Introduction
The PISO-DA4U/DA8U/DA16U and PIO-DA4U/DA8U/DA16U analog output
boards support the universal PCI interface (3.3 V/5 V PCI). These cards are
equipped with 4/8/16 14-bit analog output channels. Each of the D/A channels
features a double-buffered latch. The PISO-DAxU and the PIO-DAxU series
cards (universal PCI versions) are fully compatible with the PIO-DAx cards (PCI
versions) and users can directly replace the PIO-DAx with either the PISO-DAxU
or the PIO-DAxU without any need for software/driver modification.
Adds high-voltage isolation design has been added to the PISO-DA series which
provides the ability to protect the user’s computer from unexpected voltage
surges via the built-in high-quality isolation components that feature a 2500 VDC
bus-type isolation. For both the PIO-DA and the PISO-DA series, the voltage
output range is from -10 V to +10 V, with a current output range from 0 to 20 mA.
In addition, the PISO-DA and PIO-DA series also provide the following
advantages:
1. Accurate and easy-to-use calibration
ICP DAS provides software-based calibration instead of the previous
manual calibration so that jumpers and trim-pots are no longer required.
The calibration information can be saved in EEPROM for long-term use.
2. Individual channel configuration
Every channel can be individually configured as either voltage or current
output.
3. Card ID
ICP DAS provides a Card ID function for both the PISO-DA series and
the PIO-DA4U/DA8U/DA16U (version 1.1 or above series). Users can set
a unique card ID for each card, which can then be used to individually
identify then if more than two boards are used in a single PC.
Note: This card needs a ±12 V power supply, which can be found in either a
regular PC or an Industrial PC.
!
PIO-DA/PISO-DA Series User Manual (Ver.2.9, Feb. 2011, PMH-009-29 ) 3

1.1 Features
Supports the +5 V PCI bus for PIO-DA series
supports the +5 V and +3.3 V PCI bus for PIO-DAxU/PISO-DAxU series
Digital input port can be set to either pull-high or pull-low for PIO-DAxU/
PISO-DAxU series
Card ID function for PIO-DAxU/PISO-DAxU series
Built-in DC/Dc converter with 3000 VDC isolation for PISO-DAxU series
2500 VDC bus-type and power isolation protection for PISO-DAxU series
4/8/16 analog output channels, 14-bit analog output
Voltage output range ±10 V
Current output range: 0 ~ 20 mA (sink)
Two pacer timer interrupt sources
Double-buffered D/A latch
Software calibration
16 D/I channels, 16 D/O channels
One D-Sub connector, two 20-pin flat cable connectors
Connects directly to DB-16P, DB-16R, DB-24C, DB-24PR and DB-24POR
daughter boards
Comparison Table of the Different Version Information:
D/I Register Pin Assignment Card ID
PIO-DA 0xE0/E4/E8/EC
0xF0/F4/F8/FC
A. GND
(CN3.5/10/15/24/29) N/A
PIO-DAxU V1.0 0xE0/E4/E8/EC
0xF0/F4/F8/FC
A. GND
(CN3.5/10/15/24/29) N/A
PIO-DAxU V1.1 0xE0/E4/E8/EC
0xF0/F4/F8/FC
A. GND
(CN3.5/10/15/24/29) Yes
PIO-DAxU V1.2
or above 0xE0/E4 A. GND
(CN3.5/10/15) Yes
PISO-DAxU V1.3
or above 0xE0/E4 A. GND
(CN3.5/10/15/24/29) Yes
PIO-DA/PISO-DA Series User Manual (Ver.2.9, Feb. 2011, PMH-009-29 ) 4

1.2 Specifications
Model Name PISO-DA4U/DA8U/DA16U PIO-DA4U/DA8U/DA16U
Analog Output
Isolation Voltage 2500 V (Bus Type) N/A
Channels 4/8/16 independent 4/8/16 independent
Resolution 14-bit
Accuracy 0.01% of FSR ± 2 LSB @ 25 °C, ± 10 V
Output Range Voltage: +/- 10 V
Current: 0 ~ 20 mA
Output Driving +/- 5 mA
Slew Rate 0.71 V/µs
Output Impedance 0.1 Ωmax.
Operating Mode Software
Digital Input
Channels 16
Compatibility 5 V/TTL
Input Voltage Logic 0: 0.8 V max.
Logic 1: 2.0 V min.
Response Speed 1.0 MHz (Typical)
Digital Output
Channels 16
Compatibility 5 V/TTL
Output Voltage Logic 0: 0.4 V max.
Logic 1: 2.4 V min.
Output Capability Sink: 2.4 mA @ 0.8 V
Source: 0.8 mA @ 2.0 V
Response Speed 1.0 MHz (Typical)
Timer/Counter
Channels 3
Resolution 16-bit
Compatibility 5 V/TTL
Reference Clock Internal: 4 MHz
General
Bus Type 3.3 V / 5 V Universal PCI, 32-bit, 33 MHz
Data Bus 8-bit
Card ID Yes (4-bit) Yes (4-bit) for Version 1.1 or
above
I/O Connector Female DB37 x 1
20-pin box header x 2
Dimensions
(L x W x D) 180 mm x 97 mm x 22 mm 188 mm x 97 mm x 22 mm (Version 1.1 or above)
Power Consumption
2200 mA @ +5 V (PISO-DA4U)
2400 mA @ +5 V (PISO-DA8U)
3000 mA @ +5 V (PISO-DA16U)
600 mA@ +5 V (PIO-DA4U)
800 mA@ +5 V (PIO-DA8U)
1400 mA @ +5 V (PIO-DA16U)
Operating
Temperature 0 ~ 60 °C
Storage Temperature -20 ~ 70 °C
Humidity 5 ~ 85% RH, non-condensing
PIO-DA/PISO-DA Series User Manual (Ver.2.9, Feb. 2011, PMH-009-29 ) 5

1.3 Order Information
PIO-DA4: PCI bus 4-channel D/A board
PIO-DA8: PCI bus 8-channel D/A board
PIO-DA16: PCI bus 16-channel D/A board
PIO-DA4U: Universal PCI, 4-channel D/A board
PIO-DA8U: Universal PCI, 8-channel D/A board
PIO-DA16U: Universal PCI, 16-channel D/A board
PISO-DA4U: Universal PCI, 4-channel isolated D/A board
PISO-DA8U: Universal PCI, 8-channel isolated D/A board
PISO-DA16U: Universal PCI, 16-channel isolated D/A board
1.3.1 Options
DB-16P: 16 channel isolated D/I board
DB-16R: 16 channel relay board
DB-24PR: 24 channel power relay board
DB-24POR: 24 channel PhotoMos output board
DB-24C: 24-channel open-collector output board
ADP-20/PCI : extender, 20-pin header to 20-pin header for PCI Bus I/O
1.4 Product Checklist
The shipping package includes the following items:
One PIO-DA or PISO-DA series card
One CD-ROM
One Quick Start Guide.
It is recommended that you read the Quick Start Guide first.All necessary
and essential information is given in the Quick Start Guide, including:
Where to get the software driver, demo programs and other resources.
How to install the software.
How to test the card.
Attention!
If any of these items are missing or damaged, contact the dealer from
whom you purchased the product. Please save the shipping materials and
carton in case you need to ship or store the product in the future.
PIO-DA/PISO-DA Series User Manual (Ver.2.9, Feb. 2011, PMH-009-29 ) 6

2. Hardware configuration
2.1 Board Layout
¾PIO-DA4/DA8/DA16 Board Layout
CON1
CON2
CON3
PCI BUS
PIO-DA16
PIO-DA8
PIO-DA4
12
1920
12
1920
DI
DO
CON1: 16-channel D/O
CON2: 16-channel D/I
CON3: 4/8/16-channel D/A converter voltage/current output
PIO-DA/PISO-DA Series User Manual (Ver.2.9, Feb. 2011, PMH-009-29 ) 7

¾PIO-DA4U/DA8U/DA16U and
PISO-DA4U/DA8U/DA16U Board Layout
CON1: 16-channel D/O
CON2: 16-channel D/I
CON3: 4/8/16 channel D/A converter voltage/current output
SW1: Card ID
PIO-DA/PISO-DA Series User Manual (Ver.2.9, Feb. 2011, PMH-009-29 ) 8

2.2 Counter Architecture
There is a single 8254(Timer/Counter) chip on the PIO-DA/PISO-DA series
board and provides two interrupt sources. The first is a 16-bit timer output (INT0)
and the other one is a 32-bit timer output (INT1). The block diagram is shown
below:
OUT0
CLK0
GATE0
Counter0
OUT1
CLK1
GATE1
Counter1
OUT2
CLK2
GATE2
Counter2
Vcc
INT0
INT1
4MHz
8254 Timer/Counter
PIO-DA/PISO-DA Series User Manual (Ver.2.9, Feb. 2011, PMH-009-29 ) 9

2.3 Interrupt Operation
There are two interrupt sources included in the PIO-DA/PISO-DA series. These
two signals are named as INT0 and INT1, and their signal sources are as
follows:
INT0: 8254 counter0 output (Refer to Sec. 2.2)
INT1: 8254 counter2 output (Refer to Sec. 2.2)
If only one interrupt signal source is used, the interrupt service routine doesn’t
have to identify the interrupt source. Refer to DEMO3.C and DEMO4.C for more
information.
If there is more than one interrupt source, the interrupt service routine has to
identify the active signals in the following manner: (Refer to DEMO5.C and
DEMO6.C)
1. Read the new status of all interrupt signal sources
2. Compare the new status with the old status to identify the active signals
3. If INT0 is active, service it
4. If INT1 is active, service it
5. Save the new status to replace the old status
Note:
If the interrupt signal is too short, the new status may be the same as the
old status. In that situation, the interrupt service routine will not be able to
identify which interrupt source is active, so the interrupt signal must be
hold_active for long enough until the interrupt service routine is executed.
This hold_time is different for different OS versions. The hold_time can be
as short as a micro-second or as long as second. In general, 20 mS should
be long enough for all OS version.
!
PIO-DA/PISO-DA Series User Manual (Ver.2.9, Feb. 2011, PMH-009-29 ) 10

2.3.1 Interrupt Block Diagram
INT\
Level_trigger
INT_CHAN_0
INT_CHAN_1
initial_low
active_high
(to PCI slot)
The interrupt output signal of PIO-DA/PISO-DA series cards, INT\, is set to
Level-Trigger and Active_Low. If INT\ generates a low_pulse, the PIO-
DA4/8/16 will interrupt the PC once each time. If INT\ is fixed at low_level, the
PIO-DA4/8/16 will interrupt the PC continuously. So for the signal pulse_type
for INT_CHAN_0/1 must be controlled and must be fixed at a low_level
state normally and a high_pulse generated to interrupt the PC.
The priority of INT_CHAN_0/1 is the same. If both of these signals are active at
the same time, then INT\ will only be active once at a time. So the interrupt
service routine has to read the status of both interrupt channels to per form a
multiple-channel interrupt. Refer to Sec. 2.3 for more information.
DEMO5.C →for INT_CHAN_0 & INT_CHAN_1
If only one interrupt source is used, the interrupt service routine doesn’t have to
read the status of the interrupt source. The demo programs, DEMO3.C and
DEMO4.C, are designed to demons rate a single channel interrupt. See:
DEMO3.C →for INT_CHAN_1 only (initial high)
DEMO4.C →for INT_CHAN_1 only (initial low)
PIO-DA/PISO-DA Series User Manual (Ver.2.9, Feb. 2011, PMH-009-29 ) 11

2.3.2 INT_CHAN_0/1
INT0/1
Inverted/Noninverted
select
(INV0/1)
Enable/Disable select
(EN0/1)
INT_CHAN_0/1
The architecture for INT_CHAN_0 and INT_CHAN_1 is shown in the above
figure. The only difference between INT0 and INT1 is that the INT_CHAN_0
signal source is from the 8254 counter0 output and the INT_CHAN_1 signal
source is from the 8254 counter2 output.
INT_CHAN_0/1 must be fixed at a low level state normally and a
high_pulse generated to interrupt the PC.
EN0/1 can be used to enable/disable the INT_CHAN_0/1 in the following
manner: (Refer to Sec.3.3.4)
EN0/1 = 0 →INT_CHAN_0/1 = disabled
EN0/1 = 1 →INT_CHAN_0/1 = enabled
INV0/1 can be used to invert/non-invert INT0/1 in the following manner: (Refer to
Sec.3.3.6)
INV0/1 = 0 →INT_CHAN_0/1 = inverted state for INT0/1
INV0/1 = 1 →INT_CHAN_0/1 = non-inverted state for INT0/1
As noted above, if INT\ is fixed at a low level state, the PIO-DA4/8/16 will
interrupt the PC continuously, so the interrupt service routine should use
INV0/1 to invert/non-invert the INT0/1 in order to generate a high_pulse
(Refer to the next section)
PIO-DA/PISO-DA Series User Manual (Ver.2.9, Feb. 2011, PMH-009-29 ) 12

2.3.3 Initial_high, active_low Interrupt source
If INT0 (8254 counter0 output) is an initial_high, active_low signal (depending on
8254 counter mode), the interrupt service routine should use INV0 to invert/non-
invert INT0 to generate a high_pulse in the following manner: (Refer to
DEMO3.C)
Initial settings:
out
p
ortb
(
wBase+0x2a
,
0
);
/
* select the inverted INT0 *
/
now_int_state=1; /* initial state for INT0 */
void interrupt irq_service()
{
if (now_int_state==1) /* now INT0 is changed to LOW */(a)
{ /* --> INT_CHAN_0=!INT0=HIGH now */
COUNT_L++; /* find a LOW_pulse (INT0) */
If((inport(wBase+7)&1)==0) /* the INT0 is still fixed in LOW */
Æ{ /* need to generate a high_pulse */
outportb(wBase+0x2a,1); /* INV0 select the non-inverted input */(b)
/* INT_CHAN_0=INT0=LOW --> */
/* INT_CHAN_0 generate a high_pulse */
now_int_state=0; /* now INT0=LOW */
}
else now_int_state=1; /* now INT0=HIGH */
/* don’t have to generate high_pulse */
}
else /* now INT0 is changed to HIGH */(c)
{ /* --> INT_CHAN_0=INT0=HIGH now */
COUNT_H++; /* find a HIGH_pulse (INT0) */
If((inport(wBase+7)&1)==1) /* the INT0 is still fixed in HIGH */
{ /* need to generate a high_pulse */
outportb(wBase+0x2a,0); /* INV0 select the inverted input */(d)
/* INT_CHAN_0=!INT0=LOW --> */
/* INT_CHAN_0 generate a high_pulse */
now_int_state=1; /* now INT0=HIGH */
}
else now_int_state=0; /* now INT0=LOW */
/* don’t have to generate high_pulse */
}
if (wIrq>=8) outportb(A2_8259,0x20);
outportb(A1_8259,0x20);
}
INT0
INV0
INT_CHAN_0
(a) (b) (c) (d)
PIO-DA/PISO-DA Series User Manual (Ver.2.9, Feb. 2011, PMH-009-29 ) 13

2.3.4 Initial_low, active_high Interrupt source
If INT0 (8254 counter0 output) is an initial_low, active_high signal (depending on
the 8254 counter mode), the interrupt service routine should use INV0 to
invert/non-invert INT0 to generate a high_pulse in the following manner: (Refer
to DEMO4.C)
Initial setting:
outportb(wBase+0x2a,1); /* select the non-inverted INT0 */
now_int_state=0; /* initial state for INT0 */
void interrupt irq_service()
{
if (now_int_state==1) /* now INT0 is changed to LOW */(c)
{ /* --> INT_CHAN_0=!INT0=HIGH now */
COUNT_L++; /* find a LOW_pulse (INT0) */
If((inport(wBase+7)&1)==0)/* the INT0 is still fixed in LOW */
Æ{ /* need to generate a high_pulse */
outportb(wBase+0x2a,1); /* INV0 select the non-inverted input */(d)
/* INT_CHAN_0=INT0=LOW --> */
/* INT_CHAN_0 generate a high_pulse */
now_int_state=0; /* now INT0=LOW */
}
else now_int_state=1; /* now INT0=HIGH */
/* don’t have to generate high_pulse */
}
else /* now INT0 is changed to HIGH */(a)
{ /* --> INT_CHAN_0=INT0=HIGH now */
COUNT_H++; /* find a High_pulse (INT0) */
If((inport(wBase+7)&1)==1)/* the INT0 is still fixed in HIGH */
{ /* need to generate a high_pulse */
outportb(wBase+0x2a,0); /* INV0 select the inverted input */(b)
/* INT_CHAN_0=!INT0=LOW --> */
/* INT_CHAN_0 generate a high_pulse */
now_int_state=1; /* now INT0=HIGH */
}
else now_int_state=0; /* now INT0=LOW */
/* don’t have to generate high_pulse */
}
if (wIrq>=8) outportb(A2_8259,0x20);
outportb(A1_8259,0x20);
}
INT0
INV0
INT_CHAN_0
(a) (b) (c) (d)
PIO-DA/PISO-DA Series User Manual (Ver.2.9, Feb. 2011, PMH-009-29 ) 14

2.3.5 Multiple Interrupt Sources
Assume: INT0 is initial Low and active High,
INT1 is initial High and active Low
as below:
INT0 and INT1
are active at the
same time
INT1
INT0
INT1 returns to
normal
INT0 and INT1
return to normal
at the same time
INT1 is active
Refer to DEMO5.C for the source program. All of these falling-edge and
rising-edge can be detected using DEMO5.C.
Note:
! When the interrupt is active, the user program has to identify the active
signals. These signals may all be active at the same time, so the interrupt
service routine has to service all active signals at the same time.
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/* -------------------------------------------------------------- */
/* Note : 1.The hold_time of INT_CHAN_0 & INT_CHAN_1 must long */
/* enoug. */
/* 2.The ISR must read the interrupt status again to */
/* identify the active interrupt source. */
/* 3.The INT_CHAN_0 & INT_CHAN_1 can be active at the same */
/* time. */
/* -------------------------------------------------------------- */
void interrupt irq_service()
{
/* now ISR can not know which interrupt is active */
new_int_state=inportb(wBase+7)&0x03; /* read all interrupt */
/* signal state */
int_c=new_int_state^now_int_state; /* compare new_state to */
/* old_state */
if ((int_c&0x01)==1) /* INT_CHAN_0 is active */
{
if ((new_int_state&1)==0) /* INT0 change to low now */
{
INT0_L++;
}
else /* INT0 change to high now */
{
INT0_H++;
}
invert=invert^1; /* generate high_pulse */
}
if ((int_c&0x02)==2) /* INT_CHAN_1 is active */
{
if ((new_int_state&2)==0) /* INT1 change to low now */
{
INT1_L++;
}
else /* INT1 change to high now */
{
INT1_H++;
}
invert=invert^2; /* generate high_pulse */
}
now_int_state=new_int_state; /* update interrupt status */
outportb(wBase+0x2a,invert); /* generate a high pulse */
if (wIrq>=8) outportb(A2_8259,0x20);
outportb(A1_8259,0x20);
}
PIO-DA/PISO-DA Series User Manual (Ver.2.9, Feb. 2011, PMH-009-29 ) 16

2.4 D/I/O Block Diagram
The PISO-DA/PIO-DA series provides 16 digital input channels and 16 digital
output channels, and all signal levels are TTL compatible. The connection
diagram and block diagram are as follows:
Local Data Bus
D/I port
CON2
16 bits16 bits
D/O port
CON1
16 bits16 bits
The D/I Port can be connected to a DB-16P, which is a 16-channel isolated
digital input daughter board. The D/O Port can be connected to either a DB-16R
or a DB-24PR. The DB-16R is a 16 channels relay output board. The DB-24PR
is a 24 channels power relay output board.
PIO-DA/PISO-DA Series User Manual (Ver.2.9, Feb. 2011, PMH-009-29 ) 17

2.4.1 DI Port Architecture (CON2)
When the PC is powered up, all DI port (CON2) operation are disabled. The
enabled/disabled status of a DI port is controlled by the RESET\ signal. Refer to
Sec. 3.3.1 for more information about the RESET\ signal.
The RESET\ signal is in the Low-state Æall DI operations are disabled
The RESET\ signal is in the High-state Æall DI operations are enabled
D/I buffer CKT
Clock input
Buffer input
Data
RESET\
CON2
disable
PIO-DA/PISO-DA Series User Manual (Ver.2.9, Feb. 2011, PMH-009-29 ) 18

2.4.2 DO Port Architecture (CON1)
When the PC is powered up, the states of all DO channels are cleared low. The
RESET\ signal is used to clear the DO states. Refer to Sec. 3.3.1 for more
information about the RESET\ signal.
The RESET\ signal is in the Low-state Æall DO channels are cleared to
the low state
The block diagram of DO is as follows:
D/O buffer CKT
Clock input
input Latch
Data
RESET\
CON1
clear
PIO-DA/PISO-DA Series User Manual (Ver.2.9, Feb. 2011, PMH-009-29 ) 19

2.5 D/A Architecture
DA 3
DA 2
DA 1
DA 0D0
D13
DA 7
DA 6
DA 5
DA 4D0
D13
DA11
DA10
DA 9
DA 8D0
D13
DA15
DA14
DA13
DA12D0
D13
Buffered Data Bus (16 bits)
A0
A1
A0
A1
A0
A1
A0
A1
Current Output 0
Current Output 1
Current Output 2
Current Output 3
Current Output 4
Current Output 5
Current Output 6
Current Output 7
Current Output 8
Current Output 9
Current Output 10
Current Output 11
Current Output 12
Current Output 13
Current Output 14
Current Output 15
Voltage Output 15
Voltage Output 14
Voltage Output 13
Voltage Output 12
Voltage Output 11
Voltage Output 10
Voltage Output 9
Voltage Output 7
Voltage Output 6
Voltage Output 5
Voltage Output 4
Voltage Output 3
Voltage Output 2
Voltage Output 1
Voltage Output 0
Voltage Output 8
Amp
Amp
d0~d13
d14~d15
d0~d13
d14~d15
d0~d13
d14~d15
d0~d13
d14~d15
DA_0
DA_1
DA_2
DA_3
The PIO-DA4/8/16 provides 4/8/16 channels of double-buffered digital to analog
output and provides voltage output and current output simultaneously.
PIO-DA/PISO-DA Series User Manual (Ver.2.9, Feb. 2011, PMH-009-29 ) 20