Inrevium TB-FMCL-MIPI Instructions for use

TB-FMCL-MIPI Hardware User Manual
1
Rev.3.01
TB-FMCL-MIPI
Hardware User Manual
Rev.3.01

TB-FMCL-MIPI Hardware User Manual
2
Rev.3.01
Revision History
Version
Date
Description
Publisher
Rev.1.00
5/22/2015
Initial release
RH
Rev.1.10
5/25/2015
Reviewed and updated. General Release
RH
Rev.1.99
8/26/2015
Reviewed. Updated for PA-10087-0x Rev2.0. Submitted for
review.
ST
Rev. 2.00
9/14/2015
Updated. Released.
ST
Rev. 3.00
11/30/2015
Updated with new connector information
ST
Rev. 3.01
6/30/2016
Updated 2.Overview , 8.2 HS Mode Interface
Updated Figure.4-1, Figure.7-1, Figure.10-1
Amano

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Table of Contents
1. Related Documents andAccessories..........................................................................................8
2. Overview......................................................................................................................................8
3. Features.......................................................................................................................................9
4. Block Diagram ...........................................................................................................................10
5. External View of the Board........................................................................................................ 11
6. Board Specification....................................................................................................................13
7. Board Power System.................................................................................................................14
7.1. Power System Overview ..........................................................................................................14
7.2. MIPI User Power Rail...............................................................................................................14
7.3. LDO regulators......................................................................................................................... 15
7.4. LED Power Indicators...............................................................................................................15
8. MIPI PHY Device to FMC Interface...........................................................................................15
8.1. PHY Device Overview.............................................................................................................. 15
8.2. HS Mode Interface.................................................................................................................... 15
8.3. LP Mode Interface.................................................................................................................... 16
8.4. PHY Control.............................................................................................................................. 16
9. MIPI IO Signals..........................................................................................................................17
9.1. MIPI D-PHY Lanes................................................................................................................... 17
9.2. MIPI GPIO Signals ................................................................................................................... 17
9.3. MIPI I2C Bus ............................................................................................................................19
10. Connectors ................................................................................................................................19
10.1. LPC FMC Connector to Host Carrier Board.........................................................................19
10.2. MIPI Front Edge (I/O Window) Receptacles ........................................................................24
10.3. MIPI GPIO and I2C Debug Headers ....................................................................................26
11. FMC Facility I2C Bus.................................................................................................................27
11.1. FMC I2C EEPROM...............................................................................................................27
12. ESD Protection..........................................................................................................................27
13. Demonstration ...........................................................................................................................27
14. AppendixA: FMC I2C EEPROM...............................................................................................28
15. Appendix B: Headers, Factory Default, and Orientation........................................................... 31

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List of Figures
Figure 3-1 FMC LPC Connector Pinout per VITA 57.1 ...................................................................... 9
Figure 4-1 TB-FMCL-MIPI Block Diagram .......................................................................................10
Figure 5-1 Photo of TB-FMCL-MIPI (Side 1).....................................................................................11
Figure 5-2 Photo of TB-FMCL-MIPI (Side 2).................................................................................... 12
Figure 6-1 TB-FMCL-MIPI Board Dimensions (mm)........................................................................13
Figure 7-1 TB-FMCL-MIPI Power Structure..................................................................................... 14
Figure 7-2 VUSER Jumper Select Positions....................................................................................14
Figure 7-3 Power LEDs Identification...............................................................................................15
Figure 9-1 GPIO SIGNALS TO EACH MIPI PORT.......................................................................... 17
Figure 9-2 MIPI GPIO Voltage Select Options................................................................................. 18
Figure 10-1 Resistor for connection to TB-7V-2000T-LSI................................................................ 23
Figure 10-2 MIPI Connectors Faceplate View .................................................................................24
Figure 10-3 Axial removal vs zippering (picture courtesy of Samtec®)............................................24
Figure 10-4 MIPI Debug header side access views.........................................................................26
Figure 15-1 Default Jumper Positions and Header Orientation .......................................................31
List of Tables
Table 1-1 Accessories ........................................................................................................................ 8
Table 8-1 MIPI PHY Mode Settings.................................................................................................. 16
Table 9-1 GPIO Signals: Recommended sequencing...................................................................... 18
Table 10-1 LPC FMC Host Board Connector Pin Assignment.........................................................20
Table 10-2 MIPI D-PHY PORT A J5 (CSI)........................................................................................ 25
Table 10-3 MIPI D-PHY PORT B J16 (DSI) .....................................................................................26
Table 10-4 MIPI GPIO Debug Headers J15 and J18....................................................................... 27
Table 14-1 FMC I2C EEPROM Contents.........................................................................................28
Table 15-1 Default Header Explanation ...........................................................................................31

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Introduction
Thank you for purchasing the TB-FMCL-MIPI board. Before using the product, be sure to carefully
read this user manual and fully understand how to correctly use the product. First read through this
manual, and then always keep it handy.
SAFETY PRECAUTIONS Be sure to observe these precautions!
Observe the precautions listed below to prevent injuries to you or other personnel or damage to property.
Before using the product, read these safety precautions carefully to assure correct use.
These precautions contain serious safety instructions that must be observed.
After reading through this manual, be sure to always keep it handy.
The following conventions are used to indicate the possibility of injury/damage and classify precautions if
the product is handled incorrectly.
Indicates the high possibility of serious injury or death if the product is handled
incorrectly.
Indicates the possibility of serious injury or death if the product is handled
incorrectly.
Indicates the possibility of injury or physical damage in connection with houses or
household goods if the product is handled incorrectly.
The following graphical symbols are used to indicate and classify precautions in this manual.
(Examples)
Turn off the power switch.
Do not disassemble the product.
Do not attempt this.
Danger
Warning
Caution

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In the event of a failure, disconnect the power supply.
If the product is used as is, a fire or electric shock may occur. Disconnect the power supply
immediately and contact our sales personnel for repair.
If an unpleasant smell or smoking occurs, disconnect the power supply.
If the product is used as is, a fire or electric shock may occur. Disconnect the power supply
immediately. After verifying that there is no smoking, contact our sales personnel for repair.
Do not disassemble, repair or modify the product.
Otherwise, a fire or electric shock may occur due to a short circuit or heat generation. For
inspection, modification or repair, contact our sales personnel.
Do not touch a cooling fan.
As a cooling fan rotates at high speed, do not put your hand close to it. Otherwise, it may
cause injury to persons. Never touch a rotating cooling fan.
Do not place the product on unstable locations.
Otherwise, it may drop or fall, resulting in injury to persons or failure.
If the product is dropped or damaged, do not use it as is.
Otherwise, a fire or electric shock may occur.
Do not touch the product with a metallic object.
Otherwise, a fire or electric shock may occur.
Do not place the product in dusty or humid locations or where water may
splash.
Otherwise, a fire or electric shock may occur.
Do not get the product wet or touch it with a wet hand.
Otherwise, the product may break down or it may cause a fire, smoking or electric shock.
Do not touch a connector on the product (gold-plated portion).
Otherwise, the surface of a connector may be contaminated with sweat or skin oil, resulting
in contact failure of a connector or it may cause a malfunction, fire or electric shock due to
static electricity.
Warning

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Do not use or place the product in the following locations.
Humid and dusty locations
Airless locations such as closet or bookshelf
Locations which receive oily smoke or steam
Locations exposed to direct sunlight
Locations close to heating equipment
Closed inside of a car where the temperature becomes high
Static-prone locations
Locations close to water or chemicals
Otherwise, a fire, electric shock, accident or deformation may occur due to a short circuit or heat
generation.
Do not place heavy things on the product.
Otherwise, the product may be damaged.
■Disclaimer
This product is a MIPI interface for Xilinx FPGA evaluation boards. Tokyo Electron Device Limited
assumes no responsibility for any damages resulting from the use of this product for purposes other than
those stated.
Even if the product is used properly, Tokyo Electron Device Limited assumes no responsibility for any
damages caused by:
(1) Earthquake, thunder, natural disaster or fire resulting from the use beyond our responsibility, acts by
a third party or other accidents, the customer’s willful or accidental misuse, or use under other
abnormal conditions.
(2) Secondary impact arising from use of this product or its unusable state (business interruption or
others)
(3) Use of this product against the instructions given in this manual.
(4) Malfunctions due to connection to other devices.
Tokyo Electron Device Limited assumes no responsibility or liability for:
(1) Erasure or corruption of data arising from use of this product.
(2) Any consequences or other abnormalities arising from use of this product, or
(3) Damage of this product not due to our responsibility or failure due to modification.
This product has been developed by assuming its use for research, testing or evaluation. It is not
authorized for use in any system or application that requires high reliability.
Repair of this product is carried out by replacing it on a chargeable basis, not repairing the faulty devices.
However, non-chargeable replacement is offered for initial failure if such notification is received within
two weeks after delivery of the product.
The specification of this product is subject to change without prior notice.
The product is subject to discontinuation without prior notice.
Caution

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1. Related Documents and Accessories
All documents relating to this board can be downloaded from the TED Support Web at address
https://www.teldevice.co.jp/spweb/c0201s
Table 1-1 Accessories
Description
Manufacturer
Quantity
Spacer, 10mm, M2.6
Hirosugi
2
Spacer, 25mm, M2.6
Hirosugi
2
Screw, 6mm, M2.6 w/ washers
Hirosugi
6
2. Overview
The TB-FMCL-MIPI is an ANSI/VITA 57.1 compatible FPGA Mezzanine Card (FMC) with a
Low-Pin-Count (LPC) connector that presents two separate 4-lane MIPI ports to a pair of 40-pin
sockets located in the FMC I/O Window. Each side utilizes a PHY device designed to be
compatible with the MIPI D-PHY Specification 1.00.00, (September 2009) meeting the nominal
data throughput of 1 Gbit/s per lane.
The TB-FMCL-MIPI does not utilize any of the high-speed serial DPx data links and GBTCLKs
provided in the FMC standard, so present data speed is limited to the capabilities of HR and HP
SelectIO of Xilinx FPGAs.
The TB-FMCL-MIPI is produced as a CSI-DSI combo card that supports 4-lane MIPI input and
4-lane MIPI output on a single FMC LPC module.
Note: Through factory configuration (population options), the ports on the circuit board can support
CSI/DSI (default), CSI x2 (custom build required), or DSI x2 (custom build required). Please
contact a sales representative regarding custom board versions.

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3. Features
MIPI CSI-2 Receiver PHY Device Meticom MC20901
MIPI DSI Transmitter PHY Device Meticom MC20902
FMC LPC Main Connector Samtec ASP-134604-01
MIPI Connectors Samtec LSHM-120-01-F-DH-A-N-K-TR
Four MIPI GPIO ports direction individually selectable
MIPI I2C port Dedicated I2C port per MIPI connector
MIPI GPIO and I2C Voltage Individually jumper selected: VADJ, VUSER, 2.5V, 3.3V
Selectable MIPI VUSER up to 0.8A Teas Instruments TPS62150 Buck converter for 1.5/1.8/2.5/3.3V.
One VUSER services both ports.
FPGA VADJ GPIO Signal Level 1.65V through 3.3V using voltage level translators
12V power up to 200mA per MIPI PTC self-resetting fuse protected Cooper PTS120615V050
LDO regulators for PHYs Texas Instruments TPS74701 generating local 2.5V and 1.2V
FMC Configuration EEPROM Micron M24C02 2Kb I2C EEPROM with GA0/1 address selection
Voltage presence LED indicators One green LED for each on-board voltage rail
An excerpt from ANSI/VITA 57.1 of the FMC LPC connector physical pin layout is provided below. The
TB-FMCL-MIPI implements only the LPC sub-portion as defined for rows C, D, G, and H. All other rows
apply to the FMC HPC implementation and are left open-circuit when the TB-FMCL-MIPI is installed in
an FMC HPC receptacle. Pin signal names shown are per VITA 57.1 definition.
Figure 3-1 FMC LPC Connector Pinout per VITA 57.1

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4. Block Diagram
Figure 4-1 shows the TB-FMCL-MIPI block diagram.
FMC Low Pin Count Connector ASP-134604-01
SN74AVC4T245 level translators
use VADJ for the FMC connector
side and 2.5V for the bridge side.
MC20901 5
Channel
MIPI CSI-2
Bridge
M24C02
EEPROM
3P3VAUX
GA0
GA1
SDA
SCL
TDI
TDO
GPIO-1
BTA
GPIO-0
PINSWAP
SN74AVC4T245
SN74AVC4T245
SN74AVC4T245
HS-E_P/N
MC20902 5
Channel
MIPI DSI
Bridge
HS-D_P/N
HS-C_P/N
HS-B_P/N
HS-A_P/N
LP-E_P
LP-D_P
LP-C_P
LP-B_N
LP-A_P
GPIO-1
BTA
GPIO-0
PINSWAP
SN74AVC4T245
SN74AVC4T245
SN74AVC4T245
LP-B_P
LP-C_N
LP-D_N
LP-E_N
LP-A_N
SN74AVC4T245
Section 1
Section 2
SN74AVC2T245
SN74AVC2T245
AUX_nOE1-4
12.0V VUSER 1.2V 2.5V
TPS74701 LDO TPS74701 LDO
VUSER jumper selectable for
1.5V, 1.8V, 2.5V, or 3.3V
12V0
VUSER
DSI MIPI
PORT B
CSI-2 MIPI
PORT A
SAMTEC LSHM-120-01-F-DH-A-N-K-TR
SAMTEC LSHM-120-01-F-DH-A-N-K-TR
TPS62150
SWITCHER
3.3V
I2C SDA
I2C SCL
AUX_nOE5-8
MAX. 800mA Max. Draw 30mA Max. Draw 60mA
LP-D_P
LP-C_P
LP-B_N
LP-B_P
LP-C_N
LP-D_N
HS-E_P/N
HS-D_P/N
HS-C_P/N
HS-B_P/N
HS-A_P/N
D-PHY-A_P/N
D-PHY-B_P/N
D-PHY-C_P/N
D-PHY-D_P/N
D-PHY-E_P/N
D-PHY-A_P/N
D-PHY-B_P/N
D-PHY-C_P/N
D-PHY-D_P/N
D-PHY-E_P/N
1.2V
2.5V
1.2V
2.5V
12.0V
3.3V
VADJ
2.5V & 1.2V
STATUS LEDs
I2C SDA
I2C SCL
All CSI-2 and DSI MIPI Port SLVS,
control, and I2C signals have ESD
protection devices (not shown).
Four optional control bits set by jumpers
to VADJ, 2.5V, 3.3V, or VUSER levels
VADJ = 1.8V or 2.5V
Transition boards or cables are used between the
Samtec LSHM connectors and the camera or display.
FXMA2102 I2C LEVEL
TRANSLATOR
I2C Voltage set by jumpers
to 1.8V, 2.5V, 3.3V, or
VUSER levels
FXMA2102 I2C LEVEL
TRANSLATOR
I2C Voltage set by jumpers
to VADJ, 2.5V, 3.3V, or
VUSER levels
Four optional control bits set by jumpers
to VADJ, 2.5V, 3.3V, or VUSER levels
VUSER
3.3V_AUX
DIR
LP-E_P
LP-E_N
SN74AVC4T245
Section 1
Section 2
DIR
10-pin header for
DSI power, I2C and
optional control bits
10-pin header for
CSI power, I2C and
optional control bits
LP-A_N
LP-A_P
John Curnow 2014/08/06
SN74AVC2T245
IO
EXPANDER
SN74AVC2T245
U10
U5
3V3
12V0
VUSER
3V3
Figure 4-1 TB-FMCL-MIPI Block Diagram

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5. External View of the Board
MIPI PORTB
GPIO DEBUG HDR J18
MIPI PORTB
MIPI AUX IO VOLTAGE
SELECTOR J19
MIPI PORTB
DSI CONNECTOR J16
MIPI PORTA
CSI CONNECTOR J5
MIPI PORTA
GPIO DEBUG
HDR J15
FMC LPC
CONNECTOR J1
MIPI PORTA/PORTB
PIN SWAP HDR J3
MIPI PORTA
MIPI AUX IO VOLTAGE
SELECTOR J12 MIPI PORTB
I2C VOLTAGE
SELECTOR J17
VUSER VOLTAGE
SELECTOR J9
MIPI PORTA
I2C VOLTAGE
SELECTOR J6
Figure 5-1 Photo of TB-FMCL-MIPI (Side 1)

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Figure 5-2 Photo of TB-FMCL-MIPI (Side 2)

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6. Board Specification
The following shows the TB-FMCL-MIPI board physical specifications.
External Dimensions 76.50 mm L x 69.00 mm W –Dimensions/features per VITA57.1
Number of Layers 10 layers
Board Thickness 1.6 mm
Material Megtron 4
FMC LPC Connector Samtec ASP-134604-01
MIPI Connectors Samtec LSHM-120-01-F-DH-A-N-K-TR
Note: Refer to samtec.com for mating connector for
C
L
63.00
66.00
10.90
65.60
54.60
2.20
43.04 61.30
18.54
3.00
57.90
59.05
58.30
Ø2.7, 6plcs
3.00
0.80
C
L
Figure 6-1 TB-FMCL-MIPI Board Dimensions (mm)
Notes:
Board outline features conform to VITA57.1 air-cooled commercial grade single-width modules
MIPI connectors are pitched at 24.50mm center-to-center.
CSI position is defined as MIPI Port A, DSI position is defined as MIPI Port B
Board component side is defined in VITA 57.1 as Side 1 and faces the host carrier card when installed
Board solder side is defined as Side 2 and is probing and visually accessible when the card is installed

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7. Board Power System
7.1. Power System Overview
Figure 7-1 shows the TB-FMCL-MIPI power supply structure. The card uses the 12 Volt, the 3.3 Volt, the
3.3V AUX, and the VADJ rails supplied on the FMC connector from the carrier card. There is one 1.2V
LDO regulator to generate the PHY core voltage (MC20901/MC20902), one 2.5V LDO regulator for the
PHY IOs, and one switching regulator to generate the MIPI VUSER voltage rail. VADJ can range from
1.65V to 3.3V and is used mainly for the GPIO and I2C voltage translators. There is no control of power
sequencing. The 12V and 3.3V rails are protected by 0.5Amp PTC resettable fuses. If either fuse trips
due to an overcurrent fault, remove power to the card and wait a minute for the fuse to cool. Remove the
condition causing the excess current and apply power. If the fuse trips again, remove power, wait for the
fuse to cool, remove the card from the carrier, and contact our sales personnel for repair.
FMC LPC
CONNECTOR
12V 0.5A PTC
3.3V 0.5A PTC
3.3V AUX EEPROM
I2C I/O
EXPANDER
VADJ
Adjustable
Buck Switching
Regulator
GPIO
LEVEL
SHIFTERS
I2C
LEVEL
SHIFTERS
GPIO
LEVEL
SHIFTERS
VADJ I2C
LEVEL
SHIFTERS VUSER
3V3
2V5
VADJ
3V3
2V5
VADJ
VUSER
VUSER
LDO
Regulator 2V5
LDO
Regulator 1V2
1V5
1V8
2V5
3V3
VUSER
SELECTION
MIPI PORT 1
IO VOLTAGE
SELECTION
MIPI PORT A
MIPI PORT B
12V0
3V3_AUX
MIPI PORT 2
IO VOLTAGE
SELECTION
3V3
Figure 7-1 TB-FMCL-MIPI Power Structure
7.2. MIPI User Power Rail
The MIPI User power source connector power is supplied from a Texas Instruments TPS62150 switching
regulator. It provides four user selectable output voltages from 1.5V to 3.3V at a total current of 800mA,
or 400mA per MIPI port. The VUSER voltage does not necessarily need to reflect the MIPI IO logic
levels, however, it is available as one of the level shifter reference options. The VUSER selection
jumper is mapped as follows:
1
3.3V
2
3 4
5 6
7 8
1
2.5V
2
3 4
5 6
7 8
1
1.8V
2
3 4
5 6
7 8
1
1.5V
2
3 4
5 6
7 8
Figure 7-2 VUSER Jumper Select Positions
Note: Positioning more than one shunt, or positioning a shunt in a position not described above could
result in permanent damage to the board.

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7.3. LDO regulators
There are two Texas Instruments TPS74701 LDO regulators that are used to support the MIPI PHY
devices. The 1.2V regulator will need to supply up to 30mA to two PHY devices core supply in full
operation, and the 2.5V regulator will supply up to 60mA to two PHY devices IO supply in full operation.
In addition to the PHYs, the 2.5V regulator may also see an additional 72mA maximum loading from all
MIPI GPIO and 4.5mA maximum loading from MIPI I2C pullups if 2.5V is selected as the IO voltage
option for all the MIPI GPIO and I2C ports. Note that the TPS74701 requires a bias voltage of 1.3V
greater than the output voltage, thus the 2.5V regulator requires a bias input of at least 3.8V. Since
there is no 5V rail available, the bias input is generated by a zener diode from the FMC 12V power. The
zener regulation system draws 4.6mA (typ) to account for Bias current variation while still providing
sufficient reverse zener current to establish a stable voltage of approximately 4.3V.
The regulators each provide a Power-Good output; these open-collector outputs are tied together and
used as the control for the shared 2.5V and 1.2V LED indicator D4.
7.4. LED Power Indicators
A series of six green LEDs are located in a row on Side 2 (solder side) so they are visible when the card
is installed on an FMC carrier. The LEDs indicate the presence of the various supply rails, and under
normal conditions, all six LEDs should be lit when the card is powered-up. The following diagram of the
solder side displays the row of LEDs and their meaning:
12V0
3V3
3V3_VAUX
2V5 & 1V2
VADJ
VUSER
Figure 7-3 Power LEDs Identification
8. MIPI PHY Device to FMC Interface
8.1. PHY Device Overview
The PHY devices are produced by Meticom GmbH in both Receiver (MC20901) and Transmitter
(MC20902) versions. The devices draw very little power in operation and do not require any special
cooling considerations. The Meticom chip pinouts are designed to be mirrored between the Transmitter
(DSI) device, and Receiver (CSI-2) device. This permits a direct top-bottom PCB placement of the two
types while maintaining a fixed order and polarity of the MIPI differential pairs running to the connector.
This avoids signal integrity measures that would otherwise be needed in layout design to support the
dual CSI-2 or dual DSI assembly options.
8.2. HS Mode Interface
The FMC HS interface to the PHY devices consists of five differential pairs per MIPI port, totaling 10 IO
pins each. These signals are termed by Meticom as LVDS HS(0-4) and are the high-speed data
connection that carries MIPI payload data at up to Gb/s speeds. Typically, four lanes are assigned as

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data and one lane is assigned as clock. The HS mode data lanes operate in DDR mode with respect to
the clock, with one data bit transferred per clock transition. The Receiver (CSI-2) converts five low-swing,
high-speed differential signals (SLVS per Meticom’s terminology) to five LVDS links (4-data, 1-clock) sent
to the FMC LPC connector. The Transmitter (DSI) converts five LVDS links from the FMC LPC connector
to five SLVS links. Refer to the respective device datasheet for more details regarding electrical
characteristics and performance.
8.3. LP Mode Interface
Each PHY device also presents an alternate set of differential IOs, termed the CMOS LP(0-4). These
pins operate at LVCMOS level determined by VADJ, at up to 10Mb/s, and are active during Low-Power
(LP) mode transactions defined in the MIPI Specification. Low-power mode additionally features Bus
TurnAround (BTA) where the data direction on one of the CMOS LP links (Lane 0) is reversed to provide
host system read/write access to status and control registers from either a DSI (display) or CSI-2
(camera) MIPI peripheral. This facility supports minimized peripheral connectivity where additional
GPIOs, I2C or other side-band control links are absent.
8.4. PHY Control
Each PHY device presents a group of four control inputs to the host which govern the operation of the
MIPI link. Two pins, called GPIO-1 and GPIO-2, set the operating state of the PHY. Another input pin,
BTA, enables the Bus Turn Around (in LP) mode and is used for host access to status and control
registers within the peripheral device. The final input pin, called PINSWAP, is a three-mode input which
controls the differential polarity of all five MIPI lanes simultaneously. The following table outlines the
operating modes of the PHY device as selected by the input settings:
Table 8-1 MIPI PHY Mode Settings
Input Pins
Mode
GPIO-1
GPIO-0
BTA
PINSWAP
0
0
X
X
IC Power Down
0
1
X
X
SLVS-LVDS conversion unconditionally active
1
0
0
X
MIPI D-PHY mode, BTA not Active during LP
1
0
1
X
MIPI D-PHY mode, BTAActive on PHY channel E during LP
0
1
0
X
*MIPI D-PHY mode, BTA not Active during LP
0
1
1
X
*MIPI D-PHY mode, BTAActive on PHY channel Aduring LP
X
X
X
0
No HS Pin polarity Swaps
X
X
0
1
HS Pin polarity swap each lane at the MIPI port
X
X
1
1
No HS Pin polarity Swaps
X
X
X
**Floating
HS Pin polarity swap each lane at the LVDS HS port
* BTA on Channel A/ MIPI lane 4 is not supported on the TB-FMCL-MIPI card. These settings should not
be used.
** This option is available by removing the appropriate shorting jumper from J3: pins 1-2 for CSI, pins 3-4
for DSI. Removed jumpers may be parked on unconnected pins 5-6 and 7-8. The user must ensure
that the jumpers are installed across pins 1-2 and 3-4 to select No Pin Swap mode.

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9. MIPI IO Signals
9.1. MIPI D-PHY Lanes
Each MIPI connector, whether input (CSI-2) or output (DSI), provides five differential pairs that are
designed to interface to 100-ohm differential wiring to the MIPI peripheral. The differential pairs are
assigned per Samtec’s recommendations for the LSHM series where each pair occupies adjacent pins
bounded on both sides by GND pins. For signal integrity reasons, in the 20-pin by 2-row connector pin
matrix, the high-speed differential lanes occupy the inside row, or “short” path (ROW 1), of the connector.
All five lanes from a connector to PHY device IO pads are delay matched to 10ps to minimize the PCB
impact on signal/clock timing relationship. Both the CSI and DSI port traces are approximately 31mm in
length, measured from the Meticom PHY pins to the LSHM connector.
9.2. MIPI GPIO Signals
Each MIPI connector is supplied with four GPIO signals that are supplied from SelectIO pins on the FMC
connector, as per the following diagram:
GA1
3.3V AUX
MIPI PORTA
MIPI PORTB
GA0 A0
A1
A2
3.3V AUX
ADDR: 01111xx
SDA
SCL
BI-DIR
LEVEL
SHIFTER
VADJ VADJ VADJ
DIR1 DIR2
A1
A2 B1 B2
OEn
BI-DIR
LEVEL
SHIFTER
VADJ
DIR1 DIR2
A1
A2 B1 B2
OEn
DIR_MIPI_AUXIO_LPC3
DIR_MIPI_AUXIO_LPC4
MIPI_AUXIO_LPC1
MIPI_AUXIO_LPC2
MIPI_AUXIO_nOE1-4
MIPI_AUXIO_LPC3
MIPI_AUXIO_LPC4
MIPI_AUXIO1
MIPI_AUXIO2
MIPI_AUXIO3
MIPI_AUXIO4
I2C I/O
EXPANDER
DIR_MIPI_AUXIO_LPC3
DIR_MIPI_AUXIO_LPC4
DIR_MIPI_AUXIO_LPC5
DIR_MIPI_AUXIO_LPC6
DIR_MIPI_AUXIO_LPC7
DIR_MIPI_AUXIO_LPC8
DIR_MIPI_AUXIO_LPC1
DIR_MIPI_AUXIO_LPC2
BI-DIR
LEVEL
SHIFTER
VADJ
A1
A2 B1 B2
OEn
BI-DIR
LEVEL
SHIFTER
VADJ
DIR1 DIR2
A1
A2 B1 B2
OEn
DIR_MIPI_AUXIO_LPC7
DIR_MIPI_AUXIO_LPC8
MIPI_AUXIO_LPC5
MIPI_AUXIO_LPC6
MIPI_AUXIO_nOE5-8
MIPI_AUXIO_LPC7
MIPI_AUXIO_LPC8
MIPI_AUXIO5
MIPI_AUXIO6
MIPI_AUXIO7
MIPI_AUXIO8
DIR1 DIR2
DIR_MIPI_AUXIO_LPC5
DIR_MIPI_AUXIO_LPC6
VUSER
3V3
2V5
VADJ
VUSER
3V3
2V5
VADJ
Figure 9-1 GPIO SIGNALS TO EACH MIPI PORT
The VADJ IO voltage domain of the FMC is level shifted to the user selected MIPI IO voltage domain
using Texas Instruments SN74AVC2T245 bi-directional dual-voltage transceivers. These devices can
operate to voltages as low as 1.2V, allowing the MIPI GPIO signals to support VADJ or VUSER down to
1.5V (actual minimum VADJ is 1.65V due to I2C translator limitations). Two FPGA pins on the FMC
connector control the output enable (OEn) of the level shifters (OEn=1 results in Hi-Z on each side of
translator). Each MIPI connector GPIO group can have its MIPI IO voltage selected from four options as

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shown:
1
3.3V
2
3 4
5 6
7 8
1
2.5V
2
3 4
5 6
7 8
1
VADJ
2
3 4
5 6
7 8
1
VUSER
2
3 4
5 6
7 8
Figure 9-2 MIPI GPIO Voltage Select Options
Each GPIO group has a header for voltage selection; MIPI PORT A (CSI-2) MIPI_AUXIO_(1-4) uses
header J12, and MIPI PORT B (DSI) MIPI_AUXIO_(5-8) uses header J19.
The direction of each of the eight GPIOs is determined by the Carrier Card FPGA via the MIPI FMC’s I2C
I/O Expander (Texas Instruments, PCA9534A). The I/O Expander is powered by 3V3_AUX and is
located on the dedicated FMC I2C bus at address: 01111xx (xx is determined by the FMC slot signals
GA[0:1]; GA0 →A1, GA1 →A0). The I/O Expander’s GPIOs default to input upon power up. Once
configured, when direction control pin is “high”, the GPIOs are outputs driven to the MIPI Port connector.
When the direction control pin is “low”, the GPIOs are inputs driven from the MIPI Port connector.
To help avoid contention, the recommended configuration sequence for the I/O Expander and Buffers
are as follows:
Table 9-1 GPIO Signals: Recommended sequencing
Stage
Action
Signals
T0
Power-Up, FPGA Configuration
MIPI_AUXIO_nOE1-4 = 1
MIPI_AUXIO_nOE5-8 = 1
DIR_MIPI_AUXIO_LPC[1:8]= X (don’t Care)
MIPI_AUXIO_LPC[1:8] = X (don’t care)
Notes:
1. Both OE signals have resistor pull-ups to VADJ
2. Direction control signals have resistor pull-downs
T1
Program I/O Expander
MIPI_AUXIO_nOE1-4 = 1
MIPI_AUXIO_nOE5-8 = 1
DIR_MIPI_AUXIO_LPC[1:8]= As required
T2
Start GPIO Signals
MIPI_AUXIO_nOE1-4 = 1
MIPI_AUXIO_nOE5-8 = 1
DIR_MIPI_AUXIO_LPC[1:8]= As required
MIPI_AUXIO_LPC[1:8] = As required
T3
Enable Level Translators
MIPI_AUXIO_nOE1-4 = 0
MIPI_AUXIO_nOE5-8 = 0
DIR_MIPI_AUXIO_LPC[1:8]= As required
MIPI_AUXIO_LPC[1:8] = As required

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9.3. MIPI I2C Bus
Each MIPI Port connector provides a standard I2C bus to any peripheral device that may be able to use
it (typically devices that do not utilize the MIPI BTA capability). Each connector receives its own set of
SelectIO pin assignments on the FMC connector, thus there is no I2C bus sharing on either MIPI port,
providing complete flexibility for MIPI device slave address assignment. The I2C bus of each port is IO
Voltage level selectable through headers J6 for the CSI port (MIPI Port A) and header J17 for the DSI
port (MIPI Port B). The jumper selection positions are identical to that of the GPIO selector headers
J12 and J19, detailed earlier in Figure 9-2. Note that the I2C translation buffer only supports voltages
down to 1.65V; the user must not to select a lower VUSER or VADJ voltage if the MIPI I2C is used.
However, if the I2C is not used, it is not harmful for VUSER or VADJ, if selected, to be below 1.65V as
long as the I2C port is not expected to operate.
10. Connectors
There are three main connectors on the TB-FMCL-MIPI card. One LPC FMC connector (J1) provides the
FMC host carrier interconnection, and the other two connectors (J5 and J16) are two right-angle MIPI
port sockets facing off the front edge (I/O window) of the FMC module. Additionally, for debug and
development access, two right angle headers, J15, and J18, located behind the MIPI port sockets and
facing out to the board side edges, provide access to the MIPI GPIO and I2C signals as well as VUSER
and 12V0.
10.1. LPC FMC Connector to Host Carrier Board
The LPC FMC connector (J1) used to mate to the Host Carrier Board is a Samtec ASP-134604-01. Only
the 160-pin LPC positions are populated, however, the module may be installed on a supported HPC
receptacle.
Table 10-1 shows the FMC connector pin assignment. In this table the C2M direction means
Carrier-to-Mezzanine, representing an input to the FMC. The M2C direction means Mezzanine-to-Carrier,
representing an output from the FMC. BIDIR identifies those signals whose direction can be application
selected. Signal Direction and Description in brackets represent MIPI port option assembly. Default
assembly shown is CSI-DSI (MIPI 1 –MIPI 2). Unused LAxx, DPx, and GBTCLKx signals are not
included in the table and are left unconnected. Power and GND pins are also not included; refer to
Figure 3-1 for power and ground pin connections.
FPGA IO allocations to FMC IO pins are platform specific and not included in the following table.
Please refer to the user manual of the particular FMC carrier host FPGA platform being used for the
mapping of FMC IOs to FPGA banks and pins.

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Table 10-1 LPC FMC Host Board Connector Pin Assignment
J1
Pin
Schematic Signal
Name
VITA 57.1 Pin
Name
Direction
Type
Description
MIPI HS Signals
C18
M2C_LVDS_HS0_P
LA14_P
M2C
LVDS
MIPI CSI PHY HS
Channel E
C19
M2C_LVDS_HS0_N
LA14_N
H13
M2C_LVDS_HS1_P
LA07_P
M2C
LVDS
MIPI CSI PHY HS
Channel D
H14
M2C_LVDS_HS1_N
LA07_N
C14
M2C_LVDS_HS2_P
LA10_P
M2C
LVDS
MIPI CSI PHY HS
Channel C
C15
M2C_LVDS_HS2_N
LA10_N
H16
M2C_LVDS_HS3_P
LA11_P
M2C
LVDS
MIPI CSI PHY HS
Channel B
H17
M2C_LVDS_HS3_N
LA11_N
G6
**M2C_LVDS_HS4_P
LA00_CC_P
M2C
LVDS
MIPI CSI PHY HS
Channel A
G7
**M2C_LVDS_HS4_N
LA00_CC_N
G24
C2M_LVDS_HS0_P
LA22_P
C2M
LVDS
MIPI DSI PHY HS
Channel E
G25
C2M_LVDS_HS0_N
LA22_N
H22
C2M_LVDS_HS1_P
LA19_P
C2M
LVDS
MIPI DSI PHY HS
Channel D
H23
C2M_LVDS_HS1_N
LA19_N
G21
C2M_LVDS_HS2_P
LA20_P
C2M
LVDS
MIPI DSI PHY HS
Channel C
G22
C2M_LVDS_HS2_N
LA20_N
H25
C2M_LVDS_HS3_P
LA21_P
C2M
LVDS
MIPI DSI PHY HS
Channel B
H26
C2M_LVDS_HS3_N
LA21_N
D20
**C2M_LVDS_HS4_P
LA17_CC_P
C2M
LVDS
MIPI DSI PHY HS
Channel A
D21
**C2M_LVDS_HS4_N
LA17_CC_N
H4
CLK0_M2C_P
CLK0_M2C_P
M2C
LVDS
Optional MIPI CSI PHY
HS
Channel A
H5
CLK0_M2C_N
CLK0_M2C_N
G2
CLK1_M2C_P
CLK1_M2C_P
C2M
LVDS
Optional MIPI DSI PHY
HS
Channel A
G3
CLK1_M2C_N
CLK1_M2C_N
** inrevium strap option: route HS4 pairs to alternate clock FMC CLKx_M2C pins instead of LAxx_CC pins
MIPI LP Signals
G18
M2C_CMOS_BTA_LP0_P
LA16_P
M2C/C2M
LVCMOS
(VADJ)
MIPI CSI PHY LP
Channel E (BTA)
G19
M2C_CMOS_BTA_LP0_N
LA16_N
G15
M2C_CMOS_LP1_P
LA12_P
M2C
LVCMOS
(VADJ)
MIPI CSI PHY LP
Channel D
G16
M2C_CMOS_LP1_N
LA12_N
G12
M2C_CMOS_LP2_P
LA08_P
M2C
LVCMOS
(VADJ)
MIPI CSI PHY LP
Channel C
G13
M2C_CMOS_LP2_N
LA08_N
G9
M2C_CMOS_LP3_P
LA03_P
M2C
LVCMOS
(VADJ)
MIPI CSI PHY LP
Channel B
G10
M2C_CMOS_LP3_N
LA03_N
H7
M2C_CMOS_LP4_P
LA02_P
M2C
LVCMOS
(VADJ)
MIPI CSI PHY LP
Channel A
H8
M2C_CMOS_LP4_N
LA02_N
D23
C2M_CMOS_BTA_LP0_P
LA23_P
C2M/M2C
LVCMOS
(VADJ)
MIPI DSI PHY LP
Channel E (BTA)
D24
C2M_CMOS_BTA_LP0_N
LA23_N