Intel Arria 10 SDI II User manual

Intel® Arria® 10 SDI II IP Core
Design Example User Guide
Updated for Intel® Quartus® Prime Design Suite: 17.0
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Contents
1 SDI II Design Example Quick Start Guide........................................................................ 3
1.1 Directory Structure................................................................................................. 3
1.2 Hardware and Software Requirements....................................................................... 6
1.3 Generating the Design.............................................................................................7
1.4 Simulating the Design............................................................................................. 8
1.5 Compiling and Testing the Design ............................................................................ 8
1.5.1 Connection and Settings Guidelines...............................................................9
1.5.2 Design Limitations for Serial Loopback Design...............................................11
2 SDI II Design Example Detailed Description.................................................................. 13
2.1 Parallel Loopback Design Examples......................................................................... 14
2.2 Serial Loopback Design Examples............................................................................18
2.3 Design Components.............................................................................................. 22
2.4 Clocking Scheme Signals....................................................................................... 25
2.5 Interface Signals...................................................................................................28
2.6 Video Pattern Generator Parameters........................................................................39
2.7 Hardware Setup....................................................................................................40
2.8 Simulation Testbench............................................................................................ 41
A SDI II IP Core Design Example User Guide Archives......................................................44
B Revision History for SDI II IP Core Design Example User Guide................................... 45
Contents
Intel® Arria® 10 SDI II IP Core Design Example User Guide
2

1 SDI II Design Example Quick Start Guide
The SDI II IP core design examples for Intel® Arria® 10 devices feature a simulating
testbench and a hardware design that supports compilation and hardware testing.
When you generate a design example, the parameter editor automatically creates the
files necessary to simulate, compile, and test the design in hardware.
Figure 1. Development Steps
Design
Example
Generation
Compilation
(Simulator)
Functional
Simulation
Compilation
(Quartus Prime)
Hardware
Testing
Related Links
•SDI II IP Core User Guide
•SDI II IP Core Design Example User Guide Archives on page 44
Provides a list of user guides for previous versions of the SDI II IP core design
examples.
1.1 Directory Structure
The directories contain the generated files for the design examples.
UG-20076 | 2017.05.08
Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus
and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other
countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2008
Registered

Figure 2. Directory Structure for the Design Examples
<Design Example>
db/qdb
quartus
sdi_ii_a10_demo.qpf
sdi_ii_a10_demo.qsf
rtl
sdi_ii_a10_demo.v
sdi_ii_a10_demo.sdc
edge_detector.sv
clock_heartbeat.sv
a10_reconfig_arbiter.sv (optional)
vid_pattgen (for serial loopback design)
rx (for simplex mode design)
tx (for simplex mode design)
du (for duplex mode design)
loopback (for parallel loopback design)
<clk_ctrl.qsys generated>(optional)
<pll_148 qsys generated> (optional)
clk_ctrl.qsys (optional)
pll_148.qsys (optional)
aldec
cadence
mentor
simulation
synopsys
testbench
tpg.ctrl.tcl (optional)
hwtest
(for serial loopback design)
Table 1. Other Generated Files in RTL Folder
Folders Files
vid_pattgen /sdi_ii_colorbar_gen.v
/sdi_ii_ed_vid_pattgen.v
/sdi_ii_makeframe.v
/sdi_ii_patho_gen.v
/jtag.sdc
/pattgen_ctrl.qsys
<qsys generated folder>
loopback /loopback_top.v
/fifo/sdi_ii_ed_loopback.sdc
/fifo/sdi_ii_ed_loopback.v
/pfd/clock_crossing.v (optional)
/pfd/pfd.sdc (optional)
/pfd/pfd.v (optional)
/reclock/sdi_reclock.v (optional)
/reclock/pid_controller.v (optional)
du /du_top.v
/sdi_ii_rx_rcfg_a10.sv (optional)
/rcfg_sdi_cdr.sv (optional)
continued...
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Folders Files
/rcfg_pll_sw.sv (optional)
/rcfg_refclk_sw.sv (optional)
/sdi_ii_tx_rcfg_a10.sv (optional)
/sdi_du_sys.qsys
•/sdi_rx_phy.qsys (Quartus Prime Standard Edition)
•/sdi_rx_phy.ip (Quartus Prime Pro Edition)
•/tx_pll.qsys (Quartus Prime Standard Edition)
•/tx_pll.ip (Quartus Prime Pro Edition)
•/tx_pll_alt.qsys (Quartus Prime Standard Edition)
•/tx_pll_alt.ip (Quartus Prime Pro Edition)
(optional)
<qsys generated folder>
rx /rx_top.v
/sdi_ii_rx_rcfg_a10.sv (optional)
/rcfg_sdi_cdr.sv (optional)
/sdi_rx_sys.qsys
<qsys generated folder>
tx /tx_top.v
/rcfg_pll_sw.sv (optional)
/rcfg_refclk_sw.sv (optional)
/sdi_ii_tx_rcfg_a10.sv (optional)
/sdi_tx_sys.qsys
•/tx_pll.qsys (Quartus Prime Standard Edition)
•/tx_pll.ip (Quartus Prime Pro Edition)
•/tx_pll_alt.qsys (Quartus Prime Standard Edition)
•/tx_pll_alt.ip (Quartus Prime Pro Edition)
(optional)
<qsys generated folder>
Table 2. Other Generated Files in Simulation Folder
Folders Files
aldec /aldec.do
/rivierapro_setup.tcl
cadence /cds.lib
/hdl.var
/ncsim.sh
/ncsim_setup.sh
continued...
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Folders Files
<cds_libs folder>
mentor /mentor.do
/msim_setup.tcl
synopsys /vcs/filelist.f
/vcs/vcs_setup.sh
/vcs/vcs_sim.sh
/vcsmx/synopsys_sim_setup
/vcsmx/vcsmx_setup.sh
/vcsmx/vcsmx_sim.sh
testbench tb_top.v
rx_checker/sdi_ii_tb_rx_checker.v
rx_checker/tb_data_compare.v
rx_checker/tb_dual_link_sync.v
rx_checker/tb_fifo_line_test.v
rx_checker/tb_frame_locked_test.sv
rx_checker/tb_rxsample_test.v
rx_checker/tb_trs_locked_test.sv
rx_checker/tb_txpll_test.sv
rx_checker/tb_vpid_check.v
tb_control/sdi_ii_tb_control.v
tb_control/tb_clk_rst.v
tb_control/tb_data_delay.v
tb_control/tb_serial_delay.sv
tb_control/tb_tasks.v
tb_checker/sdi_ii_tb_tx_checker.v
tb_checker/tb_serial_check_counter.v
tb_checker/tb_serial_descrambler.v
tb_checker/tb_tx_clkout_check.v
vid_pattgen/sdi_ii_colorbar_gen.v
vid_pattgen/sdi_ii_ed_vid_pattgen.v
vid_pattgen/sdi_ii_makeframe.v
vid_pattgen/sdi_ii_patho_gen.v
1.2 Hardware and Software Requirements
Intel uses the following hardware and software to test the design examples:
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Hardware
• Intel Arria 10 GX FPGA Development Kit
• SDI Signal Generator
• SDI Signal Analyzer
• SubMiniature version B (SMB) to Bayonet Neill–Concelman (BNC) cables for
single-rate and triple-rate designs, or BNC to BNC cables for multi-rate designs
• VIDIO™ FMC Development Module VIDIO-12G-A (Nextera 12G SDI FMC daughter
card) for multi-rate designs
Software
• Intel Quartus Prime (for hardware testing)
• ModelSim* - Intel FPGA Edition, ModelSim-SE, NCSim (Verilog only), Riviera-Pro,
or VCS (Verilog only)/VCS-MX simulator
1.3 Generating the Design
Use the SDI II parameter editor in the Quartus Prime software to generate the design
examples.
Figure 3. Generating the Design Flow
Start Parameter
Editor
Specify IP Variation
and Select Device
Select
Design Parameters
Initiate
Design Generation
Specify
Example Design
1. Create a project targeting Arria 10 device family and select the desired device.
2. In the IP Catalog, locate and double-click SDI II IP Core. The New IP Variant
or New IP Variation window appears.
3. Specify a top-level name for your custom IP variation. The parameter editor saves
the IP variation settings in a file named <your_ip>.ip or <your_ip>.qsys.
4. Click OK. The parameter editor appears.
5. On the IP tab, select your desired IP settings. The generated design example will
be based on your settings.
6. On the Design Example tab, select Simulation to generate the testbench, and
select Synthesis to generate the hardware design example.
You must select at least one of these options to generate the design example files.
7. For Generate File Format, select Verilog or VHDL.
8. For Target Development Kit, select Arria 10 GX FPGA Development Kit. You
may change the target device using the Change Target Device parameter if your
board revision does not match the grade of the default targeted device.
9. Click Generate Example Design.
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1.4 Simulating the Design
The SDI II design example testbench simulates one channel serial loopback design
with TX instance connected to an internal video pattern generator. The serial output
from the TX instance connects to the RX instance in the testbench. The testbench also
includes checkers and control mechanisms.
Figure 4. Design Simulation Flow
Change to
<Simulator>
Directory
Run
<Simulation Script>
Analyze
Results
1. Navigate to the simulation folder of your choice.
2. Run the simulation script for the supported simulator of your choice. The script
compiles and runs the testbench in the simulator.
3. Analyze the results.
Table 3. Steps to Run Simulation
Simulator Working Directory Instructions
Riviera-Pro /simulation/aldec In the GUI, type:
do aldec.do
NCSim /simulation/cadence In the command line, type:
source ncsim.sh
ModelSim /simulation/mentor In the GUI, type:
do mentor.do
VCS /simulation/synopsys/vcs In the command line, type:
source vcs_sim.sh
VCS-MX /simulation/synopsys/
vcsmx
In the command line, type:
source vcsmx_sim.sh
A successful simulation ends with the following message:
#### TRANSMIT TEST COMPLETED SUCCESSFULLY! ####
#
#### Channel 1: RECEIVE TEST COMPLETED SUCCESSFULLY! ####
1.5 Compiling and Testing the Design
Compile Design
in Quartus Prime
Software
Set Up Hardware Program Device Test Design
in Hardware
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To compile and run a demonstration test on the hardware design example, follow
these steps:
1. Ensure that the hardware design example generation is complete.
2. Open quartus/sdi_ii_a10_demo.qpf.
3. Click Processing ➤ Start Compilation.
4. If you turn on the Dynamic Tx clock switching parameter in the Design
Example parameter editor, set the frequency for CLK2 or CLK3 in the Si5338
(U14) tab of the Clock Control GUI.
• For HD/3G-SDI single-rate and triple-rate designs, set CLK3 to 148.3516 MHz.
• For multi-rate designs, set CLK2 to 296.7033 MHz.
5. After successful compilation, the Quartus Prime software generates a .sof file in
your specified directory.
6. Configure the selected Arria 10 device on the development board using the
generated .sof file (Tools ➤ Programmer ).
7. For serial loopback designs, open the System Console to control the internal video
pattern generator. Click Tools ➤ System Debugging Tools ➤ System Console.
Note: Close the Clock Control GUI and the Programmer window before you open
the System Console.
8. After the initialization, type source ../hwtest/tpg_ctrl.tcl in the System
Console to open the pattern generator control user interface. Select your desired
video format.
Related Links
Setting Up Environment Variables
Provides information about setting up the Clock Control application.
1.5.1 Connection and Settings Guidelines
Before programing with the .sof file, ensure that the connections and settings are
correct.
Connections and Settings for HD/3G-SDI Single Rate and Triple Rate Designs
• For parallel loopback design, the on-board SMB RX connector (J20) connects to an
external video source and the on-board SMB TX connector (J21) connects to a
video analyzer.
• For serial loopback design, the on-board SMB TX connector (J21) connects to an
on-board SMB RX connector (J20) or a video analyzer.
• Ensure all switches on the development board are in default position.
• The SDI video analyzer displays the video generated from the source.
Note: For parallel loopback designs, you may need to switch the Si516_FS
(SW6.3) at the back of the board if you are switching between fractional
frame rate and integer frame rate video format.
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Figure 5. Switch Settings on the Arria 10 Development Board
SW5
ON
1 2 3 4
MSEL0
MSEL1
MSEL2
VIDEN
SW4
CLK_SEL
CLK_EN
Si516_FS
FACTORY
RZQ_B2K
ON
1
1 0 1 0
2 3 4
ARRIA 10
MAX V
FMCA
FMCB
SW6
ON
1 2 3 4 5
Table 4. SW6 DIP Switch Default Settings (Board Button)
Switch Board Label Description
1 CLK_SEL • ON for 100 MHz on-board clock oscillator selection (Default
position)
• OFF for SMA input clock selection
2 CLK_EN OFF for setting CLK_ENABLE high to the MAX V
3 SI516_FS • ON for setting the SDI REFCLK frequency to 148.35 MHz
•OFF for setting the SDI REFCLK frequency to 148.5 MHz (Default
position)
4 FACTORY • ON to load factory from flash (Default position)
• OFF to load user hardware from flash
5 RZQ_B2K • ON for setting RZQ resistor of Bank 2K to 99.17 ohm
• OFF for setting RZQ resistor of Bank 2K to 240 ohm (Default
position)
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Connections and Settings for Multi Rate Design
• A VIDIO™ FMC Development Module VIDIO-12G-A (Nextera 12G SDI FMC
daughter card) connects to the FMC Port B on the development board.
• For parallel loopback design, the BNC RX connector (J1/12G In) connects to an
external video source and the TX connector (J2/12G Out) connects to a video
analyzer.
• For serial loopback design, the BNC TX connector (J2/12G Out) connects to the
BNC RX connector (J1/12G In) or a video analyzer.
• Ensure all switches on the development board are in default position.
• The SDI video analyzer displays the video generated from the source.
Note: Change the jumper (J8) position before switching between fractional frame
rate and integer frame rate video formats. Press the push button (PB0) to
trigger a device (LMK03328) power cycling through the PDN pin every time
you change the jumper (J8) position.
Figure 6. Jumper Settings on Nextera 12G-SDI FMC Daughter Card
Refer to these settings to change the jumper (J8) position.
Pin 2 - 3
296.7 MHz
Open Pin 1 - 2
SDI Mode
Table 5. Jumper Settings
Jumper Block Description
J7 Programming header
J8 To switch the generated clock frequency for the TX channel:
• Pin 1–2 = 297 MHz
• Pin 2–3 = 297/1.001 MHz
J9 To select SDI or IP mode:
• Pin 1–2 = SDI mode
• Pin 2–3 = IP mode
Related Links
Intel Arria 10 FPGA Development Kit User Guide
1.5.2 Design Limitations for Serial Loopback Design
The serial loopback design example has the following limitations:
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• You may encounter certain problems with the 12G-SDI 2160p59.94 in the serial
loopback design that cannot be detected on the Omnitek Ultra 4K analyzer
(software v2.1).
• Serial loopback design is mainly for image and TX clock switching demonstrations
only. To get a more accurate jitter performance with the daughter card
components, use the parallel loopback design and connect it to a clean video
source.
• To allow segmented frame video format (1080sF30, 1080sF25) and interlaced
video format (1080i60, 1080i50) to be correctly differentiated in the external
analyzer, Payload ID has to be inserted in the serial loopback design.
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2 SDI II Design Example Detailed Description
The SDI II IP core includes three design examples for Arria 10 devices.
• Parallel loopback with external VCXO
• Parallel loopback without external VCXO
• Serial loopback
Features
• For HD/3G-SDI single rate and triple rate designs, you can choose either CMU or
fPLL as the TX PLL.
• All designs use LED status for early debugging stage.
• The simplex serial loopback designs include RX and TX options. To use RX or TX
only components, remove the irrelevant blocks from the designs.
User Requirement Preserve Remove
RX Only RX Top — TX Top
— Transceiver Arbiter
TX Only TX Top — RX Top
— Transceiver Arbiter
Note: You can directly connect the Avalon-MM pins at the RX or TX Top as shown
in the diagram below.
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Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus
and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other
countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2008
Registered

Figure 7. Components Required for TX or RX Only Design
Top
RX Top
SDI II
RX
Transceiver
PHY Reset
Controller (RX)
Transceiver
Native PHY
(RX)
RX
Reconfiguration
Management
Transceiver
Arbiter
Pattern Generator Control
SDI RX System
TX Top
SDI II
TX
Transceiver
PHY Reset
C ontroller (RT)
Transceiver
Native PHY
(TX)
SDI TX System
TX
PLL
Alt
Pattern Generator
Control PIO
Parallel Data
Serial Data
Control/Status
Avalon-MM
JTAG to Avalon
Master Bridge
Video Pattern
Generator
TX
PLL
TX
Reconfiguration
Management
TX Only Components
RX Only Components
Removed Blocks
2.1 Parallel Loopback Design Examples
The parallel loopback design examples demonstrate simplex and duplex channel
modes with and without external VCXO.
Note: For parallel loopback duplex designs, do not share the TX PLL reference clock with the
RX transceiver reference clock. The design logic tunes the TX PLL clock to match the
RX recovered clock frequency. For the parallel loopback with external VCXO designs
(single-rate and triple-rate), use the only 148.5 MHz on-board oscillator as the TX PLL
reference clock. For the RX reference clock, use a 270 MHz clock from another on-
board oscillator.
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Parallel Loopback with Simplex Mode
Figure 8. Parallel Loopback with Simplex Mode Block Diagram
Top
RX Top
SDI II
RX
Transceiver
PHY Reset
Controller (RX)
Transceiver
Native PHY
(RX)
RX
Reconfiguration
Management (3)
Transceiver
Arbiter (3)
Loopback Top
SDI RX System
TX Top
SDI II
TX
Transceiver
PHY Reset
Controller (TX)
Transceiver
Native PHY
(TX)
SDI TX System
TX PLL
Loopback
FIFO
PFD (1)
Reclock (2)
(4)
Parallel Data
Serial Data
Control/Status
Avalon-MM
(1) Generate up/down control signal to on-board Si516 for clock synchronization purpose.
(2) Block/Connection only required for parallel loopback without external VCXO designs.
(3) Block/Connection only required for triple-rate/multi-rate designs.
(4) FVH video sync signals to LMH1983 for clock synchronization purpose.
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Figure 9. Parallel Loopback with Simplex Mode Clocking Scheme
Top
RX Top
SDI II
RX
Transceiver
PHY Reset
Controller (RX)
Transceiver
Native PHY
(RX)
RX
Reconfiguration
Management (3)
Transceiver
Arbiter
Loopback Top
SDI RX System
TX Top
SDI II
TX
Transceiver
PHY Reset
Controller (TX)
Transceiver
Native PHY
(TX)
SDI TX System
TX PLL
Loopback
FIFO
PFD (1)
Reclock (2)
TX PLL Reference Clock
TX Transceiver clkout
TX PLL Serial Clock
RX Reference Clock
RX Transceiver clkout
Management Clock
RX Reference
Clock
Management
Clock
TX PLL
Reference
Clock
(1) Block/Connection only required for parallel loopback with external VCXO designs.
(2) Block/Connection only required for parallel loopback without external VCXO designs.
(3) Block/Connection only required for triple-rate/multi-rate designs.
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Parallel Loopback with Duplex Mode
Figure 10. Parallel Loopback with Duplex Mode Block Diagram
Top
Duplex Top
SDI II
Duplex
Transceiver
PHY Reset
Controller (RX)
Transceiver
Native PHY
(Duplex)
RX
Reconfiguration
Management (3)
Transceiver
Arbiter (3)
Loopback Top
SDI Duplex System
TX PLL
Loopback
FIFO
PFD (1)
Reclock (2)
Parallel Data
Serial Data
Control/Status
Avalon-MM
(4)
Transceiver
PHY Reset
C ontroller (TX)
(1) Generate up/down control signal to on-board Si516 for clock synchronization purpose.
(2) Block/Connection only required for parallel loopback without external VCXO designs.
(3) Block/Connection only required for triple-rate/multi-rate designs.
(4) FVH video sync signals to LMH1983 for clock synchronization purpose.
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Figure 11. Parallel Loopback with Duplex Mode Clocking Scheme
Top
Duplex Top
SDI II
Duplex
Transceiver
PHY Reset
Controller (RX)
Transceiver
Native PHY
(Duplex)
RX
Reconfiguration
Management (3)
Transceiver
Arbiter (3)
Loopback Top
SDI Duplex System
TX PLL
Loopback
FIFO
PFD (1)
Reclock (2)
Transceiver
PHY Reset
Controller (TX)
TX PLL Reference Clock
TX Transceiver clkout
TX PLL Serial Clock
RX Reference Clock
RX Transceiver clkout
Management Clock
RX Reference
Clock
Management
Clock
TX PLL
Reference
Clock
(1) Block/Connection only required for parallel loopback with external VCXO designs.
(2) Block/Connection only required for parallel loopback without external VCXO designs.
(3) Block/Connection only required for triple-rate/multi-rate designs.
2.2 Serial Loopback Design Examples
The serial loopback design examples demonstrate simplex and duplex channel modes.
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Serial Loopback with Simplex Mode
Figure 12. Serial Loopback with Simplex Mode Block Diagram
Top
RX Top
SDI II
RX
Transceiver
PHY Reset
Controller (RX)
Transceiver
Native PHY
(RX)
RX
Reconfiguration
Management (1)
Transceiver Arbiter
(1), (2)
Pattern Generator Control
SDI RX System
TX Top
SDI II
TX
Transceiver
PHY Reset
Controller (TX)
Transceiver
Native PHY
(TX)
SDI TX System
TX
PLL
Alt (2)
Pattern Generator
Control PIO
Parallel Data
Serial Data
Control/Status
Avalon-MM
(1) Block/Connection only required for triple-rate/multi-rate designs.
(2) Block/Connection only required for triple-rate/multi-rate for TX PLL switching designs.
(3) Block/Connection only required for triple-rate/multi-rate for TX PLL reference clock switching designs.
JTAG to Avalon
Master Bridge
Video Pattern
Generator
(1) (2)
(1)
(1)
TX
PLL
TX Reconfiguration
Management
(2), (3)
(2)
(2)
(2)
(2)
(3)
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Figure 13. Serial Loopback with Simplex Mode Clocking Scheme
Top
RX Top
SDI II
RX
Transceiver
PHY Reset
Controller (RX)
Transceiver
Native PHY
(RX)
RX
Reconfiguration
Management (1)
Transceiver Arbiter
(1), (2)
Pattern Generator Control
SDI RX System
TX Top
SDI II
TX
Transceiver
PHY Reset
Controller (TX)
Transceiver
Native PHY
(TX)
SDI TX System
TX
PLL
Alt (2)
Pattern Generator
Control PIO
JTAG to Avalon
Master Bridge
Video Pattern
Generator
TX
PLL
TX Reconfiguration
Management
(2), (3)
TX PLL Reference Clock
TX Transceiver clkout
TX PLL Serial Clock
RX Reference Clock
RX Transceiver clkout
Management Clock
(1) Block/Connection only required for triple-rate/multi-rate designs.
(2) Block/Connection only required for triple-rate/multi-rate for TX PLL switching designs.
(3) Block/Connection only required for triple-rate/multi-rate for TX PLL reference clock switching designs.
Management
Clock
RX Reference
Clock
TX PLL Alt
Reference
Clock (2), (3)
TX PLL
Reference
Clock
(1) (2)
(3)
(3)
2 SDI II Design Example Detailed Description
UG-20076 | 2017.05.08
Intel® Arria® 10 SDI II IP Core Design Example User Guide
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