Intel Cyclone 10 GX User manual

Intel® Cyclone® 10 GX Transceiver
PHY User Guide
Updated for Intel® Quartus® Prime Design Suite: 18.1
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Contents
1. Intel® Cyclone® 10 GX Transceiver PHY Overview ......................................................... 7
1.1. Device Transceiver Layout......................................................................................8
1.1.1. Intel Cyclone 10 GX Device Transceiver Layout.............................................. 8
1.1.2. Intel Cyclone 10 GX Device Package Details ................................................10
1.2. Transceiver PHY Architecture Overview.................................................................. 10
1.2.1. Transceiver Bank Architecture....................................................................10
1.2.2. PHY Layer Transceiver Components........................................................... 11
1.2.3. Transceiver Phase-Locked Loops................................................................ 13
1.2.4. Clock Generation Block (CGB)...................................................................14
1.3. Calibration.......................................................................................................... 14
1.4. Intel Cyclone 10 GX Transceiver PHY Overview Revision History................................. 15
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers....................................... 16
2.1. Transceiver Design IP Blocks................................................................................. 16
2.2. Transceiver Design Flow........................................................................................17
2.2.1. Select and Instantiate the PHY IP Core........................................................17
2.2.2. Configure the PHY IP Core.........................................................................19
2.2.3. Generate the PHY IP Core......................................................................... 19
2.2.4. Select the PLL IP Core.............................................................................. 19
2.2.5. Configure the PLL IP Core........................................................................ 20
2.2.6. Generate the PLL IP Core ......................................................................... 21
2.2.7. Reset Controller ......................................................................................21
2.2.8. Create Reconfiguration Logic..................................................................... 21
2.2.9. Connect the PHY IP to the PLL IP Core and Reset Controller........................... 22
2.2.10. Connect Datapath ................................................................................ 22
2.2.11. Make Analog Parameter Settings ............................................................. 22
2.2.12. Compile the Design................................................................................ 22
2.2.13. Verify Design Functionality...................................................................... 22
2.3. Cyclone 10 GX Transceiver Protocols and PHY IP Support......................................... 24
2.4. Using the Cyclone 10 GX Transceiver Native PHY IP Core...........................................26
2.4.1. Presets................................................................................................... 28
2.4.2. General and Datapath Parameters ............................................................. 28
2.4.3. PMA Parameters......................................................................................31
2.4.4. Enhanced PCS Parameters ........................................................................34
2.4.5. Standard PCS Parameters........................................................................ 41
2.4.6. PCS Direct ............................................................................................ 45
2.4.7. Dynamic Reconfiguration Parameters..........................................................45
2.4.8. PMA Ports.............................................................................................. 50
2.4.9. Enhanced PCS Ports................................................................................ 53
2.4.10. Standard PCS Ports................................................................................ 62
2.4.11. IP Core File Locations............................................................................. 67
2.4.12. Unused Transceiver Channels...................................................................69
2.5. Interlaken..........................................................................................................70
2.5.1. Metaframe Format and Framing Layer Control Word.....................................71
2.5.2. Interlaken Configuration Clocking and Bonding............................................73
2.5.3. How to Implement Interlaken in Cyclone 10 GX Transceivers......................... 79
2.5.4. Native PHY IP Parameter Settings for Interlaken..........................................82
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2.6. Ethernet............................................................................................................. 86
2.6.1. Gigabit Ethernet (GbE) and GbE with IEEE 1588v2....................................... 87
2.6.2. 10GBASE-R and 10GBASE-R with IEEE 1588v2 Variants............................... 98
2.6.3. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel FPGA IP Core....................... 108
2.6.4. XAUI PHY IP Core...................................................................................121
2.6.5. Acronyms.............................................................................................121
2.7. PCI Express (PIPE)............................................................................................ 122
2.7.1. Transceiver Channel Datapath for PIPE......................................................123
2.7.2. Supported PIPE Features......................................................................... 123
2.7.3. How to Connect TX PLLs for PIPE Gen1 and Gen2 Modes............................. 128
2.7.4. How to Implement PCI Express (PIPE) in Cyclone 10 GX Transceivers...........131
2.7.5. Native PHY IP Parameter Settings for PIPE ...............................................131
2.7.6. fPLL IP Parameter Core Settings for PIPE................................................... 135
2.7.7. ATX PLL IP Parameter Core Settings for PIPE .............................................137
2.7.8. Native PHY IP Ports for PIPE................................................................... 139
2.7.9. fPLL Ports for PIPE..................................................................................143
2.7.10. ATX PLL Ports for PIPE...........................................................................145
2.7.11. How to Place Channels for PIPE Configurations......................................... 146
2.8. CPRI................................................................................................................149
2.8.1. Transceiver Channel Datapath and Clocking for CPRI...................................149
2.8.2. Supported Features for CPRI ..................................................................151
2.8.3. Word Aligner in Manual Mode for CPRI.......................................................152
2.8.4. How to Implement CPRI in Cyclone 10 GX Transceivers............................... 153
2.8.5. Native PHY IP Parameter Settings for CPRI............................................... 155
2.9. Other Protocols..................................................................................................158
2.9.1. Using the "Basic (Enhanced PCS)" Configuration........................................158
2.9.2. Using the Basic/Custom, Basic/Custom with Rate Match Configurations of
Standard PCS........................................................................................ 166
2.9.3. How to Implement PCS Direct Transceiver Configuration Rule.......................185
2.10. Simulating the Transceiver Native PHY IP Core..................................................... 186
2.10.1. NativeLink Simulation Flow.................................................................... 187
2.10.2. Scripting IP Simulation..........................................................................192
2.10.3. Custom Simulation Flow........................................................................ 193
2.11. Implementing Protocols in Intel Cyclone 10 GX Transceivers Revision History........... 196
3. PLLs and Clock Networks............................................................................................ 198
3.1. PLLs................................................................................................................. 200
3.1.1. Transmit PLLs Spacing Guidelines when using ATX PLLs and fPLLs................. 200
3.1.2. ATX PLL................................................................................................ 201
3.1.3. fPLL......................................................................................................203
3.1.4. CMU PLL............................................................................................... 206
3.2. Input Reference Clock Sources............................................................................208
3.2.1. Dedicated Reference Clock Pins............................................................... 209
3.2.2. Receiver Input Pins.................................................................................209
3.2.3. PLL Cascading as an Input Reference Clock Source..................................... 210
3.2.4. Reference Clock Network.........................................................................210
3.2.5. Global Clock or Core Clock as an Input Reference Clock...............................210
3.3. Transmitter Clock Network..................................................................................210
3.3.1. x1 Clock Lines....................................................................................... 211
3.3.2. x6 Clock Lines....................................................................................... 212
3.3.3. xN Clock Lines....................................................................................... 214
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3.4. Clock Generation Block....................................................................................... 216
3.5. FPGA Fabric-Transceiver Interface Clocking............................................................ 217
3.6. Transmitter Data Path Interface Clocking...............................................................219
3.7. Receiver Data Path Interface Clocking................................................................... 220
3.8. Unused/Idle Clock Line Requirements................................................................... 221
3.9. Channel Bonding................................................................................................222
3.9.1. PMA Bonding......................................................................................... 222
3.9.2. PMA and PCS Bonding.............................................................................224
3.9.3. Selecting Channel Bonding Schemes.........................................................225
3.9.4. Skew Calculations.................................................................................. 226
3.10. PLL Feedback and Cascading Clock Network......................................................... 226
3.11. Using PLLs and Clock Networks.......................................................................... 231
3.11.1. Non-bonded Configurations....................................................................231
3.11.2. Bonded Configurations.......................................................................... 235
3.11.3. Implementing PLL Cascading..................................................................240
3.11.4. Timing Closure Recommendations...........................................................241
3.12. PLLs and Clock Networks Revision History............................................................241
4. Resetting Transceiver Channels.................................................................................. 243
4.1. When Is Reset Required? ................................................................................... 243
4.2. Transceiver PHY Implementation.......................................................................... 244
4.3. How Do I Reset?................................................................................................ 245
4.3.1. Model 1: Default Model........................................................................... 245
4.3.2. Model 2: Acknowledgment Model..............................................................254
4.3.3. Transceiver Blocks Affected by Reset and Powerdown Signals....................... 258
4.4. Using the Transceiver PHY Reset Controller............................................................ 259
4.4.1. Parameterizing the Transceiver PHY Reset Controller IP............................... 261
4.4.2. Transceiver PHY Reset Controller Parameters............................................. 261
4.4.3. Transceiver PHY Reset Controller Interfaces............................................... 264
4.4.4. Transceiver PHY Reset Controller Resource Utilization.................................. 267
4.5. Using a User-Coded Reset Controller.....................................................................267
4.5.1. User-Coded Reset Controller Signals......................................................... 268
4.6. Combining Status or PLL Lock Signals .................................................................. 269
4.7. Timing Constraints for Bonded PCS and PMA Channels............................................ 269
4.8. Resetting Transceiver Channels Revision History.....................................................271
5. Cyclone 10 GX Transceiver PHY Architecture............................................................. 272
5.1. Cyclone 10 GX PMA Architecture......................................................................... 272
5.1.1. Transmitter........................................................................................... 272
5.1.2. Receiver................................................................................................275
5.1.3. Loopback.............................................................................................. 282
5.2. Cyclone 10 GX Enhanced PCS Architecture........................................................... 283
5.2.1. Transmitter Datapath.............................................................................284
5.2.2. Receiver Datapath.................................................................................291
5.3. Cyclone 10 GX Standard PCS Architecture............................................................ 299
5.3.1. Transmitter Datapath..............................................................................300
5.3.2. Receiver Datapath..................................................................................305
5.4. Intel Cyclone 10 GX Transceiver PHY Architecture Revision History............................314
6. Reconfiguration Interface and Dynamic Reconfiguration .......................................... 315
6.1. Reconfiguring Channel and PLL Blocks...................................................................315
6.2. Interacting with the Reconfiguration Interface........................................................ 316
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6.2.1. Reading from the Reconfiguration Interface............................................... 318
6.2.2. Writing to the Reconfiguration Interface.................................................... 318
6.3. Configuration Files............................................................................................. 319
6.4. Multiple Reconfiguration Profiles...........................................................................321
6.5. Embedded Reconfiguration Streamer.................................................................... 322
6.6. Arbitration.........................................................................................................325
6.7. Recommendations for Dynamic Reconfiguration......................................................327
6.8. Steps to Perform Dynamic Reconfiguration............................................................ 328
6.9. Direct Reconfiguration Flow................................................................................. 330
6.10. Native PHY IP or PLL IP Core Guided Reconfiguration Flow..................................... 331
6.11. Reconfiguration Flow for Special Cases................................................................ 333
6.11.1. Switching Transmitter PLL ....................................................................333
6.11.2. Switching Reference Clocks....................................................................335
6.12. Changing PMA Analog Parameters......................................................................338
6.12.1. Changing VOD, Pre-emphasis Using Direct Reconfiguration Flow................. 341
6.12.2. Changing CTLE Settings in Manual Mode Using Direct Reconfiguration Flow.. 342
6.12.3. Enabling and Disabling Loopback Modes Using Direct Reconfiguration Flow...343
6.13. Ports and Parameters........................................................................................346
6.14. Dynamic Reconfiguration Interface Merging Across Multiple IP Blocks...................... 351
6.15. Embedded Debug Features................................................................................ 353
6.15.1. Altera Debug Master Endpoint................................................................ 354
6.15.2. Optional Reconfiguration Logic............................................................... 354
6.16. Using Data Pattern Generators and Checkers....................................................... 359
6.16.1. Using PRBS Data Pattern Generator and Checker..................................... 359
6.16.2. Using Pseudo Random Pattern Mode........................................................368
6.17. Timing Closure Recommendations...................................................................... 369
6.18. Unsupported Features....................................................................................... 371
6.19. Cyclone 10 GX Transceiver Register Map.............................................................372
6.20. Reconfiguration Interface and Dynamic Reconfiguration Revision History..................372
7. Calibration.................................................................................................................. 373
7.1. Reconfiguration Interface and Arbitration with PreSICE Calibration Engine .................373
7.2. Calibration Registers...........................................................................................375
7.2.1. Avalon-MM Interface Arbitration Registers................................................. 375
7.2.2. Transceiver Channel Calibration Registers.................................................. 376
7.2.3. Fractional PLL Calibration Registers...........................................................376
7.2.4. ATX PLL Calibration Registers...................................................................377
7.2.5. Capability Registers................................................................................ 377
7.2.6. Rate Switch Flag Register........................................................................ 379
7.3. Power-up Calibration.......................................................................................... 380
7.4. User Recalibration.............................................................................................. 383
7.4.1. Conditions That Require User Recalibration................................................ 383
7.4.2. User Recalibration Sequence ...................................................................384
7.5. Calibration Example............................................................................................385
7.5.1. ATX PLL Recalibration............................................................................. 385
7.5.2. Fractional PLL Recalibration..................................................................... 385
7.5.3. CDR/CMU PLL Recalibration..................................................................... 386
7.5.4. PMA Recalibration...................................................................................386
7.6. Calibration Revision History................................................................................. 387
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8. Analog Parameter Settings........................................................................................ 388
8.1. Making Analog Parameter Settings using the Assignment Editor................................388
8.2. Updating Quartus Settings File with the Known Assignment.................................... 388
8.3. Analog Parameter Settings List............................................................................389
8.4. Receiver General Analog Settings........................................................................ 390
8.4.1. XCVR_C10_RX_TERM_SEL......................................................................390
8.5. Receiver Analog Equalization Settings.................................................................. 390
8.5.1. CTLE Settings........................................................................................ 391
8.5.2. VGA Settings......................................................................................... 393
8.6. Transmitter General Analog Settings.................................................................... 393
8.6.1. XCVR_C10_TX_TERM_SEL.......................................................................394
8.6.2. XCVR_C10_TX_COMPENSATION_EN........................................................ 394
8.6.3. XCVR_C10_TX_SLEW_RATE_CTRL............................................................ 395
8.7. Transmitter Pre-Emphasis Analog Settings............................................................395
8.7.1. XCVR_C10_TX_PRE_EMP_SIGN_PRE_TAP_1T............................................396
8.7.2. XCVR_C10_TX_PRE_EMP_SIGN_PRE_TAP_2T............................................396
8.7.3. XCVR_C10_TX_PRE_EMP_SIGN_1ST_POST_TAP........................................397
8.7.4. XCVR_C10_TX_PRE_EMP_SIGN_2ND_POST_TAP....................................... 397
8.7.5. XCVR_C10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T......................... 398
8.7.6. XCVR_C10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_2T......................... 398
8.7.7. XCVR_C10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP..................... 399
8.7.8. XCVR_C10_TX_PRE_EMP_SWITCHING_CTRL_2ND_POST_TAP.....................399
8.8. Transmitter VOD Settings....................................................................................400
8.8.1. XCVR_C10_TX_VOD_OUTPUT_SWING_CTRL.............................................400
8.9. Dedicated Reference Clock Settings...................................................................... 401
8.9.1. XCVR_C10_REFCLK_TERM_TRISTATE.......................................................401
8.9.2. XCVR_C10_TX_XTX_PATH_ANALOG_MODE................................................401
8.10. Unused Transceiver Channels Settings.................................................................402
8.11. Analog Parameter Settings Revision History......................................................... 402
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1. Intel® Cyclone® 10 GX Transceiver PHY Overview
This user guide provides details about the Intel® Cyclone® 10 GX transceiver physical
(PHY) layer architecture, PLLs, clock networks, and transceiver PHY IP core. Intel
Quartus® Prime Pro Edition software version 17.1 supports the Intel Cyclone 10 GX
transceiver PHY IP core. It also provides protocol specific implementation details and
describes features such as transceiver reset and dynamic reconfiguration of
transceiver channels and PLLs.
Intel’s FPGA Intel Cyclone 10 GX devices offer up to 12 transceiver channels with
integrated advanced high speed analog signal conditioning and clock data recovery
techniques.
The Intel Cyclone 10 GX devices have transceiver channels that can support data rates
up to 12.5 Gbps for chip-to-chip and chip-to-module communication, and up to 6.6
Gbps for backplane communication. You can achieve transmit and receive data rates
below 1.0 Gbps with oversampling.
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countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
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*Other names and brands may be claimed as the property of others.
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1.1. Device Transceiver Layout
Figure 1. Intel Cyclone 10 GX FPGA Architecture Block Diagram
The transceiver channels are placed on the left side periphery in Intel Cyclone 10 GX devices.
Core Logic Fabric
M20K Internal Memory Blocks
Transceiver Channels
Hard IP Per Transceiver: Standard PCS, Enhanced PCS
PCI Express Gen2 Hard IP
PLLs
M20K Internal Memory Blocks
Variable Precision DSP Blocks
I/O PLLs
Hard Memory Controllers, General-Purpose I/O Cells, LVDS
M20K Internal Memory BlocksM20K Internal Memory Blocks
Variable Precision DSP Blocks
Core Logic Fabric
I/O PLLs
Hard Memory Controllers, General-Purpose I/O Cells, LVDS
M20K Internal Memory BlocksM20K Internal Memory Blocks
Variable Precision DSP Blocks
1.1.1. Intel Cyclone 10 GX Device Transceiver Layout
Intel Cyclone 10 GX devices offer 6-, 10-, or 12-transceiver channel counts. Each
transceiver bank has up to six transceiver channels. Intel Cyclone 10 GX devices also
have one embedded PCI Express Hard IP block.
The figures below illustrate different transceiver bank layouts for Intel Cyclone 10 GX
device variants.
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Figure 2. Intel Cyclone 10 GX Devices with 12 Transceiver Channels and One PCIe Hard
IP Block
Transceiver
Bank
GXBL1D
Transceiver
Bank
GXBL1C
Transceiver
Bank
Transceiver
Bank
CH5
CH4
CH3
CH2
CH1
CH0
Transceiver
Bank
Legend:
PCIe Gen1 - Gen2 Hard IP blocks with Configuration via Protocol (CvP) capabilities.
Cyclone 10 GX device with 12 transceiver channels and one PCIe Hard IP block.
PCIe
Gen1 - Gen2
Hard IP
(with CvP)
Figure 3. Intel Cyclone 10 GX Devices with 10 Transceiver Channels and One PCIe Hard
IP Block
Transceiver
Bank
GXBL1D
Transceiver
Bank
GXBL1C
Transceiver
Bank
Transceiver
Bank
CH5
CH4
CH3
CH2
CH1
CH0
Transceiver
Bank
Legend:
PCIe Gen1 - Gen2 Hard IP blocks with Configuration via Protocol (CvP) capabilities.
Cyclone 10 GX device with 10 transceiver channels and one PCIe Hard IP block.
PCIe
Gen1 - Gen2
Hard IP
(with CvP)
Figure 4. Intel Cyclone 10 GX Devices with 6 Transceiver Channels and One PCIe Hard
IP Block
Transceiver
Bank
GXBL1C Transceiver
Bank
CH5
CH4
CH3
CH2
CH1
CH0
Transceiver
Bank
GXBL1C
Note:
Legend:
PCIe Gen1 - Gen2 Hard IP block with Configuration via Protocol (CvP) capabilities.
Cyclone 10 GX device with six transceiver channels and one PCIe Hard IP block.
PCIe Gen1 - Gen2 Hard IP (with CvP) (1)
(1) Only CH5 and CH4 support PCIe Hard IP block with CvP capabilities.
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1.1.2. Intel Cyclone 10 GX Device Package Details
The following tables list package sizes, available transceiver channels, and PCI Express
Hard IP blocks for Intel Cyclone 10 GX devices.
Table 1. Package Details for Devices with Transceivers and Hard IP Blocks Located on
the Left Side Periphery of the Device
• Package U484: 19mm x 19mm package; 484 pins.
• Package F672: 27mm x 27mm package; 672 pins.
• Package F780: 29mm x 29mm package; 780 pins.
Device U484 F672 F780
Transceiver Count, PCIe Hard IP Block Count
10CX085 6, 1 6, 1 N/A
10CX105 6, 1 10, 1 12, 1
10CX150 6, 1 10, 1 12, 1
10CX220 6, 1 10, 1 12, 1
1.2. Transceiver PHY Architecture Overview
A link is defined as a single entity communication port. A link can have one or more
transceiver channels. A transceiver channel is synonymous with a transceiver lane.
For example, a 10GBASE-R link has one transceiver channel or lane with a data rate of
10.3125 Gbps. A 40GBASE-R link has four transceiver channels. Each transceiver
channel operates at a lane data rate of 10.3125 Gbps. Four transceiver channels give
a total collective link bandwidth of 41.25 Gbps (40 Gbps before and after 64B/66B
Physical Coding Sublayer (PCS) encoding and decoding).
1.2.1. Transceiver Bank Architecture
The transceiver bank is the fundamental unit that contains all the functional blocks
related to the device's high speed serial transceivers.
Each transceiver bank includes four or six transceiver channels in all devices.
The figures below show the transceiver bank architecture with the phase locked loop
(PLL) and clock generation block (CGB) resources available in each bank.
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Figure 5. Transceiver Bank Architecture
PMA
Channel PLL
(CDR Only)
PCS
Local CGB5
CH5
PMA
Channel PLL
(CMU/CDR)
PCS
Local CGB4
CH4
PMA
Channel PLL
(CDR Only)
PCS
Local CGB3
CH3
PMA
Channel PLL
(CDR Only)
PCS
Local CGB2
CH2
PMA
Channel PLL
(CMU/CDR)
PCS
Local CGB1
CH1
PMA
Channel PLL
(CDR Only)
PCS
Local CGB0
CH0
FPGA Core
Fabric
Clock
Distribution
Network
Six-Channel Transceiver Bank
fPLL1
Master
CGB1
Master
CGB0
ATX
PLL0
ATX
PLL1
fPLL0
Legend:
4-Channel transceiver bank
Note: This figure is a high level overview of the transceiver bank architecture. For details
about the available clock networks refer to the PLLs and Clock Networks chapter.
Related Information
PLLs and Clock Networks on page 198
1.2.2. PHY Layer Transceiver Components
Transceivers in Intel Cyclone 10 GX devices support both Physical Medium Attachment
(PMA) and Physical Coding Sublayer (PCS) functions at the physical (PHY) layer.
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A PMA is the transceiver's electrical interface to the physical medium. The transceiver
PMA consists of standard blocks such as:
• serializer/deserializer (SERDES)
• clock and data recovery PLL
• analog front end transmit drivers
• analog front end receive buffers
The PCS can be bypassed with a PCS Direct configuration. Both the PMA and PCS
blocks are fed by multiple clock networks driven by high performance PLLs. In PCS
Direct configuration, the data flow is through the PCS block, but all the internal PCS
blocks are bypassed. In this mode, the PCS functionality is implemented in the FPGA
fabric.
1.2.2.1. The Transceiver Channel
Figure 6. Transceiver Channel in Full Duplex Mode
Standard PCS
Enhanced PCS
PCS Direct
Hard IP
(Optional)
Soft PIPE
(Optional)
FPGA Fabric
Transmitter PCS
Transmitter PMA
Serializer
Standard PCS
Enhanced PCS
PCS Direct
Receiver PCS
Receiver PMA
DeserializerCDR
Notes:
(1) The FPGA Fabric - PCS and PCS-PMA interface widths are configurable.
(1)
(1)
(1)
(1)
Intel Cyclone 10 GX transceiver channels have three types of PCS blocks that together
support continuous data rates between 1.0 Gbps and 10.81344 Gbps.
Table 2. PCS Types Supported by Transceiver Channels
PCS Type Data Rate
Standard PCS 1.0 Gbps to 10.81344 Gbps
Enhanced PCS 1.0 Gbps to 12.5 Gbps
PCS Direct 1.0 Gbps to 12.5 Gbps
Note: The minimum operational data rate is 1.0 Gbps for both the transmitter and receiver.
For transmitter data rates less than 1.0 Gbps, oversampling must be applied at the
transmitter. For receiver data rates less than 1.0 Gbps, oversampling must be applied
at the receiver.
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1.2.3. Transceiver Phase-Locked Loops
Each transceiver channel in Intel Cyclone 10 GX devices has direct access to three
types of high performance PLLs:
• Advanced Transmit (ATX) PLL
• Fractional PLL (fPLL)
• Channel PLL / Clock Multiplier Unit (CMU) PLL
These transceiver PLLs along with the Master or Local Clock Generation Blocks (CGB)
drive the transceiver channels.
Related Information
PLLs on page 200
1.2.3.1. Advanced Transmit (ATX) PLL
An advanced transmit (ATX ) PLL is a high performance PLL that only supports integer
frequency synthesis. The ATX PLL is the transceiver channel’s primary transmit PLL. It
can operate over the full range of supported data rates required for high data rate
applications.
Related Information
ATX PLL on page 201
1.2.3.2. Fractional PLL (fPLL)
A fractional PLL (fPLL) is an alternate transmit PLL that generates clock frequencies for
up to 12.5 Gbps data rate applications. fPLLs support both integer frequency synthesis
and fine resolution fractional frequency synthesis. Unlike the ATX PLL, the fPLL can
also be used to synthesize frequencies that can drive the core through the FPGA fabric
clock networks.
Related Information
fPLL on page 203
1.2.3.3. Channel PLL (CMU/CDR PLL)
A channel PLL resides locally within each transceiver channel. Its primary function is
clock and data recovery in the transceiver channel when the PLL is used in clock data
recovery (CDR) mode. The channel PLLs of channel 1 and 4 can be used as transmit
PLLs when configured in clock multiplier unit (CMU) mode. The channel PLLs of
channel 0, 2, 3, and 5 cannot be configured in CMU mode and therefore cannot be
used as transmit PLLs.
Related Information
CMU PLL on page 206
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1.2.4. Clock Generation Block (CGB)
In Intel Cyclone 10 GX devices, there are two types of clock generation blocks (CGBs):
• Master CGB
• Local CGB
Transceiver banks with six transceiver channels have two master CGBs. Master CGB1
is located at the top of the transceiver bank and master CGB0 is located at the bottom
of the transceiver bank. The master CGB divides and distributes bonded clocks to a
bonded channel group. It also distributes non-bonded clocks to non-bonded channels
across the x6/xN clock network.
Each transceiver channel has a local CGB. The local CGB is used for dividing and
distributing non-bonded clocks to its own PCS and PMA blocks.
Related Information
Clock Generation Block on page 216
1.3. Calibration
Intel Cyclone 10 GX FPGAs contain a dedicated calibration engine to compensate for
process variations. The calibration engine calibrates the analog portion of the
transceiver to allow both the transmitter and receiver to operate at optimum
performance.
The CLKUSR pin clocks the calibration engine. All transceiver reference clocks and the
CLKUSR clock must be free running and stable at the start of FPGA configuration to
successfully complete the calibration process and for optimal transceiver performance.
Note: For more information about CLKUSR electrical characteristics, refer to Intel Cyclone 10
GX Device Datasheet. The CLKUSR can also be used as an FPGA configuration clock.
For information about configuration requirements for the CLKUSR pin, refer to the
Configuration, Design Security, and Remote System Upgrades in Intel Cyclone 10 GX
Devices chapter in the Intel Cyclone 10 GX Core Fabric and General-Purpose I/O
Handbook. For more information about calibration, refer to the Calibration chapter. For
more information about CLKUSR pin requirements, refer to the Intel Cyclone 10 GX
Device Family Pin Connection Guidelines.
Related Information
•Calibration on page 373
•Intel Cyclone 10 GX Device Datasheet
•Configuration, Design Security, and Remote System Upgrades in Intel Cyclone 10
GX Devices
•Intel Cyclone 10 GX Device Family Pin Connection Guidelines
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1.4. Intel Cyclone 10 GX Transceiver PHY Overview Revision History
Document
Version
Changes
2017.12.28 Made the following changes:
• Updated the "Intel Cyclone 10 GX Default Settings Preset" Figure.
• Changed the transceiver count back to 6 for 10CX085 package F672 in the "Package Details for
Devices with Transceivers and Hard IP Blocks Located on the Left Side Periphery of the Device"
table.
2017.11.06 Made the following changes:
• Changed the description of the ATX PLL in the "Advanced Transmit (ATX) PLL" section.
• Changed the transceiver counts for the F672 package in the "Package Details for Devices with
Transceivers and Hard IP Blocks Located on the Left Side Periphery of the Device" table.
• Changed the description of the Fractional PLL in the "Fractional PLL (fPLL)" section.
• Changed the location of the PCIe Hard IP block in the " Cyclone 10 GX Devices with 12 Transceiver
Channels and One PCIe Hard IP Block" figure.
• Changed the location of the PCIe Hard IP block in the " Cyclone 10 GX Devices with 10 Transceiver
Channels and One PCIe Hard IP Block" figure.
• Changed the location of the PCIe Hard IP block in the " Cyclone 10 GX Devices with 6 Transceiver
Channels and One PCIe Hard IP Block" figure.
2017.05.08 Initial release.
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2. Implementing Protocols in Intel Cyclone 10 GX
Transceivers
2.1. Transceiver Design IP Blocks
Note: Intel Cyclone 10 GX only supported with Intel Quartus Prime Pro Edition 17.1 and
future versions.
Figure 7. Cyclone 10 GX Transceiver Design Fundamental Building Blocks
Transceiver
PLL IP Core
Master/Local
Clock
Generation
Block
Avalon-MM Master
Reset Ports
Analog and Digital
Reset Bus
Reconfiguration
Registers
Avalon-MM
Interface
Non-Bonded and
Bonded Clocks Transceiver PHY IP Core (1)
Note:
Transceiver PHY
Reset Controller (2)
Legend:
Intel generated IP block
User created IP block
MAC IP Core /
Data Generator /
Data Analyzer
Parallel Data Bus
Avalon master allows access to Avalon-MM
reconfiguration registers via the Avalon
Memory Mapped interface. It enables PCS,
PMA , and PLL reconfiguration. To access
the reconfiguration registers, implement an
Avalon master in the FPGA fabric. This faciliates
reconfiguration by performing reads and writes
through the Avalon-MM interface.
Transceiver PLL IP core provides a clock source
to clock networks that drive the transceiver
channels. In Cyclone 10 devices, PLL IP Core
is separate from the transceiver PHY IP core.
Reset controller is used for resetting the
transceiver channels.
This block can be either a MAC IP core, or
a frame generator / analyzer or a
data generator / analyzer.
Transceiver PHY IP core controls the PCS and
PMA configurations and transceiver
channels functions for all communication
protocols.
(1) The Transceiver PHY IP core can be one of the supported PHY IP Cores ( For example: Native PHY IP Core).
(2) You can either design your own reset controller or use the Transceiver PHY Reset Controller.
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2.2. Transceiver Design Flow
Figure 8. Transceiver Design Flow
Generate PHY IP Core
Connect Transceiver Datapath to MAC IP Core or to a Data Generator / Analyzer
Select PLL IP Core
Generate the Transceiver PHY Reset Controller
or create your own User-Coded Reset Controller
Compile Design
Verify Design Functionality
Generate PLL IP Core
Configure the PHY IP Core
Select PHY IP Core
Configure the PLL IP Core
Connect PHY IP Core to PLL IP Core, Reset Controller, and
connect reconfiguration logic via Avalon-MM interface
Create reconfiguration logic
(if needed)
Make analog parameter settings to I/O pins using the Assignment Editor or updating the Quartus Prime Settings File
2.2.1. Select and Instantiate the PHY IP Core
Select the appropriate PHY IP core to implement your protocol.
Refer to the Cyclone 10 GX Transceiver Protocols and PHY IP Support section to decide
which PHY IP to select to implement your protocol.
You can create your Quartus Prime project first, and then instantiate the various IPs
required for your design. In this case, specify the location to save your IP HDL files.
The current version of the PHY IP does not have the option to set the speed grade.
Specify the device family and speed grade when you create the Quartus Prime project.
You can also instantiate the PHY IP directly to evaluate the various features.
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To instantiate a PHY IP:
1. Open the Quartus Prime software.
2. Click Tools ➤ IP Catalog.
3. At the top of the IP Catalog window, select Cyclone 10 GX device family
4. In IP Catalog, under Library ➤ Interface Protocols, select the appropriate PHY
IP and then click Add.
5. In the New IP Instance Dialog Box, provide the IP instance name.
6. Select Cyclone 10 GX device family.
7. Select the appropriate device and click OK.
The PHY IP Parameter Editor window opens.
Figure 9. Cyclone 10 GX Transceiver PHY Types
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2.2.2. Configure the PHY IP Core
Configure the PHY IP core by selecting the valid parameters for your design. The valid
parameter settings are different for each protocol. Refer to the appropriate protocol's
section for selecting valid parameters for each protocol.
2.2.3. Generate the PHY IP Core
After configuring the PHY IP, complete the following steps to generate the PHY IP.
1. Click the Generate HDL button in the Parameter Editor window. The
Generation dialog box opens.
2. In Synthesis options, under Create HDL design for synthesis select Verilog
or VHDL.
3. Select appropriate Simulation options depending on the choice of the hardware
description language you selected under Synthesis options.
4. In Output Directory, select Clear output directories for selected generation
targets if you want to clear any previous IP generation files from the selected
output directory.
5. Click Generate.
The Quartus Prime software generates a <phy ip instance name> folder, <phy ip
instance name>_sim folder, <phy ip instance name>.qip file, <phy ip instance
name>.qsys file, and <phy ip instance name>.v file or <phy ip instance name>.vhd
file. This <phy ip instance name>.v file is the top level design file for the PHY IP and is
placed in the <phy ip instance name>/synth folder. The other folders contain lower
level design files used for simulation and compilation.
Related Information
IP Core File Locations on page 67
For more information about IP core file structure
2.2.4. Select the PLL IP Core
Cyclone 10 GX devices have three types of PLL IP cores:
• Advanced Transmit (ATX) PLL IP core.
• Fractional PLL (fPLL) IP core.
• Channel PLL / Clock Multiplier Unit (CMU) PLL IP core.
Select the appropriate PLL IP for your design. For additional details, refer to the PLLs
and Clock Networks chapter.
To instantiate a PLL IP:
1. Open the Quartus Prime software.
2. Click Tools ➤ IP Catalog.
3. At the top of the IP Catalog window, select Cyclone 10 GX device family
4. In IP Catalog, under Library ➤ Basic Functions ➤ Clocks, PLLs, and Resets
➤ PLL choose the PLL IP ( Cyclone 10 GX fPLL, Cyclone 10 GX Transceiver
ATX PLL, or Cyclone 10 GX Transceiver CMU PLL) you want to include in your
design and then click Add.
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5. In the New IP Instance Dialog Box, provide the IP instance name.
6. Select Cyclone 10 GX device family.
7. Select the appropriate device and click OK.
The PLL IP GUI window opens.
Figure 10. Cyclone 10 GX Transceiver PLL Types
2.2.5. Configure the PLL IP Core
Understand the available PLLs, clock networks, and the supported clocking
configurations. Configure the PLL IP to achieve the adequate data rate for your design.
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