IXIA AFD2 User manual

Ixia Platform Reference Manual Manual, Release 6.30 15-1
15
Chapter 15: Ixia IRIG-B Auxiliary
Function Device
(AFD2)
The IXIA Auxiliary Function Device 2 (AFD2) provides the means for accurate
worldwide timing using Inter-Range Instrumentation Group (IRIG-B)
technology. The ADF2 decodes the GPS satellites and time information and
sends out a pulse to the Optixia chassis. The IXIA /AFD2 is shown in Figure 15-
1.
Figure 15-1. Ixia AFD2
The IXIA AFD2 with integrated IRIG-B is designed to provide 12.5 MHz GPS
clock with a programmable 80 ns sync pulse to the Optixia chassis.
The Ixia AFD2 IRIG-B receiver is controlled by an Ixia chassis through a USB
port. Chassis timing is provided by connecting the Sync Out of the AFD2 to the
Sync In of the chassis. This configuration then enables the chassis to operate as a
subordinate in a virtual chassis chain, with the Ixia AFD2 as the master.
Figure 15-2 on page 15-2 shows the AFD2 in operation with other chassis in a
local chassis chain. Multiple local chassis chains can be collected through IRIG-
B into a virtual chassis chain.

Ixia IRIG-B Auxiliary Function Device (AFD2)
15-2 Ixia Platform Reference Manual Manual, Release 6.30
15
Figure 15-2. AFD2 in a Chassis Chain
The IxExplorer GUI displays the status of the IRIG-B interface to the user.
Figure 15-3 shows the Chassis Properties dialog with status information. The
connection is determined to be either locked or unlocked. In the Locked state, the
chassis is locked to IRIG-B time within 150nS. In the unlocked state, the AFD2
IRIG-B hardware operates to lock its VCXO to 1PPS pulse.
The process of generating the Lock status for the AFD2 consists of getting IRIG-
B time lock and then synchronizing the internal clock to the IRIG-B 1PPS pulse.
The AFD2 does not enter the ‘Lock’ state until the VCXO lock condition is met.
In the unlocked state, the chassis in the unlocked chain are not accurately time-
synchronized to the rest of the chain.
In operation, once a chassis chain is constructed and the chassis are
synchronized, you can clear the timestamps to provide a baseline time for all
chassis in the chain. The chain operations are then locked until such time that the
IRIG-B lock is lost by a member of the chain. Data sent from one port in the
chain to another provides one-way latency measurements by subtraction of the
transmit time stamp from the receive time stamp.
For large or very remote chassis chains, the chassis chain properties provide an
offset delay. This delay is defaulted to 5 seconds. For chassis chains where the
communication delays are significant, as in worldwide or large chains, a longer
delay should be selected to allow for setup communication delays. The delay is
the time of a particular chassis operation (for example, start transmit, stop
transmit) plus the configured delay for any synchronous operation. When an
operation for the entire chain is executed, this delay is added to the operation. A
dialog opens indicating that the operation is in process when the delays are
significant.
The chassis time is taken from any chassis with a IRIG-B interface attached. The
setup for the chassis chain requires that all chassis in the chain be locked. This is
indicated in the IxExplorer GUI.
The critical operation for a virtual chain is the reset of the System Time Stamps.
All other actions are dependent on the synchronous execution of this operation.
Caution: A chassis connected to an AFD2 chassis does not operate properly if
set to Synchronous time source, unless the sync cable is disconnected.
Sync
Out
Sync
In
Sync
In
Ixia XM2
(slave)
Ixia XM2
(slave)
Ixia AFD2 IRIG-B
Receiver (master) Sync
Out
USB cable
provides power and COM3 channel
Customer’s IRIG
Receiver

Ixia Platform Reference Manual Manual, Release 6.30 15-3
Ixia IRIG-B Auxiliary Function Device (AFD2)
To reset time stamps for a IRIG-B-connected system, the reset operation needs to
be executed for the chassis chain, and not for the individual chassis.
Figure 15-3. Chassis Properties AFD2 - Time Source
.
Table 15-1. Chassis Properties, Time Source Tab
Section Field/Control Description
Time Source Synchronous
IRIG-B (AFD2)
IRIG-B Mode B000 B000 is straight TTL serial output (from
the IRIG-B receiver)
B120 B120 is amplitude modulation (AM) (from
the IRIG-B receiver)
IRIG-B Status Lock Status Locked = locked to IRIG-B 1PPS input
(from IRIG-B receiver)
UTC Time UTC Time (display only) in HH:MM:SS
comes from the IRIG-B receiver
Day Increments from 1 to 366
Control Flags These are vendor-specific flags that are
passed-through from the IRIG-B receiver
unless the sync cable is disconnected.
If set to Synchronous time source, a chassis
connected to IRIG-B does not operate properly

Ixia IRIG-B Auxiliary Function Device (AFD2)
AFD2 Setup
15-4 Ixia Platform Reference Manual Manual, Release 6.30
15
AFD2 Setup
The AFD2 Kit: The AFD2 kit comes with cables and items required to install and connect the
AFD2 in a lab. The AFD2 kit does not include the IRIG receiver and antenna for
permanent installation at a particular site.
The kit contains these items:
•AFD2 chassis
•AFD2 chassis rack mount ears
•3-foot sync cable
•6-foot USB cable
The AFD2 installation uses the USB cable for communication and power. The
Ixia chassis automatically detects the connections.
Successful IRIG-B
Synchronization in
IxExplorer
In the Chassis Properties dialog of IxExplorer, after selection of IRIG-B as the
timer source, the IRIG-B status is displayed. In Figure 15-3 on page 15-3, the
status is ‘locked’ to the 1PPS signal coming from the IRIG-B receiver. In the
chassis tree view of IxExplorer (Figure 15-4), the chassis status is shown as
‘IRIG-B Ready’ if it has successfully locked onto the 1PPS signal.
Figure 15-4. Chassis Tree View in IxExplorer
Enabling/Installing IRIG-B Based Synchronization
This procedure to set the time source needs to be followed only for the initial
installation of the AFD2 IRIG-B unit. Thereafter, upon subsequent restarts, the
chassis and AFD2 unit starts up fully operational.
1. Set up the antenna and IRIG-B receiver (not supplied by Ixia).
SBS Straight Binary Seconds from 1 to xxx
each day, starting at midnight. Resets to 0
each midnight.
FPGA Version FPGA version
Table 15-1. Chassis Properties, Time Source Tab
Section Field/Control Description

Ixia Platform Reference Manual Manual, Release 6.30 15-5
Ixia IRIG-B Auxiliary Function Device (AFD2)
Changing Time Source
2. Connect the 1PPS and IRIG-B outputs from the IRIG-B receiver to the
AFD2.
3. Connect the sync and USB cables between AFD2 and the Ixia chassis. On the
front panel of the AFD2,
•the Pwr OK indicator lights solid,
•the 1PPS indicator blinks to indicate the signal from the IRIG-B receiveris
good, and
•the Lock indicator lights solid.
4. Start the chassis. After starting completely, the IxExplorer resource tree is
displayed as shown in Figure 15-4 on page 15-4.
5. Note the message regarding timing source, as shown in Figure 15-5.
Figure 15-5. IxServer Start Log Before Attaching AFD2
Changing Time
Source
Any time the clock source is switched, IxServer must be restarted. When the
chassis is switched from Synchronous time source to IRIG-B, or vice-versa, the
following message is displayed as shown in Figure 15-6.
Figure 15-6. Time Source Change Detection Prompt
You are prompted to restart the IxServer. In this example, the time source was
changed from synchronous to IRIG-B.
1. Click OK and then manually restart IxServer.
IxServer restarts, then detects IRIG-B as the timing source and configure the
chassis as a subordinate, since the chassis is receiving its timing through sync
cable from the AFD2 IRIG-B source. The expected IxServer log messages
are shown in Figure 15-7 and Figure 15-8.
Figure 15-7. IxServer Log - IRIG-B AFD2 Detected
IRIG-B AFD2 is detected and COM6 port is indicated as the communication
channel between chassis and AFD2.

Ixia IRIG-B Auxiliary Function Device (AFD2)
Troubleshooting— IRIG-B Unit ‘Not Ready’
15-6 Ixia Platform Reference Manual Manual, Release 6.30
15
Figure 15-8. IxServer Log - Chassis Configured as Slave to AFD2
The chassis is configured as a subordinate to AFD2.
Troubleshooting—
IRIG-B Unit ‘Not
Ready’
If, after completing installation by following the steps above, there is no IRIG-B
information and the status is ‘Unlocked’ in the Time Sources tab of Chassis
Properties in IxExplorer (Figure 15-3 on page 15-3), then one of the following
conditions needs to be corrected.
1PPS signal is not connected: check cabling between AFD2 and the IRIG-B
receiver.
IRIG-B Mode B000 has been selected, but the IRIG-B receiver is sending
B120 signal (or vice versa): change the selection in the Time Sources tab of
Chassis Properties in IxExplorer (Figure 15-3 on page 15-3), and see if the
status is corrected (‘Locked’) after a short interval.

Ixia Platform Reference Manual Manual, Release 6.30 15-7
Ixia IRIG-B Auxiliary Function Device (AFD2)
Worldwide Synchronization
Worldwide Synchronization
Two or more Ixia chassis connected to a time reference may be distributed
worldwide forming a virtual chassis chain based on IRIG-B and/or CDMA
timing. One possible configuration is shown in Figure 15-9 on page 15-7.
Figure 15-9. Worldwide Deployment of Synchronized Chassis
The ports on all of the chassis may be shared by one or more Ixia software users
located likewise anywhere in the world. Where IRIG-B and CDMA sources are
used, all of the sources must have good quality time values in order for the trigger
to be transmitted.
Once the timing features of the chassis is configured, operating a worldwide set
of Ixia chassis is the same as local operation. The Ixia hardware and software
program the clocks such that they all send a master trigger pulse to all Ixia
chassis, within a tolerance of ±150 ns with IRIG-B and ±100 us for CDMA.
Ixia chassis timing operates by resetting at a fixed time-of-day on all chassis
from one source, and then maintaining the time accuracy through various

Ixia IRIG-B Auxiliary Function Device (AFD2)
Calculating Latency Accuracy for AFD2 (IRIG-B)
15-8 Ixia Platform Reference Manual Manual, Release 6.30
15
different means. Table 15-2 on page 15-8 describes the full set of options
available and their approximate relative accuracies.
Calculating Latency
Accuracy for AFD2
(IRIG-B)
Use the following calculation for latency accuracy for AFD2 ( IRIG-B ) setups.
Latency A to B = Lab
Latency B to A = Lba
Transmit path A to B = T1
Transmit path B to A = T2
Time at A = Ta
Time at B = Tb
Time Absolute = T
Time Error at any site = Terr
Lab=Ta+T1-Tb
Lba=Tb+T2-Ta
Delta L = Lab – Lba
Delta L = Ta+T1-Tb – ( Tb+T2-Ta )
Delta L = T1-T2+2( Ta-Tb )
Delta L = 2(Ta – Tb)
If Ta = T+/-Terr and Tb = T+/-Terr
Then
Delta L= 2(T+/-Terr – T+/-Terr)
Delta L= 2( |Terr|+|Terr|)
Delta L = 4Terr
Table 15-2. Summary of Timing Options
Available on
Devices
Timing Option Time of Day
Accuracy
Frequency
Source
Frequency Accuracy
All Chassis IRIG-B/GPS 150 nanoseconds
from GMT
Ixia AFD2 Stratum 1
Ixia 100, 400T,
1600T
Synchronous N/A Internal PC clock 1 microsecond/second
Ixia 250 CDMA 100 microseconds
from GMT
CDMA Stratum 2
Ixia 100 CDMA in-built 100 microseconds
from GMT
CDMA Stratum 2
Ixia 100 GPS in-built 150 nanoseconds
from GMT
GPS Stratum 1

Ixia Platform Reference Manual Manual, Release 6.30 15-9
Ixia IRIG-B Auxiliary Function Device (AFD2)
Front Panel LEDs
Front Panel LEDs
The AFD2 has the following front panel LEDs:
IXIA AFD2 Specifications
The IXIA AFD2 specifications are contained in Table 15-4 on page 15-9.
Table 15-3. AFD2 LEDs
Label Color Description
USB Green Indicates that the connection is enabled, and glows
solid with USB activity.
1PPS Green Indicates that the ‘1 Pulse Per Second’ heartbeat is
being generated by the IRIG-B hardware.
Pwr OK Green The AFD2 power has been validated.
Lock Green Indicates that the internal PLL has locked to the
1PPS signal. Testing is invalidated if the IRIG-B
Lock signal is not illuminated.
Table 15-4. Ixia AFD2 Specifications
General
Physical
Size 9.6"x7"x2.9" ( with feet, 2.70" without feet)
Weight 3.15 lb
Avg. Shipping Wt. 6 lbs
Shipping Vibration FED-STD-101C, Method 5019.1/5020.1
Environmental
Temperature
Operating 41°F to 122°F, ( 5 °C to 50°C)
Storage 41°F to 122°F, ( 5°C to 50°C)
Power Worst case power = 2.5W
5V regulated source
Humidity
Operating 0% to 85%, non-condensing
Storage 0% to 85%, non-condensing

Ixia IRIG-B Auxiliary Function Device (AFD2)
IXIA AFD2 Specifications
15-10 Ixia Platform Reference Manual Manual, Release 6.30
15
IRIG-B Functionality Bit rate is 100 pps and frame rate is 1fps for both
code formats. 1pps pulse provides the precise time
refrence.
IRIGB000 DC level shift, pulse width coded with BCD,
CF(control functions), SBS
IRIGB120 1kHz carrier sine wave amplitude modulated with
BCD, CF (control functions), SBS
Clock 12.5 Mhz GPS System clock
Pulse Width 80 ns
Rear Panel Switches Reset switch
Front Panel Indicators USB, 1PPS, Pwr OK, Lock
Front Panel Connectors
USB Port Type B
Sync Out RJ14
Back Panel Connectors
IRIG-in BNC, IRIG-B code in
1PPS-in BNC, 1PPS pulse in
Power (not used) 2.0mm Power jack
Table 15-4. Ixia AFD2 Specifications