JRC NJU26209 User manual

NJU26209
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Ver.2008-12-04
DAEP Decoder
 General Description
The NJU26209 is a digital signal processor that provides the function of DAEP (Dolby
Automotive Entertainment Program).
A location of sound image forward is possible without a center speaker by all seats in the
car.
The applications of NJU26209 are suitable for Car Audio, Car Navigation system and other
audio products.

Features
-Software
 DAEP (Dolby Automotive Entertainment Program)
Pro Logic II
Automotive (Advanced Surround Fader, Center Image Control)
Bass Management
Time Alignment
 Master Volume

Input Trim

Channel Trim
-Hardware
 24bit Fixed-point Digital Signal Processing
 Maximum Clock Frequency : 12.288MHz(Standard), built-in PLL Circuit
 Digital Audio Interface : 4 Input ports / 4 Output ports
 Digital Audio Format : I
2
S 24bit, left-justified, right-justified, BCK : 32fs/64fs
 Master / Slave Mode
 Microcomputer Interface
I
2
C Bus (Standard-mode/100kbps, Fast-mode/400kbps)
4-Wire Serial Bus (4-Wire: Clock, Enable, Input data, Output data)
 Operating Voltage : V
DD
=V
DDPLL
= 1.8V
: V
DDIO
= 3.3V
 Input Terminal : +5.0V Input tolerant
 Package : SSOP44 (Pb-Free)
* The detail hardware specification of the NJU26209 is described in the “ NJU26200 Series Hardware Data Sheet”.
■ Package
NJU26209V

NJU26209
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Ver.2008-12-04
 Hardware Block Diagram
Fig. 1 NJU26209 Hardware Block Diagram
SD
SDSD
SDO
OO
O1
11
1
SERIAL
SERIALSERIAL
SERIAL
HOST
HOSTHOST
HOST
INTERFACE
INTERFACEINTERFACE
INTERFACE
AD1/SDIN
AD1/SDINAD1/SDIN
AD1/SDIN
AD2/SSb AD2/SSbAD2/SSb
AD2/SSb
SCL/SCK
SCL/SCKSCL/SCK
SCL/SCK
SDA/SDOUT
SDA/SDOUTSDA/SDOUT
SDA/SDOUT
RESETb
RESETbRESETb
RESETb
MCK
MCKMCK
MCK
CLK
CLKCLK
CLK
CLKOUT
CLKOUTCLKOUT
CLKOUT
TIMING
TIMINGTIMING
TIMING
GENERATOR
GENERATORGENERATOR
GENERATOR
/ PLL
/ PLL/ PLL
/ PLL
DATA
DATADATA
DATA
RAM
RAMRAM
RAM
FIRMWARE
FIRMWAREFIRMWARE
FIRMWARE
ROM
ROMROM
ROM
PROGRAM
PROGRAMPROGRAM
PROGRAM
CONTROL
CONTROLCONTROL
CONTROL
ALU
ALUALU
ALU
ADDR
ADDRADDR
ADDRESS
ESSESS
ESS GENERATION
GENERATIONGENERATION
GENERATION UNIT
UNITUNIT
UNIT
24
2424
24-
--
-BIT
BITBIT
BIT ｘ
ｘｘ
ｘ 24
2424
24-
--
-BIT
BITBIT
BIT
MULTIPLIER
MULTIPLIERMULTIPLIER
MULTIPLIER
DSP
DSPDSP
DSP ARITHMETIC
ARITHMETICARITHMETIC
ARITHMETIC UNIT
UNITUNIT
UNIT
BCK
BCKBCK
BCKO
OO
O
SERIAL
SERIALSERIAL
SERIAL AUDIO
AUDIOAUDIO
AUDIO
INTERFACE
INTERFACEINTERFACE
INTERFACE
LRO
LROLRO
LRO
BCKI
BCKIBCKI
BCKI
LRI
LRILRI
LRI
General I/O
General I/OGeneral I/O
General I/O
INTERFACE
INTERFACEINTERFACE
INTERFACE SEL
SELSEL
SEL
L/Rout
L/RoutL/Rout
L/Rout
SDI
SDISDI
SDI0~3
0~30~3
0~3
In
InIn
Input
putput
put
WDC
WDCWDC
WDC
SDO
SDOSDO
SDO2
22
2
C/SW
C/SWC/SW
C/SWout
outout
out
SDO
SDOSDO
SDO3
33
3
LM/RMout
LM/RMoutLM/RMout
LM/RMout
PROC
PROCPROC
PROC
MUTEb
MUTEbMUTEb
MUTEb
SDO
SDOSDO
SDO0
00
0
L
LL
LB
BB
B/R
/R/R
/RB
BB
Bout
outout
out

NJU26209
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 Function Block Diagram
Fig. 2 Function Block Diagram (Firmware)
Advanced Fader /
Mixer
Master Volume &
Channel Trim
Pro Logic II
5ch
Input Trimmer
Pro Logic II
3ch
SDI0
SDO2
SDO1
SDI3
SDI2
SDI1
C/SW
L/R
LS/RS
Phantom Center
Bass
Management
RS
LS
C
LFE
L
R
RS
LS
C
L
R
CPLII
RS
LS
C
L
R
LM
RM
RS
LS
C
L
R
LM
RM
RS
LS
C
L
R
LM
RM
SW
RS
LS
C
L
R
LM
RM
SW
SDO3
SDO0
DAEP
Tim e
Alignment
Tim e
Alignment
Tim e
Alignment
Tim e
Alignment
Tim e
Alignment

NJU26209
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Ver.2008-12-04
 Pin Configuration
Fig. 3 NJU26209 Pin Configuration
NJU26209
SSOP44
44
43
42
41
40
39
38
37
1
2
3
4
5
6
7
8
9
10
11
12
VDD
VSS
VSSIO
VDDIO
SDO0
SDO1
SDO2
SDO3
SDI3
SDI2
SDI1
SDI0
LRI
VDDIO
BCKI
VSS
VDD
TEST
MUTEb
WDC
13
14
15
16
PROC
VSSIO
VDDIO
SEL
36
35
34
33
LRO
BCKO
MCK
VDDIO
17
18
19
20
VDDPLL
VSSPLL
VSS
VDD
21
22
CLKOUT
CLK
32
31
30
29
SDA/SDOUT
SCL/SCK
AD2/SSb
AD1/SDIN
28
27
26
25
TEST
TEST
TEST
RESETb
24
23
VDDIO
VSSIO

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 Pin Description
Table 1 Pin Description
Pin No. Symbol I/O Function
1 SDI3 I Audio Data Input ch.3 (LS/RS)
2 SDI2 I Audio Data Input ch.2 (C/SW)
3 SDI1 I Audio Data Input ch.1 (L/R)
4 SDI0 I Audio Data Input ch.0 (L/R)
5 LRI I LR Clock Input
6 VDDIO - I/O Power Supply +3.3V
7 BCKI I Bit Clock Input
8 VSS - DSP Core Power Supply GND
9 VDD - DSP Core Power Supply +1.8V
10 TEST * I
for test
connect with VSSIO through 3.3-ohm resistance.
11 MUTEb * I Master Volume Status after reset ‘1’: 0dB, ‘0’: Mute
12 WDC * OD Watchdog Clock output pin (Open drain output)
13 PROC * I
Signal Processing after reset ‘1’: Normal Processing, ‘0’: Waiting for a
Command without Processing
14 VSSIO - I/O Power Supply GND
15 VDDIO - I/O Power Supply +3.3V
16 SEL I Host Interface Selection ‘1’: Serial Interface, ‘0’: I
2
C bus
17 VDDPLL - PLL Power Supply +1.8V
18 VSSPLL - PLL Power Supply GND
19 VSS - DSP Core Power Supply GND
20 VDD - DSP Core Power Supply +1.8V
21 CLKOUT O OSC Clock Output
22 CLK I OSC Clock Input (12.288MHz)
23 VSSIO - I/O Power Supply GND
24 VDDIO - I/O Power Supply +3.3V
25 RESETb I Reset (RESETb=’0’: DSP Reset)
26 TEST I for test (connect to VDDIO)
27 TEST I for test (connect to VSSIO)
28 TEST I for test (connect to VSSIO)
29 AD1/SDIN I I
2
C Address (I
2
C mode) / Serial In (4-wire serial mode)
30 AD2/SSb I I
2
C Address (I
2
C mode) / Serial enable (4-wire serial mode)
31 SCL/SCK I I
2
C SCL (I
2
C mode) / Serial clock (4-wire serial mode)
32 SDA/SDOUT I/O I
2
C SDA (I
2
C mode) / Serial Out (4-wire serial mode)
33 VDDIO - I/O Power Supply +3.3V
34 MCK O A/D, D/A clock output (buffer output of a CLK pin)
35 BCKO O Bit Clock Output
36 LRO O LR Clock Output
37 SDO3 O Audio Data Output ch.3 (LM/RM)
38 SDO2 O Audio Data Output ch.2 (C/SW)
39 SDO1 O Audio Data Output ch.1 (L/R)
40 SDO0 O Audio Data Output ch.0 (LS/RS)
41 VDDIO - I/O Power Supply +3.3V
42 VSSIO - I/O Power Supply GND
43 VSS - DSP Core Power Supply GND
44 VDD - DSP Core Power Supply +1.8V
Note : I : Input
O : Output
OD : Open Drain Output
I/O : Bi-directional
Pins symbol with * : Connect with VDDIO or VSSIO through 3.3kΩresistance

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 Audio Interface
The NJU26209 audio interface provides industry serial data formats of I
2
S, MSB-first Left-justified or MSB-first
Right-justified. The NJU26209 audio interface provides four data inputs, SDI0, SDI1, SDI2 and SDI3, and four data
outputs, SDO0, SDO1, SDO2 and SDO3 as shown in table 2 and 3. The input serial data is selected by the firmware
command.
Table 2 SerialAudio Input Pin
Description
Pin No. Symbol Stereo input Multi channel input
4 SDI0
3 SDI1
Audio Data Input (L/R)
(SDI0/SDI1 pin select)
Audio Data Input (L/R)
(SDI0/SDI1 pin select)
2 SDI2 None Audio Data Input 2 (C/SW)
1 SDI3 None Audio Data Input 3 (LS/RS)
Table 3 SerialAudio Output Pin
Pin No. Symbol Description
40 SDO0 Audio Data Output 0 (LS/RS)
39 SDO1 Audio Data Output 1 (L/R)
38 SDO2 Audio Data Output 2 (C/SW)
37 SDO3 Audio Data Output 3 (LM/RM)
 Host Interface
The NJU26209 can be controlled via Serial Host Interface (SHI) using either of two serial bus formats : I
2
C bus or
4-Wire serial bus. Data transfers are in 8 bits packets (1 byte) when using either format. The SHI operates only in a
SLAVE fashion. A host controller connected to the interface always drives the clock (SCL / SCK) line and initiates data
transfers, regardless of the chosen communication protocol.
The detail I
2
C bus and 4-Wire Serial bus information are described in the ‘NJU26200 Series Hardware Data
Sheet’.
Table 4 Serial Host Interface Pin Descriptions
Pin No. Symbol Setting Host Interface
Low I
2
C Bus Interface
16 SEL High 4-Wire Serial Interface
Table 5 Serial Host Interface Pin Description
Pin No.
Symbol
(I
2
C /Serial) I
2
C bus Interface 4-Wire Serial Interface
29 AD1/SDIN I
2
C Address Select Bit1 Serial data input
30 AD2/SSb I
2
C Address Select Bit2 Slave select
31 SCL/SCK Serial Clock Serial Clock
32 SDA/SDOUT Serial Data Input/Output
(Open Drain output)
Serial data output
(CMOS Output)
Note: When I
2
C Bus is selected, this pin is a bi-directional Open Drain output. This pin, which is assigned for I
2
C Bus,
requires a pull-up resistance.
When 4-Wire Serial bus is selected, the SDA/SDOUT pin is CMOS output.
The SDA/SDOUT pin isn’t 5.0V Input tolerant.

NJU26209
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Ver.2008-12-04
 I
2
C Bus
When the NJU26209 is configured for I
2
C bus communication in SEL=”Low”, the serial host interface transfers
data on the SDA pin and clocks data on the SCL pin. The SDA is an open drain pin requiring a pull-up resistance.
Pins AD1 and AD2 are used to configure the seven-bit SLAVE address of the serial host interface. (Table 6)
Table 6 I
2
C Bus Interface Slave address
* SLAVE address is 0 when AD1/2 is “Low”. SLAVE address is 1 when AD1/2 is “High”.
* SLAVE address is 0 when R/W is “W”. SLAVE address is 1 when R/W is “R”.
Note:
Both “
Standard-Mode (100kbps)” and “Fast-Mode (400kbps)” data transfer rate are supported.
 4-Wire Serial Interface
The serial host interface can be configured for 4-Wire Serial bus communication by setting SEL1=”High” during the
Reset Sequence initialization. SHI bus communication is full-duplex; a write byte is shifted into the SDIN pin at the
same time that a read byte is shifted out of the SDOUT pin.
Data transfers are MSB first and are enabled by setting SSb = “Low”. Data is clocked into SDIN on rising
transitions of SCK. Data is latched at SDOUT on falling transitions of SCK except for the first byte(MSB) which is
latched on the falling transitions of SSb. SDOUT is always CMOS output. SDOUT does not require a pull-up
resistance.
Fig. 4 4-Wire Serial Interface Timing
Note : When the data-clock is less than 8 clocks, the input data is shifted to LSB side and is sent to the DSP core at the
transition of SSb=”High”.
When the data-clock is more than 8 clocks, the last 8 bit data becomes valid.
After sending LSB data, SDOUT transmits the MSB data which is received via SDIN until SSb becomes “High”.
bit7 bit6 bit5 bit4 bit3
AD2
bit2
AD1
bit1
R/W
bit0
0 0 1 1 1 0 0
0 0 1 1 1 0 1
0 0 1 1 1 1 0
0 0 1 1 1 1 1
R/W
Start
bit
R/W
bit ACK
Slave Address
(
7bit
)
SDIN
SDOUT
SCK
SSb
bit5 bit1
bit7 bit0
bit6
bit1bit7 bit0bit6 bit5
unstable
unstable
MSB LSB

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 Pin setting
The NJU26209 operates default command setting after resetting the NJU26209. In addition, the NJU26209
restricts operation at power on by setting PROC pin and MUTEb pin. These pins are input pin. However, these pins
operate as bi-directional pins. Connect with V
DDIO
or V
SSIO
through 3.3kΩresistance.
Table 7 Pin setting
Pin No. Symbol Setting Function
“High” The NJU26209 operates default setting after reset.
13 PROC
“Low” The NJU26209 does not operate after reset. Sending start
command is required for starting operation.
“High” Master volume is set 0dB after reset.
11 MUTEb
“Low” Master volume is set mute after reset.
 WatchDog Clock
The NJU26209 outputs clock pulse through WDC (Pin No.12) during normal operation. The WDC clock is useful
to check the status of the NJU26209 operation. For example, a microcomputer monitors the WDC clock and checks
the status of the NJU26209. When the WDC clock pulse is lost or not normal clock cycle, the NJU26209 does not
operate correctly. Then reset the NJU26209 and set up the NJU26209 again. The WDC clock is able to be variable
for 0msec to 100msec by command. Default setting of WDC clock is 100msec.
The WDC pin is open drain output. The WDC pin setting (Table 8)
Table 8 WDC pin setting
Note: The cycle of WDC output is rough. Because WDC output inserts in the process of sound processing.
In slave mode, when there is no input of BCKI/LRI, WDC can’t output.
It is required to set up a sampling rate correctly.
Pin No. Symbol Setting
WDC pin is used. Connect with V
DDIO
through 3.3k Ω resistance.
12 WDC
WDC pin is not used. Connect with V
SSIO
through 3.3k Ω resistance.
Do not open WDC pin.

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 Firmware Command Table
Host processor can control the NJU26209 via I
2
C bus or 4-Wire serial bus interface. The following table
summarizes the available user commands.
Table 9 Command Table
No. Command Description
1 Set Task Command
2 System State Command
3 Sample rate Select Command
4 Smooth Control Config Command
5 Master Volume Control Command
6 Channel Trim Control Command
7 Input Trim Control Command
8 DAEP Balance Control Command
9 DAEP Phantom Center Config Command
10 Pro Logic II Shelf Filter Config Command
11 Bass Management Config Command
12 Bass Management LFE Trim Command
13 Bass Management Center Trim Command
14 Bass Management L/R Trim Command
15 Bass Management LS/RS Trim Command
16 Front Delay Control Command
17 Middle Delay Control Command
18 Surround Delay Control Command
19 Center Delay Control Command
20 Subwoofer Delay Control Command
21 PNG Mode Command
22 Firmware Version Number Request Command
23 DSP Reset Command
24 Start Command
25 Nop Command
Notes : In respect to detail command information, request New Japan Radio Co., Ltd. and permission of a
licenser (Dolby) is required.

Response of status
NJU26209 returns the response of 4 types to the host controller.
Table 10 Response of status
Response Command Remark
Status : Command Accepted 0x80
Reception OK
Status : Command Error 0x81
Reception ERROR
Status : Command Process
0x82 Command processing
Status : Not Ready 0x83 Initialization

NJU26209
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 License Information
The Word “DOLBY”, “Pro Logic II”, DAEP and the double D mark are trademarks of Dolby Laboratories.
The NJU26209 can only be delivered to licensees of Dolby Laboratories.
Please refer to the licensing application manual issued by Dolby Laboratories.
[CAUTION]
The specifications on this databook are only
given for information , without any guarantee
as regards either mistakes or omissions. The
application circuits in this databook are
described only to show representative usages
of the product and not intended for the
guarantee or permission of any right including
the industrial rights.