JVC KD-LX333R User manual

SERVICE MANUAL
CD RECEIVER
No.49715
Jun. 2002
COPYRIGHT 2002 VICTOR COMPANY OF JAPAN, LTD.
KD-LX333R
KD-LX333R
Area Suffix
E
EX
Continental Europe
Central Europe
Contents
Safety precaution
Preventing static electricity
Disassembly method
Adjustment method
1-2
1-3
1-4
1-13
1-14
1-16
1-16
1-17~33
Flow of finctional operation intil opelation
until TOC read
Maintenance of laser pickup
Replacement of laser pickup
Description of Major ICs
KD-LX333R
10
7 8
9
11
12
OFF
STDM
ATT
SOURCE

KD-LX333R
1-17
Descri
p
tion of ma
j
or ICs
Micro-
controller
interface
Audio output
circuit Digital output
16k
RAM
Address
circuit
1-bit
DAC Servo control
Clock
generator
LPF
PWM D/A
A/D
ROM
CLV servo
Sync signal
protection
EFM
Sub code
detector
Data
slicer
VCO
PLL
TMAX
Digital equalizer
automatic
adjustment circuit
RAM
Correction
circuit
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
BCK
LRCK
AOUT
DOUT
IPF
V
DD3
V
SS3
SBOK
CLCK
DATA
SFSY
SBSY
/HSO
/
UHSO
PV
DD3
PDO
VXDD3 XO XI XV
SS3
TEIN V
DD3
V
SS3
DMO FMO AV
DD3
SEL TEBC RFGC V
REF
TRO FOO
DV SS3
RO
DV
DD3
DVR
LO
DV
SS3
ZDET
V
SS5
BUS0
BUS1
BUS2
BUS3
BUCK
/CCE
/RST
V
DD5
TEZI
TEI
SBAD
FEI
RFRP
RFZI
RFCT
AV
DD3
RFI
SLCO
AV
SS3
VCOF
RV
REF
LPFO
LPFN
TMAX
TC9490FA (IC521) : DSP & DAC
1.Pin layout & Block daiagram

KD-LX333R
1-18
2.Pin function (1/2)
I/O
O
O
O
O
O
-
-
O
I/O
O
O
O
O
O
-
O
O
I
O
-
O
-
O
I
-
I
I
I
I
I
I
I
O
O
-
Function
Bit clock outputpin 32fs, 48fs, or 64fs selectable by command.
L/R channel clock output pin."L" for L channe and "H" for R channel.
Output polarity can be inverted by command.
Audio data output pin. MSB-first or LSB-first selectable by command.
Digital data output pin. Outputs up to double-speed playback.
Correction flag output pin.When set to "H",AOUT output cannot be corrected
by C2 correction processing.
Digital 3.3V power supply voltage pin.
Digital GND pin.
Subcode Q data CRCC result output pin."H" level when result is OK.
Subcode P-W data read clockI/O pin.I/O polarity selectable by command.
Subcode P-W data output pin.
Playback frame sync signal output pin.
Subcode block sync signal output pin."H" level at S1 when subcode sync is
detected.
Playback speed mode flag output pins.
PLL-only 3.3V power supply voltage pin.
EFM and PLCK phase difference signal output pin.
TMAX detection result output pin.
Inverted input pin for PLL LPF amp.
Output oin for PLL LPF amp.
PLL-only VREF pin.
VCO filter pin.
Analog GND pin.
DAC output pin for data slice level generation.
RF signal input pin.Zin selectable by command.
Analog 3.3V power supply voltage pin.
RFRP signal center level input pin.
RFRP signal zero-cross input pin.
RF ripple signal input pin.
Focus error signal input pin.
Sub-beam adder signal input pin.
Tracking error input pin. Inputs when tracking servo is on.
Tracking error signal zero-cross input pin.
Focus equalizer output pin.
Tracking equalizer output pin.
Analog reference power supply voltage pin.
Symbol
BCK
LRCK
AOUT
DOUT
IPF
VDD3
VSS3
SBOK
CLCK
DATA
SFSY
SBSY
/HSO
/UHSO
PVDD3
PDO
TMAX
LPFN
LPFO
PVREF
VCOF
AVSS3
SLCO
RFI
AV
RFCT
RFZI
RFRP
FEI
SBAD
TEI
TEZI
FOO
TRO
VREF
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
TC9490FA(2/3)
Playback speed/UHSO /HSO
H
H
L
--
H
L
L
--
Normal
Double
4 times
---
TMAX OutputTMAX Detection result
Longer than fixed period
Within fixed period
Shorter than fixed period
"PVDD3"
"HIZ"
"AVSS3"

KD-LX333R
1-19
2.Pin function (2/2)
I/O
O
O
O
-
O
O
-
-
I
-
I
O
-
-
O
-
-
O
-
O
-
I/O
I
I
I
-
Function
RF amplitude adjustment control signal output pin.
Tracking balance control signal output pin.
APC circuit ON/OFF signal output pin. At laser on,high impedance with
UHS="L" ,H output with UHS="H".
Analog 3.3V power supply voltage pin.
Feed equalizer output pin.
Disc equalizer output pin.
Digital GND pin.
Digital 3.3V power supply voltage pin.
Test input pin. Normally,fixed to "L".
System clock oscillator GND pin.
System clock oscilatoe input pin.
System clock oscillator output pin.
System clock oscillator 3.3V power supply voltage pin.
DA converter GND pin.
R-channel data forward output pin.
DA converter 3.3V power supply pin.
Reference voltage pin.
L-channel data forward output pin.
DA converter GND pin.
1 bit DA converter zero data detection flag output pin.
Microcontroller interface GND pin.
Microcontroller interface data I/O pins.
Microcontroller interface clock input pin.
Microcontroller interface chip enable signal input pin.At "L".
Bus0 to BUS3 are active.
Reset signal input pin. At reset,"L".
Microcontroller interface 5V power supply pin.
Symbol
RFGC
TEBC
SEL
AVDD3
FMO
DMO
VSS3
VDD3
TESIN
XVSS3
XI
XO
XVDD3
DVSS3
RO
DVDD3
DVR
LO
DVSS3
ZDET
VSS5
BUS0
BUS1
BUS2
BUS3
BUCK
/CCE
/RST
VDD5
Pin No.
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
TC9490FA(3/3)
8
7
6
5
4
3
2
1V+
B OUTPUT
B INPUT
B INPUT
A INPUT
A INPUT
A OUTPUT
-
V-+
+-
NJM4565MD (IC151,IC171,IC323) : Operational amp

KD-LX333R
1-20
20k 20k
20k
20k
20k
180k
60k
15pF 1
k
x0.5
x0.5
1.75k
240k
15pF
14k 2k
1k
2k 50k
x2
x2
240k
60k
80k
80k
20k
20k
180k
40pF
40pF
3k
3k
12k
12k
15k
50 A
10pF
20 A
40k
20k
20k 20k
50k
PEAK
15k
10pF
40k
60 A
1.3V
BOTTOM
PEAK
40k
30k
13GVSW
VRO
FEO
FEN
RFRP
RFRPIN
RFGO
RFGC
AGCIN
RFO
RFN
GND
14
15
16
17
18
19
20
21
22
23
24
12 RFDC
TEO
TEN
TEBC
SEL
LDO
MDI
TNI
TPI
FPI
FNI
Vcc
11
10
9
8
7
6
5
4
3
2
1
TA2147F-X (IC501) : RF amp.
1.Terminal layout
2.Block diagram

KD-LX333R
1-21
3.Pin function
I/O
-
I
I
I
I
I
O
I
I
I
O
O
I
O
O
I
O
I
O
I
I
O
I
-
Function
3.3V Power supply pin
Main-beam amp input pin
Main-beam amp input pin
Sub-beam amp input pin
Sub-beam input pin
Monitor photo diode amp input pin
Laser diode amp output pin
APC circuit ON/OFF control signal,laser diode (LDO) control signal input or
bottom/peak detection frequency change pin.
Tracking error balance adjustment signal pin
Adjusts TE signal balance by eliminating carrier component from
PWM signal(3-state output, PWM carrier = 88.2kHz) output from
TC9490F/FA TEBC pin using RC-LPF and inputting DC.
TEBC input voltage:GND~Vcc
Tracking error signal generation amp negative-phase input pin
Tracking error signal generation amp output pin.
Combining TEO signal and RFRP signal with TC9490F/FA configures
tracking search system.
RF signal peak detection output pin
AGC/FE/TE amp gain change pin
Reference voltage (VRO) output pin *VRO = 1/2 Vcc when Vcc = 3.3V
Focus error signal generation amp output pin
Focus error signal generation amp negative-phase input pin
Signal amp output pin for track count
Combining RFRP signal TEO signal with TC9490F/FA configures tracking
search system.
Signal generation amp input pin for track count
RF signal amplitude adjustment amp output pin
RF amplitude adjustment control signal input pin
Adjusts RF signal amplitude by eliminating carrier component from PWM
signal (3-state output, PWM carrier = 88.2kHz) output from TC9490F/FA
RFGC pin using RC-LPF and inputting DC.
*RFGC input voltage :GND-Vcc
RF signal amplitude adjustment amp input pin
RF signal generation amp output pin
RF signal generation amp input pin
GND pin
Symbol
Vcc
FNI
FPI
TPI
TNI
MDI
LDO
SEL
TEBC
TEN
TEO
RFDC
GVSW
VRO
FEO
FEN
RFRP
RFRPIN
RFGO
RFGC
AGCIN
RFO
RFN
GND
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
LDOSEL
GND OFF
HIZ
Vcc ON
ON
Connected to Vcc
through 1k resistor
Control signal output
Control signal output
APC
circuit
ModeGVSW
GND
HIZ
Vcc
CD-RW
CD-DA
CD-DA

KD-LX333R
1-22
TA8273H (IC941) : Power amp
11
6 20
1
4
10
15
25
13
14
16
12
9
8
5
7
2
22
17
19
18
21
23
24
3
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
INRF
INRR
ST BY
Vcc 1/2 Vcc 3/4
OUT RF+
OUT RF-
GND
OUTRR+
OUTRR-
GND
REF
INLF
INLR
PRE GND
ON TIME Muting &
ON Time Control
Circuit
Protective
circuit
Protective
circuit
Mute
circuit
Ripple
Filter
Stand by
Switch
AC CONT2
+
+
0.22 F
2200 F 0.022
F
0.22 F
AC CONT1
+5V
ST ON
+
+
+
+
47 F
0.22 F
0.22 F
22 F
+
Mute 10K
+
3.3 F
OUTLF+
OUTLF-
Low Level
Mute ON
GND
OUTLR+
OUT LR-
GND
1.Block diagram

KD-LX333R
1-23
2.Terminal layout
3.Pin function TA8273H
AC CONT 1
GND
OUTRR-
STBY
OUTRR+
VCC1/2
OUTRF-
GND
OUTRF+
REF
INRF
INRR
PREGND
INLR
INLF
ONTIME
OUTLF+
GND
OUTLF-
VCC3/4
OUTLR+
MUTE
OUTLR-
GND
AC CONT 2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
SymbolPin No. Function
Header of IC
Power GND
Outpur(-) for Rear Rch
Stand by input
Output (+) for Rear Rch
Power input
Output (-) for Front Rch
Power GND
Output (+) for Front Rch
Ripple filter
Front Rch input
Rear Rch input
Signal GND
Rear Lch input
Front Lch input
Power on time control
Output (+) for Front Lch
Power GND
Output (-) for Front Lch
Power input
Output (+) for Rear Lch
Muting control input
Output (-) for Rear Lch
Power GND
Header of IC

KD-LX333R
1-24
UPD784217AGC168 (IC701) : Main micon
1.Pin layout
2.Pin functions(1/3)
1
~
25
75
~
51
100 ~ 76
26 ~ 50
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
I/O
I
I
I
I
O
O
O
O
-
-
-
-
-
-
I
I
I
I
I
I
I
I
-
-
I
I
I
I
I
I
I
I
-
O
O
-
I
O
I/O
I
O
O
Function
CD mechanical switch 2 detection signal input
CD mechanical switch 3 detection signal input
CD mechanical switch 4 detection signal input
Rest switch detection signal input
Motor signal control signal output at loading
Motor signal control signal output at leject
DIMMER pulse control output
POWER ON:H,FLAT PANEL:L
5V
GND
Reset detection teaminal
CD mechanical switch 1 detection signal input
J-BUS int
POWER SAVE2. Operating together with BACKUP.H input:STOP
Pulse signal for CRUISE input(only in 330R)
RDS clock input
RDS data input
Remocon input(111R:READY)
5V
5V
Temperature detection input
Key input 0
Key input 1
Key input 2
Level meter input
MRC output voltage detection
S.QUALITY level input
S.METER level input
GND
Subwoofer volume control analog output
Dot matrix contrast adjustment analog output
5V
J-BUS data input
J-BUS data output
J-BUS clock input and output
H:LX333R L:LX111R
Data output to LCD driver
Clock output to LCD driver
Symbol
SW2
SW3
SW4
RST-SW
LMO
LM1
DIM-OUT
ILLUM1
VDD
X2
X1
VSS
XT2
XT1
RESET
SW1
BUS-INT
PS2
CRUISE
RDS-SCK
RDS DA
REMOCON
AVDD
AVREFO
TEM1
KEY0
KEY1
KEY2
LEVEL
MRC
SQ
SM
AVSS
W-VOL
DOT-CNT
AVREF
BUS-SI
BUS-SO
BUS-SCK
STAGE2
LCD-DA
LCD-SCK

KD-LX333R
1-25
2.Pin functions(2/3)
Pin No.
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
I/O
O
O
I
O
O
O
O
O
O
O
I
O
O
I
I
I
I
I
I
I
O
O
-
O
O
O
I
I
O
-
I
I
O
O
O
O
O
O
-
O
O
O
O
O
-
O
O
-
O
O
O
-
Function
Chip enable output 1 to LCD driver
Buzzer output
12C communication data input
12C communication data output
12C communication clock output
J-BUSI/O signal terminal
Tray motor negative signal output terminal
Tray motor positive signal output terminal
Motor control signal output in door down
Motor control signal output in door up
Stereo signal input L:Stereo
AF check output AF check:L
Chameleon machanical switch 1 detection signal input
Chameleon machanical switch 2 detection signal input
Chameleon machanical switch 3 detection signal input
Chameleon machanical switch 4 detection signal input
Chameleon machanical switch 5 detection signal input
Rotary volume signal 1 input
Rotary volume signal 2 input
Auto seek/stop selection output SEEK:L STOP:H
FM/AM selection output FM:H AM:L
IC control CE output
IC control data output
IC control clock output
IC control data input
Telephone mute detection input
POWER AMP ON/OFF selection output
GND
Dimmer detection input L:dimmer ON
Power save 1 Operating together with ACC.Power save :L Operating :H
Power ON/OFF selection output Power ON:H
CD power supply control signal output CD:H
Mute output MUTEON:L
Subwoofer cut off frequency control output 1
Subwoofer cut off frequency control output 2
Subwoofer mute output MUTE ON:H
5V
data output terminal
clock signal output terminal
FM band filter selection signal output
CD-DA/CD-RW selection control output CD-RW:L
Reset signal output to LCD driver
Door motor kick signal output
Tray motor kick signal output
Data cmmunication clock output with CDLSI
Data cmmunication clock CE with CDLSI
CDLSI reset signal output
GND
Symbol
LCD-CE1
BUZZER
12C-DAI
12C-DAO
12C-CLK
BUS-I/O
TMO
TM1
DMO
DM1
ST
NC
AFCK
C-SW1
C-SW2
C-SW3
C-SW4
C-SW5
VOL1
VOL2
SEEK/STP
NC
FM/AM
PLL-CE
PLL-DO
PLL-CLK
PLL-DI
TEL-MUTE
AMP-KILL
VSS
DIM -IN
PS1
POWER
CD-ON
MUTE
W-LPF1
W-LPF2
W-MUTE
VDD
VOL-DA
VOL-CLK
CF-SEL
GVSW
LCD RST
NC
DMK
TMK
NC
BUCK
CCE
RST
TEST

KD-LX333R
1-26
2.Pin functions(3/3)
Pin No.
95
96
97
98
99
100
I/O
I/O
I/O
I/O
I/O
I
O
Function
Data communication input and output port 0 with CDLSI
Data communication input and output port 1 with CDLSI
Data communication input and output port 2 with CDLSI
Data communication input and output port 3 with CDLSI
H:not for 8cm DISC L:for 8cm DISC
Symbol
BUSO
BUS1
BUS2
BUS3
DISCSEL
NC
+-+--+
+-
-
-
+
+
REFR
REFL
FILTER
8
9
10
1112
13
14
1234567
INR
NFR
FIL
NFLCL+ Vcc INL
CL- LGND OUTL OUTR RGND CR- CR+
17
8
3220
14
BA3220FV-X (IC301,IC401) : Line out amp
1.Pin layout
2.Block diagram

KD-LX333R
1-27
BD3860K (IC911) : E.Vol & Loud
1.Terminal layout
2.Block diagram
3.Pin function
1 11
33 23
34
44
22
12
13
12
7
8
37
10
11
41
42
43
44
1
2
3
4
6 5 9 40 36 35 343328323130 2919 15 14
39 38 37 25 24 26 23 22 21 20 18 17 16
GND FIL VCC SEL1
0 18 dB
0 18 dB
VIN1 LOUD1 HF1 LF1 DET1 TIN1 TNF1 BNF1
OUTF1
OUTR1
SI
SC
OUTR2
OUTF2
BOUT2BNF2TNF2TIN2BBOUT2MIX2VCA2DET2LF2HF2LOUD2VIN2SEL2
D2
C2
B2
A2
D1
C1
B1
A1
BOUT1VCA1 MIX1 BBOUT1
POWER
SUPPLY INPUT
GAIN
INPUT
GAIN
MAIN
VOLUME
0 -40 dB
LOUDNESS
MAIN
VOLUME
0 -40 dB
LOUDNESS
LOW(f=50Hz) 6dB
PROCESS CONTROL +3 to 12dB
(f=10kHz)
LOW(f=50Hz) 6dB
PROCESS CONTROL +3 to 12dB
(f=10kHz)
TREBLE
-14 +14dB
TREBLE
-14 +14dB
BASS
-14 +14dB
BASS
-14 +14dB
FADER
CH1 FRONT
0 -5 dB
FADER
CH2 FRONT
0 -5 dB
FADER
CH1 REAR
0 -5 dB
FADER
CH2 REAR
0 -5 dB
LOGIC
INPUT
SELECTOR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
CH2 Input Pin A
CH2 Input Pin B
CH2 Input Pin C
CH2 Input Pin D
1/2 VCC Pin
Ground Pin
Serial Data Receiving Pin
Serial Clock Receiving Pin
Power Supply Pin
CH2 Rear Output Pin
CH2 Front Output Pin
CH1 Rear Output Pin
CH1 Front Output Pin
CH1 Bass Filter Setting Pin
CH1 Bass Filter Setting Pin
CH2 Bass Filter Setting Pin
CH2 Bass Filter Setting Pin
CH2 Treble Filter Setting Pin
CH1 Treble Filter Setting Pin
CH2 Treble Input Pin
CH2 BBE II Signal Output Pin
CH2 Output MIX Amplifier
Inverse Input Pin
A2
B2
C2
D2
FIL
GND
SI
SC
VCC
OUTR2
OUTF2
OUTR1
OUTF1
BOUT1
BNF1
BOUT2
BNF2
TNF2
TNF1
TIN2
BBOUT2
MIX2
Pin
No. Symbol Function 23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
CH2 High Pass VCA Output Pin
CH2 Low Pass Filter Setting Pin
CH2 High Pass Filter Setting Pin
CH2 High Pass Attack/ReleaseTime Setting Pin
BBE ON/OFF switching time constant pin
CH1 High Pass Attack/ReleaseTime Setting Pin
CH1 treble Input Pin
CH1 BBE II Signal Output Pin
CH1 Output MIX Amplifier Inverse Input Pin
CH1 High Pass VCA Output Pin
CH1 Low Pass Filter Setting Pin
CH1 High Pass Filter Setting Pin
CH1 Loudness Filter Setting Pin
CH1 Main Volume Input Pin
CH2 Loudness Filter setting Pin
CH2 Main Volume Input Pin
CH2 Input Gain Output Pin
CH1 Input Gain output Pin
CH1 Input Pin A
CH1 Input Pin B
CH1 Input Pin C
CH1 Input Pin D
VCA2
LF2
HF2
DET2
DEF
DET1
TIN1
BBOUT1
MIX1
VCA1
LF1
HF1
LOUD1
VIN1
LOUD2
VIN2
SEL2
SEL1
A1
B1
C1
D1
Pin
No. Symbol Function

KD-LX333R
1-28
Vdd WPIN SCL SDA
A0 A1 A2 GND
8 Vdd
7 WPIN
6 SCL
5 SDA
A0 1
A1 2
A2 3
GND 4
16kbit EEPROM allay
11bit
11bit
8bit
Address
decoder Slave Word
Address resister Data
resister
START STOP
ACK
Control circuit
High voltage osc circuit Power supply
voltage det.
Vdd
GND
A0,A1,A2
SCL
SDA
WPIN
-
-
I
I
I/O
I
Power supply.
GND
No use connect to GND.
Serial clock input.
Serial data I/O of slave and word address.
Write protect terminal.
Symbol I/O Function
BR24C32F-X (IC703) : EEPROM
1. Pin layout
3. Block diagram
2. Pin function
14 13 12 11 810 9
1234 756
VDD C1 C4 I/O4 I/O3O/I4 O/I3
I/O1 O/I1 O/I2 I/O2 VssC2 C3
BU4066BCFV-X (IC322) : Quad analog switch
1. Pin layout & Block diagram

KD-LX333R
1-29
1. Pin layout
2. Block diagram
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
QUAL
RDATA
Vref
MUX
VDD1
VSS1
VSS3
CMP
RCLK
N.C.
XO
XI
VDD2
VSS2
T1
T2
-
+
8th Switched
capacitor filter
PLL
57kHz
RDS/ARI
PLL
1187.5Hz Bi-phase
decoder Differential
decoder
Measurement
circuit
Reference
clock
100k
100k
120k
anti-aliasing
filter
comparator
Analog
Power supply
Digital
Power supply
4
3
5
6
12
11
13 14 10 9
BU1923F (IC51) : RDS decoder
78
16
1
2
MUX
Vref
VDD1
VSS1
VDD2
VSS2
Xl X0 T1 T2
RDATA
QUAL
RCLK
CMP
VSS3
RPM6938-SV4 (IC602) : Remote sensor
Vcc
Vcc
Comp
AGC
AMP
PD
Detector
BPF
fo
trimming
circuit
I/V
conversion
magnetic shield
Rout
GND
22k
1.Block diagram

KD-LX333R
1-30
FAN8037 (IC581) : CD driver
1. Pin layout & Block diagram
2. Pin function
30
29
28
27
26
25
36
35
34
33
32
31
1
2
3
4
5
6
7
8
9
10
11
12
13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37
s
w
s
w
s
w
M
S
C
M
S
C
M
S
C
D
D
D
D
D
D
T.S.D
STAND BY
ALL MUTE
POWER SAVE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
I
I
O
I
I
O
I
I
O
I
I
I
I
I
I
-
I
I
I
I
I
I
-
O
CH2 op-amp input(+)
CH2 op-amp input(-)
CH2 op-amp output
CH3 op-amp input(+)
Ch3 op-amp input(-)
CH3 op-amp output
CH4 op-amp input(+)
CH4 op-amp input(-)
CH4 op-amp output(+)
CH5 motor speed control
CH5 forward input
CH5 reverse input
CH6 motor speed control
CH6 forward input
CH6 reverse input
Signal ground
CH7 forward input
CH7 reverse input
CH7 motor speed control
Stand by
Power save
All mute
Power supply voltage
CH7 drive output(-)
IN2+
IN2-
OUT2
IN3+
IN3-
OUT3
IN4+
IN4-
OUT4
CTL1
FWD1
REV1
CTL2
FWD2
REV2
SGND
FWD3
REV3
CTL3
SB
PS
MUTE
PVCC2
DO7-
Pin
No.
Symbol I/O Function 25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
O
O
O
-
O
O
O
O
O
O
-
O
O
O
O
-
I
O
I
I
-
I
I
O
CH7 drive output(+)
CH6 drive output(-)
CH6 drive output(+)
Power ground2
CH5 drive output(-)
CH5 drive output(+)
CH4 drive output(-)
CH4 drive output(+)
CH3 drive output(-)
CH3 drive output(+)
Power ground1
CH2 drive output(-)
CH2 drive output(+)
CH1 drive output(-)
CH1 drive output(+)
Power supply voltage
Regulator feedback input
Regulator output
Regulator reset input
Bias voltage input
Signal supply voltage
CH1 op-amp input(+)
CH1 op-amp input(-)
CH1 op-amp output
DO7+
DO6-
DO6+
PGND2
DO5-
DO5+
DO4-
DO4+
DO3-
DO3+
PGND1
DO2-
DO2+
DO1-
DO1+
PVCC1
REGOX
REGX
RESX
VREF
SVCC
IN1+
IN1-
OUT1
Pin
No.
Symbol I/O Function

KD-LX333R
1-31
2
1
11
12
10
15 13
14
5
4
6
3
8
9
7
ILM AJGND GND
C6
10u
C5
0.1u
C4
0.1u
C3
0.1u
AUDIO OUT
CD OUT
CTRL
ANT CTRL
EXT OUT
ANT OUT
VCC ACC
Surge Protector
BIAS TSD
C1
100u C2 0.1u
+B
ACC
BATT.DET OUT
COMPOUT
VDD OUT
SW5VOUT
ILMOUT
C7
0.1u
C8
0.1u
R1
UNIT R:
C:F
note1) TAB (header of IC)
connected to GND
HA13164A (IC961) : Regulator
1.Terminal layout
2.Block diagram
3.Pin function
Pin No. Symbol Function
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
EXTOUT
ANTOUT
ACCIN
VDDOUT
SW5VOUT
COMPOUT
ANT CTRL
VCC
BATT DET
AUDIO OUT
CTRL
CD OUT
ILM AJ
ILM OUT
GND
Output voltage is VCC-1 V when M or H level applied to CTRL pin.
Output voltage is VCC-1 V when M or H level to CTRL pin and H level
to ANT-CTRL.
Connected to ACC.
Regular 5.7V.
Output voltage is 5V when M or H level applied to CTRL pin.
Output for ACC detector.
L:ANT output OFF , H:ANT output ON
Connected to VCC.
Low battery detect.
Output voltage is 9V when M or H level applied to CTRL pin.
L:BIAS OFF, M:BIAS ON, H:CD ON
Output voltage is 8V when H level applied to CTRL pin.
Adjustment pin for ILM output voltage.
Output voltage is 10V when M or H level applied to CTRL pin.
Connected to GND.
123456789101112131415
TAB

KD-LX333R
1-32
1
2
3
4
5
6
7
14
13
12
11
10
9
8
OE1
A1
Y1
OE2
A2
Y2
Vss
Vcc
OE4
A4
Y4
OE3
A3
Y3
HD74HC126
HD74HC126FP (IC771) : Changer control
M5282FP-X (IC321) : E. volume
1. Pin layout
3. Pin function
2. Block diagram
1
2
3
4
5
10
9
8
7
6
1
2
3
10
457 8
9
1
2
3
4
5
6
7
8
9
10
Vcc/2 output for microphone amp.
Microphone amp. positive input terminal.
Microphone amp. negative input terminal.
Microphone amp. output terminal.
Ground.
Non connection.
VCA input terminal.
VCA control terminal.
VCA output terminal.
Power supply.
Vcc/2
Amp+IN
Amp-IN
Amp OUT
GND
NC
VCA IN
Vc
VCA OUT
Vcc
Pin
No.
Symbol Function
+– 6
7
5
8
B
+–
2
1
3
4
A
A OUT
A IN–
A IN+
VEE
VCC
B OUT
B IN–
B IN+
NJM2100M (IC821) : Operational amp

KD-LX333R
1-33
LC75878W (IC601) : LCD driver
1. Pin layout
2. Block diagram
1
~
25
75
~
51
26 ~ 50
100 ~ 76
3. Pin function
1~73
74
75
76~83
84~87
88
89
90
91
92
93
94
95
96
97
98
99
100
O
O
O
O
O
-
-
O
I
I
I
I
-
I/O
I
I
I
I
Segment driver output pin.
Segment driver output pin.
Segment driver output pin.
Common driver output pin.
General-purpose output pin.
Logic block power supply pin.
LCD driver power supply pin.
LCD driver bias 4/4 voltage (H-level) power pin.
LCD driver bias 3/4 voltage (intermediate level) power pin.
LCD driver bias 2/4 voltage (intermediate level) power pin.
LCD driver bias 1/4 voltage (intermediate level) power pin.
LCD driver bias 0/4 voltage (L-level) power pin.
Power supply pin to connect to ground.
Oscillator pin.
Display off, general-purpose output port L fixed input pin.
Chip enable
Synchronization clock
Transfer data
SEG1~SEG73
SEG74
SEG75
COM8~COM1
P1~P4
VDD
VLCD
VLCD0
VLCD1
VLCD2
VLCD3
VLCD4
VSS
OSC
LCD RESET
CE
CL
DI
No. Symbol I/O Function
OSC
VLCD
VLCD0
VLCD1
VLCD2
VLCD3
VLCD4
VDD
VSS
P1 P4 COM1 COM8 S75/COM9 S74/COM10 S73 S1
INH
DI
CL
CE
GENERAL
PORT COMMON
DRIVER SEGMENT DRIVER & LATCH
SHIFT REGISTER
CONTROL
REGISTER
CCB
INTERFACE
CLOCK
GENERATOR
CONTRAST
ADJUSTER

Block diagram
TU1
TUNER PACK
J1 FM/AM
S.METER
SEEK/STOP
SD/ST
PLLCE
PLLD1
PLLCL
IC51
RDS
FMDET.ADJ
RDSDA
RDSSCK
AMAF
IC701
CPU
IC911
E.VOLUME
L-CH
R-CH
LOUTF
LOUTR
LOUTF
LOUTR
IC361
Lch
IC461
Rch
INFL
INFR
INFL
INFR
IC941
POWER AMP
IC961
REGULATOR
OUTFL ,OUTFR
OUTFL ,OUTFR
CN901
ACC
CN301
CN771
REAR L
REAR R
Rear speaker
Front speaker
BATT
Line out
CH-L
CHR
IC703
EPROM
IC771
JVCBUS
DA1
CLK
BUSSI/BUSSO BUSINT,BUSSCK
RESET
IC702
RESET
IC151
CD LPF
IC521
DSP&DAC
IC501
RF AMP
IC581
CD&TRAY/DOOR
LOADINGDRIVER
IC951
REGULATOR VCC
LCDDA,LCDDL,LCDCF1,LCDCE2,LCDRST
RSET,REMOCON,KEY1,KEY2
CN701
CN601
CN702
KEY0
KEY1
CN631
CN704
CN503 CN504
CASW1
CASW2
CASW3
CD-L
CD-R
L-CH
R-CH
BUS0
BUS1
BYS2
BUS3
BUCK
CCE
RST
FOO
FRD
DMO
FMO
SLE,TEB,RFDC,RFBC
TE,RFBO,RFRP,FEO
VA,VB,VC
MD,LC
CN501
TR SP FE
LO FO
DOOR TRAY
CD MECHA
KEY0
KEY1
REMOCON
IC603
REMOCON
IC601
LCD DRIVER
LCDRST,LCDCE1
LCDCL,LCDDA
KEY SWITCH
LED
LCD
KEY2
INV
VOL-DA
VOL-CLK
A
B
C
D
E
F
G
1
2
3
4
5
2-1
KD-LX333R

Parts are safety assurance parts.
When replacing those parts make
sure to use the specified one.
TUNER SIGNAL
CD SIGNAL
CD CHANGER SIGNAL
FRONT SIGNAL
REAR SIGNAL
KD-LX333R KD-LX333R
A
B
C
D
E
F
G
1
2
3
4
5
2-2
Standard schematic diagram
Main amp section