Kenwood TM-221A User manual

144MHz FM TRANSCEIVER
TM-221A/E/ES
SERVICE MANUAL
KENWOOD
©1987-3 PRINTED IN JAPAN
‘B51-3217-00 (O) 1551
Knob (Button)
(K29-3058-04) x 3
Metallic cabinet (Top)
{A01-1021-03)
Knob (Button)
(K27-0496-04) x 2
Panel ass’y*
(A20-)
KENWOOD © 14miz FM TRANSCEIVER TM-221A
16510
Knob (Main)
(K29-3060-04)
Knob (Button)
(K29-3070-04)
Knob (Button)*
{K29-)
Knob (Button)
(K29-3069-04)
Knob (Button)
(K29-3067-04)
Knob (Button)
{K29-3065-04)
CIRCUIT DESCRIPTION .........0-c0cee cues 2
SEMICONDUCTOR DATA ...........0seeees 12
DESCRIPTION OF ELEMENTS .............-. 13
PARIS LIST Gs tresses aOae der Beek Gtet a ahs 16
EXPLODED VIEW sis; cntnieiond eh ce aah eeahn 32
BACKING fick rvkin Ge ted hee tke aden dense 33
DISASSEMBLY ...........0eeceeeeceecuee 34
ADJUSTMENT ....... ccc 0ccceeececeuees 35
PC BOARD VIEWS
LCD ASS'Y (B38-0303-05) .......e.ees cues 41
VCO (X58-3090-00) .. 0. ec eee eee cece aces 44
DRIVE (X59-3120-00) .. 00.0. e cece eee eees 41
APC (15059190200)... 05 bs han ahaadneks 42
(F (X60-3140-00): ais-oy caduceus aeredhowd s 42
Knob (VOL, SQL)
(K29-3061-04) x 2
CONTENTS
Microphone*
(T91-)
* Refer to parts list on page 16.
Photo is TM-221A.
SOL (X59-3150-00) 2... ee eee cee 42
MIC (X59-3160-00) 21... eee eee ee eee 42
VOL (X59-3170-00) 2... ee eee 42
FINAL UNIT (X45-1330-03) ... 0... .. ee eee 43
FINAL UNIT (X45-1360-02) .. 2... 2... eee 43
CONTROL UNIT (X53-3040-XX). 2.2.2... eee 44
TX-RX UNIT (X57-3060-XX) 2... ee ee 45
SCHEMATIC DIAGRAM .................044- 49
LEVEL DIAGRAM ...............0-02 20 eee 53
BLOCK DIAGRAM ................200000- 54
TERMINAL FUNCTIONS ................0.- 55
TSU-5 (CTCSS UNIT) ©... eee ee ee eee 56
SPECIFICATIONS ................ BACK COVER

TM-221A/E/ES
CIRCUIT DESCRIPTION
TM-221A (45W)
K [ mi [m2
TM-221ES (45w)
11 | mz | lw
Final unit X45-1360-02
X45-1330-03 X45-1360-02
Control unit
X53-3040-1 1 [x53-3040-21 [ X53-3040-22 X53-3040-51 X53-3040-61
| X53-3040-51 | X53-3040-61
TX-RX unit X57-3060-11 X57-3060-51
X57-3060-52
Table 1 Comparison of TM-221A, TM-221E and TM-221ES
Frequeny configuration
The TM-221A/E/ES utilize a PLL synthesizer system
incorporating a digital VFO. (See Fig. 1.) The channel
step can be selected as 5, 10, 12.5 (T,W), 15, 20, or 25kHz.’
The receiver operates as a double conversion system. Re-
ceived signals are mixed with the first local oscillator
(133.305~137,300MHz (K,M), 133,300~135.295MHz
(T,W)) to produce the first intermediate frequency of
10,.695MHz (K,M), 10.7MHz (T,W). The first intermediate
frequency is mixed with the second local oscillator (10.24
MHz (K,M), 10.245MHz (T,W)) to produce the second
intermediate frequency of 455kHz.
The transmitter system consists of a PLL circuit in-
corporating a direct oscillator and direct divider. The
output is amplified by a linear amplifier prior to being
transmission.
144~148MHz (iM)
144~146MHz (T,W)
1st MIX
133.305~
Receiver system
@ General
Incoming signals from the antenna pass through a low-
pass filter in the Transmitter Final unit and a diode trans-
mit/receive switch, then enter the receiver front end.
After passing through two antenna coils the signals are
amplified by a GaAs (galium arsenide) FET (Q1
3SK184(S). Undesired signals are removed by 3 tuning
coils (L19~L21 : K,M) or a 3-pole helical resonator (L3 :
TW). The resulting signal is applied to the first mixer
Q2 : 3SK131(V12), which employs an N channel MOS FET
to obtain good 2-signal characteristics. In the first mixer
(Q2) the signal is mixed with the first local oscillator
from the PLL system to produce the first IF signal of
10.695MHz (K,M), 10.7MHz (T,W). Interfering Adjacent
channel interference is removed from the first IF signal
by a two-stage monolithic crystal filter (MCF) (L6).
455kHz
CFW455F
10.7MHz (TW) co 10.24MHz (KM)
137.300MHz {K,M)
133.300~
T
10.245MHz
(T,W)
135,.295MHz
(T,W)
‘Sams
eae
TT 7
PLL |
SYSTEM |
L.
a
_Jj
MIC
144,000~
147.995MHz (KM)
144.000~
145.S95MHz (T,W)
Fig. 1 Frequency configuration

TM-221A/E/ES
TM-221A/E/ES
CIRCUIT
DESCRIPTION
CIRCUIT
DESCRIPTION
The
first
IF
signal
is
amplified
by
Q3
:
2SC2714(Y)
Rating
—
+
: |
i
AF amp.
put
is
filtered
to
remove
the
second
intermediate
fre-
quency
component
(455kHz),
amplified
twice,
and
is
then
fed
to
the
rectifier.
After
rectification,
the
signal
passes
through
the
squelch
control
to
the
audio
limiter
circuit.
@
S-meter
circuit
:
The
S-meter
output
voltage
of
the
special
narrow-FM
iC
(TA7761F)
is
amplified
by
an_
inverting
amplifier,
then
fed
to
the
Control
unit.
The
microprocessor
converts
the
analog
voltage
to
a
digital
signal
that
is
used
to
control
10.7MHz2
+7.5kHz or more at 3dB
+25kHz or less at 40dB
+£45kHz or less at 6OdB
70dB or more within £1MHz,
(Spurious
response
40dB
or
more
Guaranteed
attenuation
at
fo~fo
+
500kHz)
80dB or more at fo—(900~
Q20kHz)
Nominal
center
frequency
(fo)
Pass
bandwidth
ae
geal
iT
AW
R41
Attenuation bandwidth
and
fed
toa
special
narrow-FM
IC
ate
Here
the
Nominal
conterfrequency
(ol
|
10.695MHz
|
HY
<
signal
is
mixed
with
the
10.24MHz
(K,
),
10.245MHz
Pee
bandwidih
os
+7
5kHz
or
more
at
308
rca
7
7
L
:
(T,W)
frequency
from
the
second
local
oscillator
to
pro-
1
e25kHz
or
less
at
40dB
2
>
3
8
duce
the
455kHz
second
IF
signal.
This
signal
is
sharpened
Attenuation
bandwidth
+ABkHz
or
less
at
60dB
2
Pr
|
g
8 8
by
passing
it
through
a
six-element
ceramic
filter
F0dB
or
more
within
£1MHz
‘omits
|
4
&xgas
(CFW455F).
The
signal
is
then
amplified
by
a
five-stage
40dB
or
more
spurious
at
|
2
#325
limiting
amplifier
contained
in
IC1. This
is
followed
by
Guaranteed
attenuation
fo~fo
+
500kHz
|
g
8
€
g
é
quadrature
detection
which
is
also
performed
by
{C1.
Un-
meee
at
|
:
i
Weeks
desirable
high-frequency
components
are
removed
from
Slice
z
|
ee
ee:
the
detected
signal
by
an
active
low-pass
filter.
The
signal
:
-
on
Pa
Pe
‘
:
Insertion
loss
1.5dB
or
less
SO0Se%5
a
then
passes
through
the
audio
volume
control,
then
is
Terminate
7
3kR/OpF
>
:
=
fs
£5
ag:
1s
7
e
natin
et
=
—
=
amplified
by
the
audio
power
amplifier
(1C4),
and
applied
ail
ee
e
3
|
:
TS8rars
to
the
speaker.
The
circuit
configuration
from
detection
Table
2-1
MCF
(L71-0216-05)
characteristics
ro
|
7
“
onward
is
shown
in
Fig.
2.
(TX-RX
unit
L6
:
K,M
type)
E
|
Oo
D
O
®
Squelch
circuit
:
[
:
5
The
noise
component
extracted
from
the
detector
out-
g
|
-
?
8
£
<
|
-
E
3S
2
fo)
Normally on
en bv ee
VOL(X59-3170-00) remote controller (option)
the
LCD
bar
meter.
Ripple
1,0dB
or
less
raane”
1
Sah
or
less
zg
i
sags
—
&
Table
2-2
MCF
(L71-0228-05)
characteristics
=n
as
Z
Ais
tue
tn
|
ong
hh
p:
Y
a
(TX-RX
unit
L6
:
T,W
type)
S25e
e
3s
aol
na
Sv
LE
os
<
es
E
e2ee
Soge
Suse
S238
Sts
BRS
e
Nominal
center
frequency
455kHzt1kHz
4
S
e
=
6dB
bandwidth
£6kHz
or
more
(from
455kHz)
z
4
ig
S°8S
Cc.
a
50dB
bandwidth
|
£12.5kHz
or
less
(from
455kHz)
oo
Le
Sas
Teme.
Rippie
-OfLS
ore
3dB
or
less
2Gees
(within
455£4kHz)
262
2
2
{Insertion
loss
6dB
or
less
Guaranteed
attenuation
350B
or
less
is
(within
455+100kHz)
(/O
impedance
2.0kQ
Table
3
Ceramic
filter
CFW455F
(L72-0315-05)
|
>
characteristics
(TX-RX
unit
L10)
&
&
|
i
E
ie
”
|
28
=
g|
£3
3
2
8,
|
Begs
g
(8S
2ld2
2.
Se
x
=
_
fod
n
| | |
Detector output
UNIT
SQL
CONTROL
Fig. 2 Circuits from detector output onward
Noise amp.
1st-stage output
DT and CK lines are shared
with PLL DT and CK lines
VRi
VOL
CONTROL UNIT (X53-3040-XX)

TM-221A/E/ES
CIRCUIT DESCRIPTION
Transmitter system
@ General
in the transmitter system the desired frequency is pro-
duced directly by an oscillator. Frequency modulation is
obtained directly thru the use of a varactor diode.
@ Modulation circuit
Audio signals from the microphone are applied to a
three-stage operational amplifier which adds preemphasis,
performs amplification and limiting, and includes a splatter
filter to remove undesired high-frequency components.
After amplification by the operational amplifier, part of
the audio signal is applied to the microphone check circuit
used in the low-power mode.
In the FM modulation circuit, the frequency of the
VCO is directly modulated by a varactor diode.
RO?
(TM-221E)
VR?
% (TM-22tA/ES),
—
TX-RX UNIT
TO FINAL UNIT
@ Preamplifier stage circuit
The output from the VCO enters the linear amplifier,
which is capable of high-quality signal amplification
because it operates entirely in linear mode. APC, (Auto-
matic Power Control) is performed by controlling the
collector voltage of the 3 stage final preamplifier stage.
@ Power amplifier circuit
The drive signal is applied to the power module and
amplified to the required level. In the model TM-221A/
ES heat is dissipated efficiently by a large mechanically
strong heatsink.
@ APC and SWR protection circuits
Fig. 3 shows the basic ALC (Automatic Level Control)
and SWR (Standing Wave Ratio) protection circuits. The
SWR protection circuit incorporates a CM coupler that
detects any reflected power caused by mismatching of the
antenna. After detection and amplification, this circuit
acts to lower the output contro! voltage, which protects
the power module by reducing the gain. The automatic
power control (APC) circuit incorporates a diode that is
used to detect a portion of the output from the power
module. The detected signal is amplified and is then used
to control the power control voltage. The control voltage
is inversely proportional to the output, so a constant
output level is maintained.
ee ea all
FINAL UNIT
ee en ny ANT
LS 6 ANT
= GNO
o bas
o “Ts ek
° is)
R2 d eX gabice
OTPI
= v NU VRI
eat od LL] Z VR ey
J
C16
BRE t | | |
16 $e em me ne em
|
|
iQ
bees
. es rei creed
Fig. 3 APC and SWR protection circuits
Condition
Operating vo! tage
Specifications
M57747 M57726
Current consumption
5
Input power
Output power
2G7ZL= 502
ZG=ZL=502 | 0.4 (Vcc1¥12.5V)
55
Case temperature (operating)
Storage temperature
—30~+110 —30~ +110
—40~+110 —40~+110
Table 4 Power module M57747 (TM-221E), M57726 (TM-221A/ES)
absolute maximum ratings (Final unit Q1)
TM-221A/E/ES
CIRCUIT DESCRIPTION
PLL synthesizer
Fig. 4 is the PLL system block diagram. The trans-
mitter and receiver systems of the TM-221A/E/ES have
independent VCOs and PLLs, but share a common low-
pass filter.
The VCOs are configured as subunits. This construc-
tion minimizes outside influence and improves frequency
stability.
DATA
CLOCK
RESET (W,T only)
10 VCO(X58-3090-00)
Fig. 4 PLL system block diagram
10.24MHz (K,M)
12,8MHz (T,W) > 1 (5)
1/8 divider
2-modulus
prescaler
(1/128, 1/129)
VCO input
53
fREF divider
1/A divider
{7-bit binary)
1/N Programmable divider
Se {10-bit binary) z
Shift register (21-bit)
©
Data input
from Control unit
Fig.5 PLL IC ; M54959P block diagram
21 pulse counter
To
provide
5,
10,
12.5
(T,W),
15,
20,
and
25kHz
steps,
a
comparison
frequency
of
5kHz
or
6.25kHz
(T,W)
is
obtained
by
dividing
the
10.24MHz
(K,M),
12.8MHz
(T,W)
frequency
of
the
reference
oscillator
by
2048
or
2560
{T,W).
In
both
the
transmitter
and
receiver
systems
the
target
frequency
is
produced
directly
by
the
VCO,
passed
through
one
amplifier
stage,
then
applied
to
a
pulse-swallow
PLL
IC
that
divides
the
frequency,
performs
phase
comparison,
and
locks
the
frequency.
The reference frequency division ratios (four values)
and comparison frequency divison ratio are supplied to
the PLL IC (M54959P) as external serial data. An internal
dual-modulus (1/128 and 1/129) prescaler enables the
entire pulse-swallow PLL circuit to be implemented on
a single chip. (See Fig. 5.) The switching functions
(SW1
and
SW2)
of
the
PLL
IC
are
used
to
switch
between
the 8R (receive) and 8T (transmit) operating voltages
in the transmit and receive modes.
The switch controls are applied together with frequency
division ratio data from the Control unit.
RX 133.305~137,300MHz (K,M)
133,300~135,295MHz (T,W)
TX 144.000~147.995MHz (K,M)
144,000~145.995MHz (T,W)
To unlock control circuit
Divides 10,24MHz
by 2048 (KM)
Divides 12.8MHz
by 2048 or 2560
(TW)
Comparison | fg
frequency
ue
4
7 5V
detector
To LPF
Data latch (21-bit)
Latch signal
To8T To8R
control contro
circuit circuit

At 144MHz (K,M), fvco (RX) has the following
relationship to the various frequency division ratios :
fVCO=(144—10.695) = [(n X 128) + A] X fosc/R
where, fVCO : Frequency output by the VCO
n: 10-bit binary programmable counter setting
A: 7-bit binary programmable counter setting
fosc : 10.24MHz reference oscillator
R : 14-bit binary programmable counter setting
(2048)
If n=208 and A=37, then;
fyco=[(208 X 128) + 37] X 10240/2048
= [26624 + 37] X5
= 133305kHz=133.305MHz
DRIVE (X59-3120-00)
r
8V when PLL is locked
in transmit mode
OV when PLL is unlocked
in transmit mode A
©
”? ND 2
oO
+
eT
8R
1c2
M54959P ay
(€ OV)
2 °
ov Ps
5V R62 68.5v1 77" as
R63
% > UNLOCK
Low (OV) when PLL is locked
High (5.5V) when PLL is unlocked
TM-221A/E/ES
CIRCUIT DESCRIPTION
® Unlock detector circuit
Whenever the PLL is unlocked, pin 10 of the PLL IC goes
high (“H") (5.5V), turning off Q15 so that Q1 and Q2
in the module unit (drive unit) turn OFF. The result is
that during receive Q17 is OFF, and during transmit
Q4 and Q5 in the module unit are OFF, This halts trans-
mit, preventing unwanted radiation from the antenna.
(See Fig. 6.)
Rto
FROM PLL OUT TO DRIVE TR Q19.
8V when PLL locked in receive mode
OV when PLL unlocked in receive mode
| Ree c79
1.4V when PLL is locked 2 = ;
OV when PLL is unlocked
Qi7 [> To 1st RX mixer
R71
(Pv
Bo
eo
Sy
LA DH °
gmt
|
e
oT
—— ——_I
C69 discharge is delayed when
voltage rises and advanced when
voltage falls.
Fig. 6 PLL unlock detector circuit

Digital control unit
@ General
The control unit consists of a microprocessor, input
keys, peripheral circuits, and a display. The single micro-
processor (!C3) controls all transceiver functions. The pin
assignments of the microprocessor are listed on the
Table 6.
@ Keys and rotary encoder input circuits
Fig. 7 shows the input circuit for the keys and rotary
encoder. Data from the front panel keys, microphone
keys, and rotary encoder are applied directly to the
microprocessor,
Terminal
Xt 4.194304MHz crystal oscillator.
73
Not used;
CTCSS shift register reset
a! (K,M)
ee
Oo
O
cs a
altale||2 Wid Sis a|2 [ole
BS ral
SHIFT
5V
Not used.
Sauelch control during remote
38 P22 H 5 pi ?
control.
nee? 1 Reset input.
PO3/SI
PO2/SO
ie)
Shift register strobe.
Beep oscillator output.
Microphone DOWN switch input/
serial data input.
Microphone PTT switch input/
serial data input.
PO1/SCK
Microphone UP switch input/
serial data input.
Model setting : 'L’’ for 144MHz
“H" for 430MHz band.
Backup detect input.
SHIFT switch input.
LCD driver data.
LCD driver clock.
LCD driver enable.
M.IN switch input.
VEO/M select switch input.
REV switch input.
Not used.
Frequency step select switch input.
SCAN switch input.
+
Directional input.
CTCSS switch input (K,M).
Alert switch input (T,W).
TONE switch input.
Not used.
Pull-down pin.
PLL and shift register clock.
PLL and shift register data.
PLL enable.
Not used.
[GND terminal (OV).
BUSY input.
Power supply pin (5V).
Encoder input.
{only when connected).
GND terminal (OV).
Remote connection detect input
ae etal
Tone detect input (when CTCSS
is on (KM).
CTCSS IC data (KM).
Not used.
RF meter analog input.
S meter analog input.
CTCSS IC clock.
DAC digital data output.
Table 5 yPD75106G-508-18B pin assignments (Control unit IC3)

comM1
COMS
@ Display circuit
Located in the LCD assembly (Fig. 8), the display
circuit consists of the
LCD driver, its peripheral circuits,
and the LCD. The LCD is driven with a 50% duty cycle
BUSY
Me
Pant
a
Og0gn000006
CALL
rm
2)
33
34
35
36
37
38
39
40
“1
42
43
44
45
46
47
48
Se ae
ap 8S
SCAN
ce)
Sa
HOON OG UU OL
ep
oa
wo
t
+
ey
nn
LC7582
58 59
Po s7|
TM-221A/E/ES
CIRCUIT DESCRIPTION
according to serial data sent from pins P71 to P73 of the
microprocessor to the LCD driver. Fig. 9 shows the
common output and segment output signals of the LCD
driver.
8 ow
5x8
«ew @
tek Bs
nok oo
Vico
ra Ch bruce
GND
VicD
ee Crier ei
GND
$1~$52 —
Only the COM1
side is ON. : GND
COM1 and COM2 vie
side is ON. GND
Only the COM2
side is ON.
VLCD
VLCD
<>
COM1 and COM2
side are OFF.
1
fosc/si2 SEC
Fig. 9 LCD driver common and segment
100
[|
[|
oO 2 m °
680P
2.7K
output signals
047
Fig. 8 LCD ass’y (B38-0303-05)

TM-221A/E/ES
CIRCUIT DESCRIPTION
@ Reset backup circuit
Fig. 10 shows the reset backup circuit. When the
transceiver is turned ON, 3.0V is applied at the INT4
pin causing I|C3 to enter the backup mode.
Ci6
1C2 timing chart
Pin 1
Pin 3
Fig. 10 Reset and backup circuit
10
@ PLL data output
PLL data is supplied from pins P92 (CK), P91 (DT),
and P90 (RST) of the microprocessor. Fig. 11 shows
the data transfer format. Fig. 12 shows the data con-
figuration.
21 bit
CK
<a
MSB LSB
1S
Fig. 11 PLL data transfer format
B
MSI
fff
Le]
a]
ef
fof]
fess]
slo
tll
Pulse
swallow
counter
|
frequency division 22] 21 | 24] 2°] 2+] 24 24
ratio A |
Main counter
frequency
division
|
20] 24] 29| 22]
2a]
24] 2¢| 27]
28
|
2
'
ratio N {
Port setting, {oozes
comparison frequency ps ]o2]0s]o4
selection
&
a
Shift register
The 21-bit data is converted by the procedure below.
1. Frequency division ratio data A, N (17 bits)
F (RX display—10.695MHz) =
[(N X 128) + A] X 10.24MHz/ref (K, M)
F (RX display — 10.7MHz) =
L(N X 128) + A] X12.8MHz/ref (T, W)
N : Frequency division ratio of main 10-bit counter
A: Frequency division ratio of 7-bit pulse swallow counter
2. Comparison frequency (ref) selection (2 bits)
D2
5,10, 15, 20 or 25k Hz steps
L
Phase comparison frequency
3. Switch selection (2 bits}
ey |
o3 [D4 | swi [swe |
Fig. 12 PLL data configuration

@ Alert and electronic volume contro! output (when
optional remote controller is connected)
The alert and electronic volume contro! outputs are
provided by pins P92 (CK), P91 (DT), and P21 (ST) of
the microprocessor to the 8-bit shift register (1C3) in
the TX-RX unit. P92 (CK) and P91 (DT) are also used for
the PLL data. Fig. 13 shows the data transfer format.
Fig. 14 shows the data configuration.
Bbit
DT
MSB LSB
: |
Fig. 13 Data transfer format for alert and
electronic volume control
control
DOWN
UP
D6 to D8 when the
remote controller
Electronic =
Alert control
Fig. 14 Data configuration for alert and
electronic volume control
@ Tone output
The outputs from pins P40 to P43 and P50 to P53
of the microprocessor are applied to a ladder resistance
network (IC4) which converts these signals into an analog
waveform with 38 possible tone frequencies combinations
67.0 to 250.3Hz. Fig. 15 shows the internal configuration
of IC4,
P53
P52
P51
P50
P43
P42
P41
P40
{option) is connected.
TM-221A/E/ES
CIRCUIT DESCRIPTION
@ S-meter and RF meter input
The analog voltage of the S-meter is applied to pin
PTHOO of the microprocessor, and the analog voitage of
the RF meter to pin PTHO1. After 4-bit (16-step) analog-
to-digital conversion, the resulting signal is sent to the
display.
@ Busy input
When squelch is ON and an input signal is present, a
tow input lights the busy indicator.
@ CTCSS unit (option : TM-221A only) input and output
The microprocessor sends data from pins P30, P31, and
P61 to the CTCSS unit. Fig. 16 shows the data transfer
format. Fig. 17 shows the data configuration. When a tone
is detected from the CTCSS unit, a ‘’'H”’ is applied to pin
P32 of the microprocessor to open the squelch.
8bit
cTc Ii
CTD
MSB LSB
cTSs |
Fig. 16 CTCSS data transfer format
CTCSS unit MN6520 tone frequency select data
pet G2 es] BF | 26)
Ex.885Hz LH LE H H 4H
Fig. 17 CTCSS data configuration
@ Remote control (RC-10) (option) input and output
When the RC-10 remote control unit is connected a
“H"' is applied to pin INTO of the microprocessor, switch-
ing the following pins to the functions indicated:
PO3>SI _ : Serial data input pin
PO2—>SO_: Serial data output pin
P01 > SCK : Serial clock input/output pin
Fig. 15 Internal configuration of KRR-C0071 ladder resistance network
(Control unit 1C4)
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M-221A/E/ES
SEMICONDUCTOR DATA
Electronic volume LC7532M (VOL IC1)
@ Electric characteristics
Conditions
High-frequency. distortion
VDD=3V, RL=50kQ,
f=1kHz, VR MAX,
VIN=—20dBV
VDD=2.1V, RL=50kQ,
f=1kHz, VR MAX,
ViIN=—20dBV
Output in low-power mode
At OdBm input: f=1kHz, RL=51kQ
Input impedance
RIN
UP, DN, CE
Current consumption
@ Block diagram
IDD (1)
IDD (2)
VDD=S8V when operating
VDD=3V, CE="L"
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