Model V660
OPERATION
The Model V660 Programmable Clock Generator provides precise control over generated clock
frequency. Moreover, the conditions under which the Output Clock may be altered or disabled are
programmable and quite flexible.
The operation is conceptually quite simple. With the V660 in the inactive state, the program RAM
address is initialized to zero with a read of register 3E16 or a write of register 3216 with data equal to zero.
A predetermined sequence of output frequency and control information governing the response of the
Output Clock, Interrupt, and other outputs is written into the on-board RAM memory. One set of
frequency and control information constitutes a Step in the sequence. A Step then, consists of four
consecutive 16-bit words in the RAM: a frequency divisor, a flag word, and two words containing a 24-
bit termination count whose meaning is determined by Flag bits.
Once an entire sequence (up to 256 Steps) of Step information is loaded, the RAM pointer can be set to a
starting Step address (usually zero). Through the CSR register, the user chooses a clock source (Base
Clock) upon which the Output Clock is derived Ceither one of two internal crystal oscillators (10 MHZ
or 10.24 MHZ) or an external clock provided through a front-panel single-pin LEMO connector. The
user may also choose to predivide the Base Clock by 256 if the Output Clock is to be in a frequency range
that is much smaller than the Base Clock. When the FPA (Frequency Program Active) bit in the CSR is
set along with this Base Clock and other initializing information, the module will begin to exercise the
program list.
The V660-ZB11 option provides a divide by 10 range of possible frequencies from the V660-ZA11
option. Moreover, all strobe pulse widths are longer on the ZB11 option (200 nanoseconds versus 35
nanoseconds) for compatibility with modules which require longer trigger input pulses.
Control information within each Step describes the internal and external conditions required for the
termination of that Step. If and when these conditions are reached, the next Step is executed with its own
set of frequency and control information. Step termination can be programmed to occur after a) a
predetermined number of external triggers are received (from either one of two sources), b) a
predetermined number of output clocks are produced, or, at any time you read register 4216. Step
executions will continue until the completion of a Step containing an EOL (End-of-List) flag bit. This
will cause the next accessed Step to be the Afirst@step (i.e., the Step located at RAM address zero). At
this point, the program will either seamlessly continue execution with this step or deactivate completely.
The decision is based on the state of the RCM (Recycle Mode) bit in the CSR when the EOL Step is
completed.
For program RAM layout refer to page 9, 11, 13
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