Linear Technology DC2520A Quick setup guide

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DEMO MANUAL DC2520A
DESCRIPTION
LTC2344
16-/18-Bit, Octal 400ksps, SAR ADC
Demonstration circuit 2520A shows the proper way to drive
the LT C ®2344 ADC. The LTC2344 is alow noise, high speed,
simultaneoussampling16-/18-bitsuccessiveapproximation
register (SAR) ADC. The LTC2344 has a flexible SoftSpan
™
interface that allows conversion-by-conversion control of
the input voltage span on a per-channel basis. An internal
2.048V reference and 2×buffer simplify basic operation
while an external reference can be used to increase the input
range and the SNR of the ADC.
The DC2520A demonstrates the DC and AC performance of
the LTC2344 in conjunction with the DC590/DC2026 and
DC890 data collection boards. Use the DC590/DC2026 to L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and PScope,
QuikEval and SoftSpan are trademarks of Linear Technology Corporation. All other trademarks
are the property of their respective owners.
demonstrate DC performance such as peak-to-peak noise
and DC linearity. Use the DC890 if precise sampling rates
are required or to demonstrate AC performance such as
SNR, THD, SINAD and SFDR. The DC2520A is intended to
demonstrate recommended grounding, component place-
ment and selection, routing and bypassing for this ADC. A
suggesteddrivercircuitfortheanaloginputsisalsopresented.
Designfilesforthis circuit board including the schematic,
layout and BOM are available at
http://www.linear.com/demo/DC2520A
Figure 1. DC2520A Connection Diagram
–9V
VIN2
0V to 4.096V
VIN1
0V to 4.096V
CLK
100MHz MAX
2.5VP-P
+9V
DC890
DC590 OR DC2026
GND
BOARD PHOTO

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DEMO MANUAL DC2520A
DC890 QUICK START PROCEDURE
Check to make sure that all jumpers are set to their default
settings as described in the DC2520A Jumpers section of
this manual. The default connections configure the ADC to
use the onboard reference and regulators to generate all
the required bias voltages. The analog inputs by default are
DC coupled. Connect the DC2520A to a DC890 USB High
Speed Data Collection Board using connector P1. Then,
connect the DC890 to a host PC with a standard USB A/B
cable. Apply ±9V to the indicated terminals. Then apply
a low jitter signal source to J5 and J6. Use J7 to route
the signal sources of J5 and J6 to the desired AIN0-AIN3
inputs. Observe the recommended input voltage range
for each analog input. Connect a low jitter 2.5VP-P sine
wave or square wave to connector J1. See the Assembly
Options table for the appropriate clock frequency. Note
that J1 has a 50Ω termination resistor to ground.
Run the PScope
™
software (Pscope.exe version K86 or
later) which can be downloaded from www.linear.com/
designtools/software.
Complete software documentation is available from the
Help menu. Updates can be downloaded from the Tools
menu. Check for updates periodically as new features
may be added.
The PScope software should recognize the DC2520A and
configure itself automatically.
Click the Collect button (See Figure 3) to begin acquiring
data. The Collect button then changes to Pause, which
can be clicked to stop data acquisition.
DC590/DC2026 QUICK START PROCEDURE
IMPORTANT! To avoid damage to the DC2520A, make
sure that VCCIO (JP6 of the DC590, JP3 of the DC2026)
of the DC590/DC2026 is set to 3.3V before connecting
the DC590/DC2026 to the DC2520A.
To usetheDC590/DC2026withtheDC2520A,itisnecessary
to apply ±9V and ground to the ±9V and GND terminals of
the DC2520A. Connect the DC590/DC2026 to a host PC
with a standard USB A/B cable. Connect the DC2520A to
a DC590/DC2026 USB serial controller using the supplied
14-conductor ribbon cable. Apply a signal source to J5
and J6. Use J7 to route the signal sources of J5 and J6
to the desired AIN0-AIN3 inputs. No Clock is required on
J1 when using the DC590/DC2026. The clock signal is
provided by the DC590/DC2026.
Run the QuikEval software (quikeval.exe version K110 or
later)which is availablefrom www.linear.com/designtools/
software. The correct control panel will be loaded auto-
matically. Click the COLLECT button (Figure 6) to begin
reading the ADC.
ASSEMBLY OPTIONS
Assembly
Version U1 Part Number
Max Conversion
Rate
Number of
Channels
Number of
Bits
Max CLK IN
Frequency
CLK IN/fs
Ratio
DC2520A-A LTC2344-18 400ksps 4 18 68.8MHz 172
DC2520A-B LTC2344-16 400ksps 4 16 68.8MHz 172

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DEMO MANUAL DC2520A
DC2520A SETUP
+
–
+
–
AIN0 AIN0+
AIN0–
VCM
R107
49.9Ω
U25B
LT6237IDD
U25A
LT6237IDD
C96
0.1µF
C94
1000pF
C98
OPT
C116
OPT
R129
1k
R108
24.9Ω
R123
24.9Ω
C104
0.1µF
VCC
VEE
R124
49.9Ω
C100
39pF
C112
39pF
EN
C102
1000pF
dc2326 F02
R113
0Ω
R119
1k
DC Power
TheDC2520A requires ±9VDC and draws +132mA/–52mA.
Most of the supply current is consumed by the FPGA,
opamps, regulators and discrete logic on the board. The
±9VDC input voltage powers the ADC through LT1763
regulators which provide protection against accidental
reverse bias. Additional regulators provide power for the
FPGA and opamps.
Clock Source
You must provide a low jitter 2.5VP-P sine or square wave
to the clock input, J1. The clock input is AC coupled so the
DC level of the clock signal is not important. A generator
such as the Rohde & Schwarz SMB100A high speed clock
source is recommended to drive the clock input. Even a
good generator can start to produce noticeable jitter at
low frequencies. Therefore it is recommended for lower
sample rates to divide down a higher frequency clock to
the desired sample rate. The ratio of clock frequency to
conversion rate is shown in the Assembly Options table. If
the clock input is to be driven with logic, it is recommended
that the 49.9Ω termination resistor (R4) be removed.
Driving R4 with discrete logic may result in slow rising
edges. These slow rising edges may compromise the SNR
of the converter in the presence of high-amplitude higher
frequency input signals.
Data Output
Parallel data output from this board (0V to 2.5V default),
if not connected to the DC890, can be acquired by a logic
analyzer, and subsequently imported intoa spreadsheet, or
mathematical package depending on what form of digital
signal processing is desired. Alternatively, the data can
be fed directly into an application circuit. Use pin 50 of
P1 to latch the data. The data should be latched using the
negative edge of this signal. The data output signal levels
at P1 can also be increased to 0V-3.3V if the application
circuit requires a higher voltage. This is accomplished by
moving JP2 to the 3.3V position.
Figure 2. 0V–4.096V Single-Ended to Fully Differential DC Coupled Driver

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DEMO MANUAL DC2520A
Reference
The default reference is the LTC2344 internal 4.096V
reference. Alternatively, if a higher reference voltage is
desired, the LTC6655-5 reference (U7) can be used by
setting the REF jumper (JP1) to the EXT position and
installing a 0Ω resistor in the R7 position. This should
result in better SNR performance but may slightly degrade
the THD performance of the LTC2345.
Analog Inputs
All eight inputs have the same driver circuitry. The circuit of
Figure 2 shows the driver for AIN0. It provides aDC coupled
single-ended to fully differential output to the analog inputs
of the LTC2344 with a maximum 0V-4.096V input signal.
DC890 Data Collection
For SINAD, THD or SNR testing a low noise, low distor-
tion generator such as the B&K Type 1051 or Stanford
Research SR1 should be used. A low jitter RF oscillator
such as the Rohde & Schwarz SMB100A is used to drive
the clock input. This demo board is tested in house by
attempting to duplicate the FFT plot shown in Typical
Performance Characteristics section of the LTC2344 data
sheet. This involves using a 68.8MHz clock source, along
with asinusoidal generator at a frequency of approximately
2kHz. The input signal level is approximately –1dBFS. A
typical FFT obtained with DC2520A is shown in Figure 3.
Note that to calculate the real SNR, the signal level (F1
amplitude = –1.081dB) has to be added back to the SNR
that PScope displays. With the example shown in Figure 3
this means that the actual SNR would be 93.59dB instead
of the 92.51dB that PScope displays. Taking the RMS sum
of the recalculated SNR and the THD yields a SINAD of
93.50dB which is fairly close to the typical number for
this ADC.
DC2520A SETUP
To change the default settings for the LTC2344 in PScope,
click on the Set Demo Bd Options button in the PScope
tool bar shown in Figure 4. This will open the Configure
Channels menu of Figure 5. In this menu it is possible to
set the input signal range setting for each channel. There
is also a button to return PScope to the default DC2520A
settings which are optimized for the default hardware
settings of the DC2520A.
There are a number of scenarios that can produce mislead-
ing results when evaluating an ADC. One that is common
is feeding the converter with an input frequency that is
a sub-multiple of the sample rate, and which will only
exercise a small subset of the possible output codes.
The proper method is to pick an M/N frequency for the
input sine wave frequency. N is the number of samples
in the FFT. M is a prime number between one and N/2.
Multiply M/N by the sample rate to obtain the input sine
wave frequency. Another scenario that can yield poor
results is if you do not have a signal generator capable of
ppm frequency accuracy or if it cannot be locked to the
clock frequency. You can use an FFT with windowing to
reduce the “leakage” or spreading of the fundamental, to
get a close approximation of the ADC performance. If an
amplifier or clock source with poor phase noise is used,
the windowing will not improve the SNR.
DC590/DC2026 Data Collection
Due to the relatively low and somewhat unpredictable
sample rate of the DC590/DC2026 its usefulness is lim-
ited to noise measurement and data collection of slowly
moving signals. A typical data capture and histogram are
shown in Figure 6. To change the default settings for the
LTC2344 in QuikEval, click on the Sequence Config but-
ton. This will open the Config Dialog menu of Figure 7.
In this menu it is possible to set the input signal range for
each sequence. There is also a button to return QuikEval
to the default DC2520A settings which are optimized for
the default hardware settings of the DC2520A.

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DEMO MANUAL DC2520A
DC2520A SETUP
Layout
As with any high performance ADC, this part is sensitive
to layout. The area immediately surrounding the ADC on
the DC2520A should be used as a guideline for placement,
and routing of the various components associated with
the ADC. Here are some things to remember when laying
out a board for the LTC2344. A ground plane is necessary
to obtain maximum performance. Keep bypass capacitors
as close to supply pins as possible. Use individual low
impedance returns for all bypass capacitors. Use of a
symmetrical layout around the analog inputs will minimize
the effectsof parasitic elements. Shield analog input traces
with ground to minimize coupling from other traces. Keep
traces as short as possible.
Component Selection
When driving a low noise, low distortion ADC such as the
LTC2344, component selection is important so as to not
degrade performance. Resistors should have low values
to minimize noise and distortion. Metal film resistors are
recommended to reduce distortion caused by self heat-
ing. Because of their low voltage coefficients, to further
reduce distortion NPO or silver mica capacitors should be
used. Any buffer used to drive the LTC2344 should have
low distortion, low noise and a fast settling time such as
the LT6237.

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DEMO MANUAL DC2520A
DC2520A SETUP
Figure 3. PScope Screen Shot
Figure 4. PScope Tool Bar

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DEMO MANUAL DC2520A
DC2520A SETUP
Figure 5. PScope Configuration Menu

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DEMO MANUAL DC2520A
DC2520A SETUP
Figure 6. QuikEval Screen Shot
Figure 7. QuikEval Configuration Menu

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DEMO MANUAL DC2520A
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
DC2520A CONNECTORS
DC2520A JUMPERS
Definitions
JP1: REF selects INT or EXT reference for the ADC. The
default setting is INT.
JP2: VCCIO sets the output levels at P1 to either 3.3V
or 2.5V. Use 2.5V to interface to the DC890 which is the
default setting. Use 3.3V to interface to the DC2026.
JP3: I/O selects LVDS or CMOS logic levels. The default
setting is CMOS. Only CMOS is currently supported.
Definitions
P1: DC890 interface is used to communicate with the
DC890 controller.
J1: CLK provides the master clock for the DC2520A when
interfaced to the DC890.
J2: FPGA PROGRAM is used to program the FPGA. This
is for factory use only.
JP4: EEPROM is for factory use only. The default posi-
tion is WP.
JP5-JP6: AIN0-AIN3 can be used to short individual AIN
inputs to ground or can be used drive the individual AIN
inputs. The default is to leave these open.
JP13-JP14: Coupling selects AC or DC coupling for VIN1
and VIN2. Default setting is DC.
JP15: Sets VCM for the single-end to differential drivers
of AIN0-AIN3
J3: JTAG is for factory use only.
J4: DC590/DC2026 interface is used to communicate with
the DC2026 Linduino controller or DC590.
J5 and J6: Provide analog input voltages to AIN0-AIN3
of the ADC.
J7: Routes the signals of J5 and J6 to AIN0-AIN3.

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DEMO MANUAL DC2520A
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
[phone] ●FAX: [phone] ●www.linear.com
 LINEAR TECHNOLOGY CORPORATION 2016
LT 0516 • PRINTED IN USA
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in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including but not limited to product safety
measures typically found in finished commercial goods. As a prototype, this product does not fall within the scope of the European Union
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