Linear MT 525 User manual

1
LT1010
1010fc
Fast ±150mA Power Buffer
The LT
®
1010 is a fast, unity-gain buffer that can increase
the output capability of existing IC op amps by more than
an order of magnitude. This easy-to-use part makes fast
amplifiers less sensitive to capacitive loading and reduces
thermal feedback in precision DC amplifiers.
Designed to be incorporated within the feedback loop, the
buffer can isolate almost any reactive load. Speed can be
improved with a single external resistor. Internal operat-
ing currents are essentially unaffected by the supply
voltage range. Single supply operation is also practical.
This monolithic IC is supplied in 8-pin miniDIP, plastic
TO-220 and 8-pin DFN packages. The low thermal resis-
tance power package is an aid in reducing operating
junction temperatures.
■
20MHz Bandwidth
■
75V/µs Slew Rate
■
Drives ±10V into 75Ω
■
5mA Quiescent Current
■
Drives Capacitive Loads > 1µF
■
Current and Thermal Limit
■
Operates from Single Supply ≥4.5V
■
Very Low Distortion Operation
■
Available in 8-Pin miniDIP, Plastic TO-220
and Tiny 3mm ×3mm ×0.75mm 8-Pin DFN
Packages
■
Boost Op Amp Output
■
Isolate Capacitive Loads
■
Drive Long Cables
■
Audio Amplifiers
■
Video Amplifiers
■
Power Small Motors
■
Operational Power Supply
■
FET Driver
Very Low Distortion Buffered Preamplifier
FEATURES
DESCRIPTIO
U
APPLICATIO S
U
TYPICAL APPLICATIO
U
–
+
LT1056CN8 LT1010CT
7
IN OUT OUTPUT
BOOST
V
+
V
+
1010 TA01
LM334
I
SET
= 2mA
R
SET
33.2Ω
1%
NOTE 1: ALL RESISTORS 1% METAL FILM
NOTE 2: SUPPLIES WELL BYPASSED AND LOW Z
O
V
–
V
–
R7
50Ω
C2
22pF
C1
22pF
V
+
18V
V
+
–18V
R6
100Ω
R8
100Ω
R4
10k
R3
1k
R1
1k
R2
1M
3
2
4
6
FREQUENCY (Hz)
0.1
HARMONIC DISTORTION (%)
0.2
0.4
10 1k 10k 100k
1010 TA02
0
100
0.3
VOUT = 10VP-P
RL= 400Ω
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.

2
LT1010
1010fc
(Note 1)
Total Supply Voltage .............................................. ±22V
Continuous Output Current .............................. ±150mA
Input Current (Note 3) ....................................... ±40mA
Operating Junction Temperature Range
LT1010C ............................................... 0°C to 100°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
ABSOLUTE AXI U RATI GS
WWWU
PACKAGE/ORDER I FOR ATIO
UU
W
100% Thermal Limit Burn In–LT1010CT
ORDER PART
NUMBER
LT1010CN8 LT1010CT
1
2
3
4
8
7
6
5
TOP VIEW
V
+
BIAS
OUT
NC
INPUT
NC
V
–
NC
N8 PACKAGE
8-LEAD PDIP
T
JMAX
= 100°C, θ
JC
= 45°C/W, θ
JA
= 100°C/W
T PACKAGE
5-LEAD PLASTIC TO-220
OUTPUT
BIAS
V–(TAB)
V+
INPUT
FRONT VIEW
5
4
3
2
1
V–
T
JMAX
= 125°C, θ
JC
= 3°C/W, θ
JA
= 50°C/W
PRECO DITIO I G
U
UU
SYMBOL PARAMETER CONDITIONS (Note 4) MIN TYP MAX UNITS
V
OS
Output Offset Voltage (Note 4) 0 150 mV
●–20 220 mV
V
S
= ±15V, V
IN
= 0V 20 100 mV
I
B
Input Bias Current I
OUT
= 0mA 0 250 µA
I
OUT
≤150mA 0 500 µA
●0 800 µA
A
V
Large-Signal Voltage Gain ●0.995 1.00 V/V
R
OUT
Output Resistance I
OUT
= ±1mA 5 10 Ω
I
OUT
= ±150mA 5 10 Ω
●12 Ω
Slew Rate V
S
= ±15V, V
IN
= ±10V, 75 V/µs
V
OUT
= ±8V, R
L
= 100Ω
ELECTRICAL CHARACTERISTICS
The ●indicates specifications which apply over the full operating
temperature range, otherwise specifications are at TA= 25°C. (See Note 4. Typical values in curves.)
Consult LTC Marketing for parts specified with wider operating temperature ranges.
TOP VIEW
9
DD PACKAGE
8-LEAD (3mm ×3mm) PLASTIC DFN
5
6
7
8
4
3
2
1V
+
BIAS
OUT
NC
INPUT
NC
V
–
NC
T
JMAX
= 100°C, θ
JC
= 3°C/W, θ
JA
= 40°C/W
EXPOSED PAD (PIN 9) V
–
CAN BE SOLDERED TO PCB
TO REDUCE THERMAL RESISTANCE (NOTE 7)
DD PART
MARKING
LT1010CDD LBWZ
ORDER PART
NUMBER
ORDER PART
NUMBER
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/

3
LT1010
1010fc
SYMBOL PARAMETER CONDITIONS (Note 4) MIN TYP MAX UNITS
V
SOS+
Positive Saturation Offset I
OUT
= 0 (Note 5) 1.0 V
●1.1 V
V
SOS–
Negative Saturation Offset I
OUT
= 0 (Note 5) 0.2 V
●0.3 V
R
SAT
Saturation Resistance I
OUT
= ±150mA (Note 5) 22 Ω
●28 Ω
V
BIAS
Bias Terminal Voltage R
BIAS
= 20Ω(Note 6) 700 840 mV
●560 880 mV
I
S
Supply Current I
OUT
= 0, I
BIAS
= 0 9 mA
●10 mA
ELECTRICAL CHARACTERISTICS
The ●indicates specifications which apply over the full operating
temperature range, otherwise specifications are at TA= 25°C. (See Note 4. Typical values in curves.)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: For case temperatures above 25°C, dissipation must be derated
based on a thermal resistance of 25°C/W for the T package, 130°C/W for
the N8 package and 40°C/W for the DD package for
ambient temperatures
above 25°C. See Applications Information.
Note 3: In current limit or thermal limit, input current increases sharply
with input-output differentials greater than 8V; so input current must be
limited. Input current also rises rapidly for input voltages 8V above V
+
or
0.5V below V
–
.
Note 4: Specifications apply for 4.5V ≤V
S
≤40V,
V
–
+ 0.5V ≤V
IN
≤V
+
– 1.5V and I
OUT
= 0, unless otherwise stated.
Temperature range is 0°C ≤T
J
≤100°C, T
C
≤100°C.
Note 5: The output saturation characteristics are measured with 100mV
output clipping. See Applications Information for determining available
output swing and input drive requirements for a given load.
Note 6: The output stage quiescent current can be increased by
connecting a resistor between the BIAS pin and V
+
. The increase is
equal to the bias terminal voltage divided by this resistance.
Note 7: Thermal resistance varies depending upon the amount of PC board
metal attached to the pin (Pin 9) of the device. θ
JA
is specified for a certain
amount of 1oz copper metal trace connecting to Pin 9 as described in the
thermal resistance tables in the Applications Information section.

4
LT1010
1010fc
Bandwidth Phase Lag Phase Lag
QUIESCENT CURRENT (mA)
0
0
FREQUENCY (MHz)
20
50
10 20
1010 G01
10
40
30
30 40
R
L
= 200Ω
R
L
= 50Ω
V
IN
= 100mV
P-P
C
L
100pF
A
V
= –3dB
T
J
= 25°C
FREQUENCY (MHz)
25
5
10
PHASE LAG (DEGREES)
20
50
10 20
1010 G02
RL= 50Ω
RL= 200Ω
CL= 100pF
RS= 50Ω
IBIAS = 0
TJ= 25°C
FREQUENCY (MHz)
25
5
10
PHASE LAG (DEGREES)
20
50
10 20
1010 G03
RL= 50ΩRL= 200Ω
CL= 100pF
RS= 50Ω
RBIAS = 20Ω
TJ= 25°C
Small-Step Response Output Impedance Capacitive Loading
TIME (ns)
0
–150
VOLTAGE CHANGE (mV)
–100
–50
0
50
150
10 20
1010 G04
30
100
RL= 100Ω
TJ= 25°C
INPUT OUTPUT
FREQUENCY (MHz)
0.1
1
OUTPUT IMPEDANCE (Ω)
10
100
1 10 100
1010 G05
I
BIAS
= 0
T
J
= 25°C
FREQUENCY (MHz)
0.1
–20
VOLTAGE GAIN (dB)
0
10
1 10 100
1010 G06
–10
RS= 50Ω
IBIAS = 0
TJ= 25°C
100pF3nF
0.1µF
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Slew Response Negative Slew Rate Supply Current
TIME (ns)
–50
OUTPUT VOLTAGE (V)
–5
0
5
100 200
1010 G07
–10
–15
–20 0 50 150
10
15
20
250
V
S
= ±15V
R
L
= 100Ω
T
J
= 25°C
f ≤1MHz
POSITIVE
NEGATIVE
I
BIAS
= 0
R
BIAS
= 20Ω
QUIESCENT CURRENT (mA)
0
SLEW RATE (V/µs)
200
300
40
1010 G08
100
010 20 30
400 V
S
= ±15V
0 ≥V
IN
≥–10V
R
L
= 200Ω
R
L
= 100Ω
R
L
= 50Ω
FREQUENCY (MHz)
0
SUPPLY CURRENT (mA)
80
60
40
20
0
4
1010 G09
123 5
V
S
= ±15V
V
IN
= ±10V
I
L
= 0
T
C
= 25°C

5
LT1010
1010fc
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Output Offset Voltage Input Bias Current Input Bias Current
TEMPERATURE (°C)
–50
OFFSET VOLTAGE (mV)
100
150
150
1010 G10
50
0050 100
200 V
IN
= 0
V
+
= 38V
V
–
= –2V
V
+
= 2V
V
–
= –38V
TEMPERATURE (°C)
–50
BIAS CURRENT (µA)
100
150
150
1010 G10
50
0050 100
200 V
IN
= 0
V
+
= 38V
V
–
= –2V
V
+
= 2V
V
–
= –38V
OUTPUT CURRENT (mA)
–150
BIAS CURRENT (µA)
100
0100
1010 G12
50
0–100 –50 50
150
200
150
V
S
= ±15V
R
L
= 75Ω
T
J
= 125°C
T
J
= 25°C
T
J
= –55°C
Voltage Gain Output Resistance Output Noise Voltage
TEMPERATURE (°C)
–50
0.997
GAIN (V/V)
0.998
0.999
050
100 150
1010 G13
1.000 IOUT = 0
VS= 40V
VS= 4.5V
TEMPERATURE (°C)
–50
0
OUTPUT RESISTANCE (Ω)
4
8
050
100 150
1010 G14
12
2
6
10
IOUT ≤150mA
FREQUENCY (Hz)
10
100
NOISE VOLTAGE (nV/√Hz)
150
200
100 1k 10k
1010 G15
50
0
TJ= 25°C
RS= 1k
RS= 50Ω
Positive Saturation Voltage Negative Saturation Voltage Supply Current
TEMPERATURE (°C)
–50
SATURATION VOLTAGE (V)
2
3
150
1010 G16
1
0050 100
4
I
L
= 150mA
I
L
= 50mA
I
L
= 5mA
TEMPERATURE (°C)
–50
SATURATION VOLTAGE (V)
2
3
150
1010 G16
1
0050 100
4
I
L
= –150mA
I
L
= –50mA
I
L
= –5mA
TOTAL SUPPLY VOLTAGE (V)
0
SUPPLY CURRENT (mA)
5
6
40
1010 G18
4
310 20 30
7
T
J
= –55°C
T
J
= 25°C
T
J
= 125°C
V
IN
= 0
I
OUT
= 0
I
BIAS
= 0

6
LT1010
1010fc
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Bias Terminal Voltage Total Harmonic Distortion Total Harmonic Distortion
TEMPERATURE (°C)
–50
0.5
BIAS TERMINAL VOLTAGE (V)
0.7
1.0
050
1010 G19
0.6
0.9
0.8
100 150
V
S
= ±20V
R
BIAS
= 100Ω
R
BIAS
= 20Ω
OUTPUT VOLTAGE (V
P-P
)
0.1
0.2
HARMONIC DISTORTION (%)
0.3
0.4
1 10 100
1010 G20
0.1
0
R
L
= 50Ω
f = 10kHz
V
S
= ±15V
T
C
= 25°C
I
BIAS
= 0 R
BIAS
= 50Ω
FREQUENCY (kHz)
1
0.4
HARMONIC DISTORTION (%)
0.6
0.8
10 100 1000
1010 G21
0.2
0
IBIAS = 0
VS= ±15V
VOUT = ±10V
TC= 25°C
RL= 50Ω
RL= 100Ω
Shorted Input Characteristics Peak Power Capability Peak Output Current
INPUT VOLTAGE (V)
–15
INUPT CURRENT (mA)
0
010
1010 G22
–25
–50 –10 –5 5
25
50
15
V
S
= ±15V
V
OUT
= 0
T
J
= 25°C
PULSE WIDTH (ms)
1
0
PEAK POWER (W)
2
4
6
8
10 100
1010 G23
10 T
C
= 85°C
TO-220
TEMPERATURE (°C)
–50
0
OUTPUT CURRENT (A)
0.2
0.5
050
1010 G24
0.1
0.4
0.3
100 150
VS= ±15V
VOUT = 0
SINK
SOURCE

7
LT1010
1010fc
APPLICATIO S I FOR ATIO
WUUU
General
These notes briefly describe the LT1010 and how it is
used; a detailed explanation is given elsewhere
1
. Empha-
sis here will be on practical suggestions that have resulted
from working extensively with the part over a wide range
of conditions. A number of applications are also outlined
that demonstrate the usefulness of the buffer beyond that
of driving a heavy load.
Design Concept
The schematic below describes the basic elements of the
buffer design. The op amp drives the output sink transis-
tor, Q3, such that the collector current of the output
follower, Q2, never drops below the quiescent value (de-
termined by I
1
and the area ratio of D1 and D2). As a result,
the high frequency response is essentially that of a simple
follower even when Q3 is supplying the load current. The
internal feedback loop is isolated from the effects of
capacitive loading by a small resistor in the output lead.
–
+
R1
D2
I2
D1
A1
Q3
INPUT
OUTPUT
V+
V–
1010 AI01
BIAS
I1
Q1
Q2
idealized buffer with the unloaded gain specified for the
LT1010. Otherwise, it has zero offset voltage, bias current
and output resistance. Its output also saturates to the
internal supply terminals
2
.
1
R. J. Widlar, “Unique IC Buffer Enhances Op Amp Designs; Tames Fast Amplifiers,”
Linear Technology Corp. TP-1 , April, 1984.
2
See electrical characteristics section for guaranteed limits.
The scheme is not perfect in that the rate of rise of sink
current is noticeably less than for source current. This can
be mitigated by connecting a resistor between the bias
terminal and V
+
, raising quiescent current. A feature of the
final design is that the output resistance is largely indepen-
dent of the follower quiescent current or the output load
current. The output will also swing to the negative rail,
which is particularly useful with single supply operation.
Equivalent Circuit
Below 1MHz, the LT1010 is quite accurately represented
by the equivalent circuit shown here for both small- and
large-signal operation. The internal element, A1, is an
R
OUT
R′
R′R′= R
SAT
– R
OUT
V
SOS+
V
+
V
–
OUTPUTINPUT
I
B
V
OS
V
SOS–
1010 AI02
+
A1
Loaded voltage gain can be determined from the unloaded
gain, A
V
, the output resistance, R
OUT
, and the load resis-
tance, R
L
, using:
AAR
RR
VL VL
OUT L
=+
Maximum positive output swing is given by:
VVV R
RR
OUT SOS L
SAT L
+++
=+
(– )
The input swing required for this output is:
VV R
RVV
IN OUT OUT
L
OS OS
++
=+
⎛
⎝
⎜⎞
⎠
⎟+∆1–
where ∆V
OS
is the 100mV clipping specified for the
saturation measurements. Negative output swing and
input drive requirements are similarly determined.
Supply Bypass
The buffer is no more sensitive to supply bypassing than
slower op amps as far as stability is concerned. The 0.1µF
disc ceramic capacitors usually recommended for op
amps are certainly adequate for low frequency work. As
always, keeping the capacitor leads short and using a

8
LT1010
1010fc
APPLICATIO S I FOR ATIO
WUUU
without limiting. Because of this, it is capable of power
dissipation in excess of its continuous ratings.
Normally, thermal overload protection will limit dissipa-
tion and prevent damage. However, with more than 30V
across the conducting output transistor, thermal limiting
is not quick enough to ensure protection in current limit.
The thermal protection is effective with 40V across the
conducting output transistor as long as the load current is
otherwise limited to 150mA.
Drive Impedance
When driving capacitive loads, the LT1010 likes to be
driven from a low source impedance at high frequencies.
Certain low power op amps (e.g., the LM10) are marginal
in this respect. Some care may be required to avoid
oscillations, especially at low temperatures.
Bypassing the buffer input with more than 200pF will solve
the problem. Raising the operating current also works.
Parallel Operation
Parallel operation provides reduced output impedance,
more drive capability and increased frequency response
under load. Any number of buffers can be directly paral-
leled as long as the increased dissipation in individual
units caused by mismatches of output resistance and
offset voltage is taken into account.
When the inputs and outputs of two buffers are connected
together, a current, ∆I
OUT
, flows between the outputs:
∆=+ IVV
RR
OUT OS OS
OUT OUT
12
12
–
where V
OS
and R
OUT
are the offset voltage and output
resistance of the respective buffers.
Normally, the negative supply current of one unit will
increase and the other decrease, with the positive supply
current staying the same. The worst-case (V
IN
→V
+
)
increase in standby dissipation can be assumed to be
∆I
OUT
V
T
, where V
T
is the total supply voltage.
Offset voltage is specified worst case over a range of
supply voltages, input voltage and temperature. It would
ground plane is prudent, especially when operating at high
frequencies.
The buffer slew rate can be reduced by inadequate supply
bypass. With output current changes much above
100mA/µs, using 10µF solid tantalum capacitors on both
supplies is good practice, although bypassing from the
positive to the negative supply may suffice.
When used in conjunction with an op amp and heavily
loaded (resistive or capacitive), the buffer can couple into
supply leads common to the op amp causing stability
problems with the overall loop and extended settling time.
Adequate bypassing can usually be provided by 10µF solid
tantalum capacitors. Alternately, smaller capacitors could
be used with decoupling resistors. Sometimes the op amp
has much better high frequency rejection on one supply,
so bypass requirements are less on this supply.
Power Dissipation
In many applications the LT1010 will require heat sink-
ing. Thermal resistance, junction to still air is 100°C/W
for the TO-220 package and 130°C/W for the miniDIP
package. Circulating air, a heat sink or mounting the
package to a printed circuit board will reduce thermal
resistance.
In DC circuits, buffer dissipation is easily computed. In AC
circuits, signal waveshape and the nature of the load
determine dissipation. Peak dissipation can be several
times average with reactive loads. It is particularly impor-
tant to determine dissipation when driving large load
capacitance.
With AC loading, power is divided between the two output
transistors. This reduces the effective thermal resistance,
junction to case to 15°C/W for the TO-220 package as long
as the peak rating of neither output transistor is exceeded.
The typical curves indicate the peak dissipation capabili-
ties of one output transistor.
Overload Protection
The LT1010 has both instantaneous current limit and
thermal overload protection. Foldback current limiting has
not been used, enabling the buffer to drive complex loads

9
LT1010
1010fc
be unrealistic to use these worst-case numbers above
because paralleled units are operating under identical
conditions. The offset voltage specified for V
S
= ±15V,
V
IN
= 0V and T
A
= 25°C will suffice for a worst-case
condition.
APPLICATIO S I FOR ATIO
WUUU
At lower frequencies, the buffer is within the feedback loop
so that its offset voltage and gain errors are negligible. At
higher frequencies, feedback is through C
F
, so that phase
shift from the load capacitance acting against the buffer
output resistance does not cause loop instability.
Stability depends upon the RFCFtime constant or the
closed-loop bandwidth. With an 80kHz bandwidth, ring-
ing is negligible for CL= 0.068µF and damps rapidly for
CL= 0.33µF. The pulse response is shown in the graph.
A1
LT1010
VIN
V–
A2
LT1010
V+
IS
∆IOUT
IS + ∆IOUT IS – ∆IOUT
VOUT
1010 AI03
IS
A2
LT1010
R
S
R
F
20k
V
IN
C
F
100pF
C
L
1010 AI04
V
OUT
–
+
A1
LT1007
Output load current will be divided based on the output
resistance of the individual buffers. Therefore, the avail-
able output current will not quite be doubled unless output
resistances are matched. As for offset voltage, the 25°C
limits should be used for worst-case calculations.
Parallel operation is not thermally unstable. Should one
unit get hotter than its mates, its share of the output and
its standby dissipation will decrease.
As a practical matter, parallel connection needs only some
increased attention to heat sinking. In some applications,
a few ohms equalization resistance in each output may be
wise. Only the most demanding applications should re-
quire matching, and then just of output resistance at 25°C.
Isolating Capacitive Loads
The inverting amplifier below shows the recommended
method of isolating capacitive loads. Noninverting ampli-
fiers are handled similarly.
TIME (µs)
0
OUTPUT VOLTAGE (V)
0
200
1010 AI05
0
50 100 150
5
–5
–5
5
C
L
= 0.068µF
C
L
= 0.33µF
Pulse Response
Small-signal bandwidth is reduced by CF, but consider-
able isolation can be obtained without reducing it below
the power bandwidth. Often, a bandwidth reduction is
desirable to filter high frequency noise or unwanted
signals.
A2
LT1010
R
F
2k
R
S
2k
V
IN
C
F
1nF
C
L
1010 AI06
V
OUT
–
+
A1
LT118A
The follower configuration is unique in that capacitive
load isolation is obtained without a reduction in small-
signal bandwidth, although the output impedance of the
buffer comes into play at high frequencies. The precision
unity-gain buffer above has a 10MHz bandwidth without
capacitive loading, yet it is stable for all load capacitance
to over 0.3µF, again determined by RFCF.

10
LT1010
1010fc
APPLICATIO S I FOR ATIO
WUUU
This is a good example of how fast op amps can be made
quite easy to use by employing an output buffer.
Integrator
A lowpass amplifier can be formed just by using large CF
in the inverter described earlier, as long as the increasing
closed-loop output impedance above the cutoff frequency
is not a problem and the op amp is capable of supplying
the required current at the summing junction.
A2
LT1010
R
F
20k
C
F
500pF
C
I
I
IN
1010 AI07
V
OUT
–
+
A1
LT1012
BIAS
+
LT1010
22µF+
22µF
TYPICAL SPECIFICATIONS
1VP-P INTO 75Ω
AT A = 2
0.5dB TO 10MHz
3dB DOWN AT 16MHz
AT A = 10
0.5dB TO 4MHz
–3dB = 8MHz
+
68µF
1010 AI08
PEAKING
5pF to 25pF
25Ω
900Ω
OUTPUT
(75Ω)
0.01µF
1k
GAIN SET
5.1k
Q1, Q2: 2N3866
–15V
8.2k
15V
–15V
Q2Q1INPUT
stage. Feedback is arranged in the conventional manner,
although the 68µF-0.01µF combination limits DC gain to
unity for all gain settings. For applications sensitive to
NTSC requirements, dropping the 25Ωoutput stage bias
value will aid performance.
If the integrating capacitor must be driven from the buffer
output, the circuit above can be used to provide capacitive
load isolation. As before, the stability with large capacitive
loads is determined by RFCF.
Wideband Amplifiers
This simple circuit provides an adjustable gain video
amplifier that will drive 1VP-P into 75Ω. The differential
pair provides gain with the LT1010 serving as an output
A2
LT1010
R1
100Ω
R2
800Ω
C1
15pF
VIN
1010 AI09
VOUT
–
+
A1
HA2625
A2
LT1010
R1
400Ω
R2
1.6k
INPUT
1010 AI10
OUTPUT
–
+
A1
HA2625
This shows the buffer being used with a wideband ampli-
fier that is not unity-gain stable. In this case, C1 cannot be
used to isolate large capacitive loads. Instead, it has an
optimum value for a limited range of load capacitances.
The buffer can cause stability problems in circuits like
this. With the TO-220 packages, behavior can be im-
proved by raising the quiescent current with a 20Ω
resistor from the bias terminal to V+. Alternately, devices
in the miniDIP can be operated in parallel.
It is possible to improve capacitive load stability by
operating the buffer class A at high frequencies. This is
done by using quiescent current boost and bypassing the
bias terminal to V–with more than 0.02µF.
Putting the buffer outside the feedback loop as shown
here will give capacitive load isolation, with large output
capacitors only reducing bandwidth. Buffer offset, re-
ferred to the op amp input, is divided by the gain. If the
load resistance is known, gain error is determined by the
output resistance tolerance. Distortion is low.

11
LT1010
1010fc
APPLICATIO S I FOR ATIO
WUUU
current boost. The appearance is always worse with fast
rise signal generators than in practical applications.
Track and Hold
The 5MHz track and hold shown here has a 400kHz power
bandwidth driving ±10V. A buffered input follower drives
the hold capacitor, C4, through Q1, a low resistance FET
switch. The positive hold command is supplied by TTL
logic with Q3 level shifting to the switch driver, Q2. The
output is buffered by A3.
When the gate is driven to V –for HOLD, it pulls charge out
of the hold capacitor. A compensating charge is put into
the hold capacitor through C3. The step into hold is made
independent of the input level with R7 and adjusted to zero
with R10.
Since internal dissipation can be quite high when driving
fast signals into a capacitive load, using a buffer in a power
package is recommended. Raising buffer quiescent cur-
rent to 40mA with R3 improves frequency response.
This circuit is equally useful as a fast acquisition sample
and hold. An LT1056 might be used for A3 to reduce drift
in hold because its lower slew rate is not usually a problem
in this application.
Current Sources
A standard op amp voltage to current converter with a
buffer to increase output current is shown here. As usual,
A3
LT1010
A2
LT1010
R2
200Ω
R1
50Ω
R3
800Ω
R4
39Ω
R5
39Ω
C1
20pF
INPUT
1010 AI11
OUTPUT 1
OUTPUT 2
–
+
A1
HA2625
OTHER
SLAVES
The 50Ωvideo line splitter here puts feedback on one
buffer with the others slaved. Offset and gain accuracy of
slaves depend on their matching with master.
When driving long cables, including a resistor in series
with the output should be considered. Although it reduces
gain, it does isolate the feedback amplifier from the effects
of unterminated lines which present a resonant load.
When working with wideband amplifiers, special atten-
tion should
always be paid to supply bypassing, stray
capacitance and keeping leads short. Direct grounding of
test probes, rather than the usual ground lead, is abso-
lutely necessary for reasonable results.
The LT1010 has slew limitations that are not obvious from
standard specifications. Negative slew is subject to
glitching, but this can be minimized with quiescent
A2
LT1010
–
+
–
+
A3
LT118A
A4
LT118A
C1
50pF
C2
150pF
HOLD
R2
2k
D1
HP2810
Q3
2N2907
V
–
Q1
2N5432
SD
R4
2k
Q2
2N2222
R8
5k
R9
10k
D2*
6V
*2N2369 EMITTER BASE JUNCTION
OUTPUT
R10
50k
R5
1k
R6
1k
C4
1nF
C3
100pF
C5
10pF
R1
2k
R3
20Ω
INPUT
V
+
–
+
A1
LT118A
R11
6.2k
1010 AI12
R7
200k

12
LT1010
1010fc
excellent matching of the feedback resistors is required to
get high output resistance. Output is bidirectional.
APPLICATIO S I FOR ATIO
WUUU
A2
LT1010
R3
100k
0.01%
V2
R1
100k
0.01%
R2
100k
0.01%
R4
100k
0.01%
R4
10Ω
0.1%
V1
1010 AI13
I
OUT
–
+
A1
LT1012
R2(V2 – V1)
R1R4
I
OUT
=
A2
LT1010
R1
10Ω
0.1%
VIN
10R1
IOUT =
–
+
VIN
IOUT
1010AI14
6
72
3
5
A1
LM163
×10
This circuit uses an instrumentation amplifier to eliminate
the matched resistors. The input is not high impedance
and must be driven from a low impedance source like an
op amp. Reversal of output sense can be obtained by
grounding Pin 7 of the LM163 and driving Pin 5.
enables the current regulator to get control of the output
current from the buffer current limit within a microsecond
for an instantaneous short.
In the voltage regulation mode, A1 and A2 act as a fast
voltage follower using the capacitive load isolation tech-
nique described earlier. Load transient recovery as well as
capacitive load stability are determined by C1. Recovery
from short circuit is clean.
Bidirectional current limit can be obtained by adding
another op amp connected as a complement to A3.
Supply Splitter
Dual supply op amps and comparators can be operated
from a single supply by creating an artificial ground at half
the supply voltage. The supply splitter shown here can
source or sink 150mA.
The output capacitor, C2, can be made as large as neces-
sary to absorb current transients. An input capacitor is
also used on the buffer to avoid high frequency instability
that can be caused by high source impedance.
Output resistances of several megohms can be obtained
with both circuits. This is impressive considering the
±150mA output capability. High frequency output charac-
teristics will depend on the bandwidth and slew rate of the
amplifiers. Both these circuits have an equivalent output
capacitance of about 30nF.
Voltage/Current Regulator
This circuit regulates the output voltage at VVuntil the
load current reaches a value programmed by VI. For
heavier loads, it is a precision current regulator.
With output currents below the current limit, the current
regulator is disconnected from the loop by D1 with D2
keeping its output out of saturation. This output clamp
A2
LT1010
D1
1N457
D2
1N457
C1
1nF R3
2Ω
R4
2k
0.1%
–
+
–
+
R2
2k
1010 AI15
A3
LT118A
V
I
10mA/V
V
V
1V/V
R5
2k
0.1%
OUTPUT
R6
99.8k
0.1%
R1
2k
R7
99.8k
0.1%
C2
10pF
A1
LT118A
A1
LT1010
R2
10k
R1
10k
C1
1nF
C3
0.1µF
C2
0.01µF
V
+
/2
1010 AI16
V
+

13
LT1010
1010fc
High Current Booster
The circuit below uses a discrete stage to get 3A output
capacity. The configuration shown provides a clean, quick
way to increase LT1010 output power. It is useful for high
current loads such as linear actuator coils in disk drives.
The 33Ωresistors sense the LT1010’s supply current
with the grounded 100Ωresistor supplying a load for the
LT1010. The voltage drop across the 33Ωresistors
biases Q1 and Q2. Another 100Ωvalue closes a local
feedback loop, stabilizing the output stage. Feedback to
the LT1056 control amplifier is via the 10k value. Q3 and
Q4, sensing across the 0.18Ωunits, furnish current
limiting at about 3.3A.
APPLICATIO S I FOR ATIO
WUUU
signal. The amplified difference between these signals is
used to set Q2’s bias, and hence, Q1’s channel current.
This forces Q1’s VGS to whatever voltage is required to
matchthecircuit’sinput and output potentials.The2000pF
capacitor at A1 provides stable loop compensation. The
RC network in A1’s output prevents it from seeing high
speed edges coupled through Q2’s collector-base junc-
tion. A2’s output is also fed back to the shield around Q1’s
gate lead, bootstrapping the circuit’s effective input ca-
pacitance down to less than 1pF.
Gain-Trimmable Wideband FET Amplifier
A potential difficulty with the previous circuit is that the
gain is not quite unity. The figure labeled A on the next
page maintains high speed and low bias while achieving
a true unity-gain transfer function.
This circuit is somewhat similar except that the Q2-Q3
stage takes gain. A2 DC stabilizes the input-output path
and A1 provides drive capability. Feedback is to Q2’s
emitter from A1’s output. The 1k adjustment allows the
gain to be precisely set to unity. With the LT1010, output
stage slew and full power bandwidth (1VP-P) are 100V/µs
and 10MHz respectively. – 3dBbandwidth exceeds 35MHz.
At A = 10 (e.g., 1k adjustment set at 50Ω), full power
bandwidth stays at 10MHz while the –3dB point falls to
22MHz.
With the optional discrete stage, slew exceeds 1000V/µs
and full power bandwidth (1VP-P) is 18MHz. –3dB band-
width is 58MHz. At A = 10, full power is available to
10MHz, with the – 3dB point at 36MHz.
LT1010
100Ω
33Ω
–15V
33Ω
10k
22µF
15V
100Ω
1k
0.18Ω
1k
0.18Ω
Q1
MJE2955
Q2
MJE3055
OUTPUT
1010 AI17
Q4
2N3904
Q3
2N3906
–
+
LT1056
10k
68pF
INPUT
+
22µF
HEAT SINK OUTPUT TRANSISTORS
+
15pF
A2
LT1010
1k
10k
–5V
5V
3
BA OUTPUT
6
4
–5V
5V
7
0.1µF
2
Q2
2N2222
INPUT Q1
2N5486
–
+
2000pF 0.1µF
1010 AI18
0.01µF
10M 100Ω
A1
LTC1050
10M
Wideband FET Input Stabilized Buffer
The figure below shows a highly stable unity-gain buffer
with good speed and high input impedance. Q1 and Q2
constitute a simple, high speed FET input buffer. Q1
functions as a source follower with the Q2 current source
loadsettingthedrain-sourcechannelcurrent.TheLT1010
buffer provides output drive capability for cables or
whatever load is required. Normally, this open-loop con-
figuration would be quite drifty because there is no DC
feedback. The LTC
®
1050 contributes this function to
stabilize the circuit. It does this by comparing the filtered
circuit output to a similarly filtered version of the input

14
LT1010
1010fc
APPLICATIO S I FOR ATIO
WUUU
–
+
A1
LT1012
A2
LT1010
Q3
2N3906
470Ω
10pF
OUTPUT
1k
50Ω300Ω2k10k10M
INPUT
5.6k
–15V
(A) (B)
3k
3k
3k
–15V
15V
3Ω
3Ω
BA
2N3904
2N3906
10M
1k
15V
Q2
2N3904
Q1
2N5486
1k
GAIN
ADJ
AB
0.002µF
0.1µF
0.1µF
1k
1010 AI19
0.01µF
Gain-Trimmable Wideband FET Amplifier
Figure A. Waveforms Using LT1010 Figure B. Waveforms Using Discrete Stage
10ns/DIV 10ns/DIV
A = 0.2V/DIV
B = 0.2V/DIV
A = 0.2V/DIV
B = 0.2V/DIV
1010 AI20 1010 AI21
Figures A and B show response with both output stages.
The LT1010 is used in Figure A (Trace A = input, Trace B
= output). Figure B uses the discrete stage and is slightly
faster. Either stage provides more than adequate perfor-
mance for driving video cable or data converters and the
LT1012 maintains DC stability under all conditions.
Thermal Considerations for the MiniDIP Package
The miniDIP package requires special thermal consider-
ations since it is not designed to dissipate much power. Be
aware that for applications requiring large output cur-
rents, another package should be used.

15
LT1010
1010fc
APPLICATIO S I FOR ATIO
WUUU
Typical thermal calculations for the miniDIP package are
detailed in the following paragraphs.
For 4.8mA supply current (typical at 50°C, 30V supply
voltage—see supply current graphs) to the LT1010 at
±15V, P
D
= power dissipated in the part is equal to:
(30V)(0.0048A) = 0.144W
The rise in junction is then:
(0.144W)(130°C/W—This is θ
JA
for the N package)
= 18.7°C.
This means that the junction temperature in 50°C ambient
air without driving any current into a load is:
18.7°C + 50°C = 68.7°C
Using the LT1010 to drive 8V DC into a 200Ωload using
±15V power supplies dissipates P
D
in the LT1010 where:
P
VV V
R
VVV W
D
OUT OUT
L
=
()
()
=
()()
Ω=
+
–
–. 15 8 8
200 0 280
This causes the LT1010 junction temperature to rise
another (0.280W)(0.130°C/W) = 36.4°C.
This heats the junction to 68.7°C + 36.4°C = 105.1°C.
Caution: This exceeds the maximum operating tempera-
ture of the device.
An example of 1MHz operation further shows the limita-
tions of the N (or miniDIP) package. For ±15V operation:
P
D
at I
L
= 0 at 1MHz* = (10mA)(30V) = 0.30W
This power dissipation causes the junction to heat from
50°C (ambient in this example) to 50°C + (0.3W)
(130°C/W) = 89°C. Driving 2V
RMS
of 1MHz signal into a
200Ωload causes an additional
PVW
D
=Ω
⎛
⎝
⎜⎞
⎠
⎟
()
=
2
200 15 2 0 130•– .
to be dissipated, resulting in another (0.130W)
(0.130°C/W) = 16.9°C rise in junction temperature to
89°C + 16.9°C = 105.9°C.
Caution: This exceeds the maximum operating tempera-
ture of the device.
Thermal Resistance of DFN Package
For surface mount devices, heat sinking is accomplished
by using the heat spreading capabilities of the PC board
and its copper traces. Copper board stiffeners and plated
through-holes can also be used to spread the heat gener-
ated by power devices.
The following table lists thermal resistance for several
different board sizes and copper areas. All measurements
were taken in still air on 3/32" FR-4 board with one ounce
copper.
Table 1. DFN Measured Thermal Resistance
COPPER AREA THERMAL RESISTANCE
TOPSIDE BACKSIDE BOARD AREA (JUNCTION-TO-AMBIENT)
2500 sq mm 2500 sq mm 2500 sq mm 40°C/W
1000 sq mm 2500 sq mm 2500 sq mm 45°C/W
225 sq mm 2500 sq mm 2500 sq mm 50°C/W
100 sq mm 2500 sq mm 2500 sq mm 62°C/W
For the DFN package, the thermal resistance junction-to-
case (θ
JC
), measured at the exposed pad on the back of the
die, is 16°C/W.
Continuous operation at the maximum supply voltage and
maximum load current is not practical due to thermal
limitations. Transient operation at the maximum supply is
possible. The approximate thermal time constant for a
2500sq mm 3/32" FR-4 board with maximum topside and
backside area for one ounce copper is 3 seconds. This time
constant will increase as more thermal mass is added (i.e.
vias, larger board, and other components).
For an application with transient high power peaks, aver-
age power dissipation can be used for junction tempera-
ture calculations as long as the pulse period is significantly
less than the thermal time constant of the device and
board.
*See Supply Current vs Frequency graph.

16
LT1010
1010fc
DEFI ITIO OF TER S
UW U
Output Offset Voltage: The output voltage measured with
the input grounded (split supply operation).
Input Bias Current: The current out of the input terminal.
Large-Signal Voltage Gain: The ratio of the output volt-
age change to the input voltage change over the specified
input voltage range.*
Output Resistance: The ratio of the change in output
voltage to the change in load current producing it.*
Output Saturation Voltage: The voltage between the out-
put and the supply rail at the limit of the output swing
toward that rail.
Saturation Offset Voltage: The output saturation voltage
with no load.
Saturation Resistance: The ratio of the change in output
saturation voltage to the change in current producing it,
going from no load to full load.*
Slew Rate: The average time rate of change of output
voltage over the specified output range with an input step
between the specified limits.
Bias Terminal Voltage: The voltage between the bias
terminal and V
+
.
Supply Current: The current at either supply terminal with
no output loading.
*Pulse measurements (~1ms) as required to minimize thermal effects.
SCHE ATIC DIAGRA
WW
(Excluding protection circuits)
Q13Q4
Q10Q9
Q3
Q2
Q1
Q12
Q15
C1
30pF
Q19Q17
R9
4k
R1
4k
R13
200Ω
R8
1k
R11
200Ω
R14
7Ω
R10
200Ω
R12
3k
Q14
Q18Q11
Q16
OUTPUT
V–
INPUT
1010 SD
BIAS
V+
Q20
Q8
R4
1k
R7
300Ω
R5
1.5k
R6
15Ω
R3
1k
R2
1k
Q7Q6
Q5
Q21
Q22

17
LT1010
1010fc
U
PACKAGE DESCRIPTIO
DD Package
8-Lead Plastic DFN (3mm ×3mm)
(Reference LTC DWG # 05-08-1698)
3.00 ±0.10
(4 SIDES)
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON TOP AND BOTTOM OF PACKAGE
0.38 ±0.10
BOTTOM VIEW—EXPOSED PAD
1.65 ±0.10
(2 SIDES)
0.75 ±0.05
R = 0.115
TYP
2.38 ±0.10
(2 SIDES)
14
85
PIN 1
TOP MARK
(NOTE 6)
0.200 REF
0.00 – 0.05
(DD) DFN 1203
0.25 ±0.05
2.38 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1.65 ±0.05
(2 SIDES)2.15 ±0.05
0.50
BSC
0.675 ±0.05
3.5 ±0.05
PACKAGE
OUTLINE
0.25 ±0.05
0.50 BSC

18
LT1010
1010fc
N8 Package
8-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510)
U
PACKAGE DESCRIPTIO
N8 1002
.065
(1.651)
TYP
.045 – .065
(1.143 – 1.651)
.130 ±.005
(3.302 ±0.127)
.020
(0.508)
MIN
.018 ±.003
(0.457 ±0.076)
.120
(3.048)
MIN
12 34
87 65
.255 ±.015*
(6.477 ±0.381)
.400*
(10.160)
MAX
.008 – .015
(0.203 – 0.381)
.300 – .325
(7.620 – 8.255)
.325 +.035
–.015
+0.889
–0.381
8.255
()
NOTE:
1. DIMENSIONS ARE INCHES
MILLIMETERS
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)
.100
(2.54)
BSC

19
LT1010
1010fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
T Package
5-Lead Plastic TO-220 (Standard)
(Reference LTC DWG # 05-08-1421)
U
PACKAGE DESCRIPTIO
T5 (TO-220) 0801
.028 – .038
(0.711 – 0.965)
.067
(1.70) .135 – .165
(3.429 – 4.191)
.700 – .728
(17.78 – 18.491)
.045 – .055
(1.143 – 1.397)
.095 – .115
(2.413 – 2.921)
.013 – .023
(0.330 – 0.584)
.620
(15.75)
TYP
.155 – .195*
(3.937 – 4.953)
.152 – .202
(3.861 – 5.131)
.260 – .320
(6.60 – 8.13)
.165 – .180
(4.191 – 4.572)
.147 – .155
(3.734 – 3.937)
DIA
.390 – .415
(9.906 – 10.541)
.330 – .370
(8.382 – 9.398)
.460 – .500
(11.684 – 12.700)
.570 – .620
(14.478 – 15.748)
.230 – .270
(5.842 – 6.858)
BSC
SEATING PLANE
* MEASURED AT THE SEATING PLANE

20
LT1010
1010fc
PART NUMBER DESCRIPTION COMMENTS
LT1206 250mA, 60MHz Current Feedback Amplifier 900V/µs, Excellent Video Characteristics
LT1210 1.1A, 35MHz Current Feedback Amplifier 900V/µs Slew Rate, Stable with Large Capacitive Loads
LT1795 Dual 500mA, 50MHz CFA 500mA I
OUT
ADSL Driver
LT1886 Dual 700MHz, 200mA Op Amp DSL Driver
©LINEAR TECHNOLOGY CORPORATION 1991
LT/LWI 0806 REV C • PRINTED IN THE USA
RELATED PARTS
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